CN105026938A - Signal processing apparatus - Google Patents

Abstract

A 1PPS signal reception unit (101) receives a 1PPS signal. An operation clock generation unit (102) generates an operation clock. A clock deviation measurement unit (103) measures a clock deviation that is a frequency deviation of the operation clock relative to the 1PPS signal. A counter (105) starts a count in accordance with the clock period of the operation clock when the 1PPS signal is inputted. The counter (105) completes one round of count when the count reaches a predetermined count completion value. Thereafter, the counter (105) starts another round of count. A sampling signal generation unit (106) outputs a sampling signal each time the counter (105) completes one round of count. A correction value calculation unit (110) and a change timing calculation unit (111) change the count completion value of any round, on the basis of the clock deviation, , thereby adjusting the output timing of the sampling signal.

Description

signal processing device

technical field

The invention relates to a time synchronization control technology, in particular to a time synchronization control technology in a device for collecting electric power of transmission lines and/or busbars.

Background technique

At present, there are protection and control systems as follows: the power (voltage value, current value) of transmission lines and/or busbars is collected at multiple locations, and when an abnormality is detected based on these power values, the system is immediately disconnected to prevent the spread of the accident.

In this protection control system, in order to reduce the phase deviation of the collected electricity, it is necessary to use a synchronized signal between collection points as a reference for electricity collection.

In protective relay devices in recent years, one computing device (hereinafter also referred to as IED: Intelligent Electronic Device, intelligent electronic device) is connected to multiple data collection devices (hereinafter also referred to as MU: Merging) via a local area network (program bus). Unit, merge unit).

Each MU obtains timing synchronization according to the synchronization signal (1PPS signal: 1Pulse Per Second signal (second pulse signal)), so that the data sampling timing and timestamp value between MUs are consistent.

prior art literature

patent documents

Patent Document 1: Japanese Patent Laid-Open No. 2001-305177

Contents of the invention

The problem to be solved by the invention

The reception period of the 1PPS signal is 1 second intervals.

Therefore, it is necessary for each MU to mount a high-precision crystal oscillator (frequency deviation: ± several ppm) in a clock generation circuit to generate a high-precision clock with a small frequency deviation, and to suppress the deviation of sampling timing between MUs to 1 second ± a few microseconds or less.

Therefore, an inexpensive general-purpose oscillation circuit (frequency deviation accuracy of about ±50 ppm) commonly used in digital circuits cannot be used, and there is a problem of increased cost.

The present invention was made to solve the above-mentioned problems, and an object of the present invention is to enable highly accurate synchronous control even when using a general-purpose oscillation circuit with a frequency deviation of about ±50 ppm.

means to solve the problem

The signal processing device of the present invention has: a pulse signal receiving unit that receives a pulse signal per unit time; an operation clock generation unit that generates an operation clock signal whose clock cycle is smaller than the unit time; The signal receiving part inputs the pulse signal, the operation clock signal is input from the operation clock generation part, and counting corresponding to the clock period of the operation clock signal is started when the pulse signal is input, and the counting is performed when the pulse signal is input. When counting up to the predetermined counting completion value, the counting of one cycle is completed, and the counting of the next cycle is started; the control signal output part outputs the control signal whenever the counter completes the counting of one cycle a clock deviation measurement unit, which receives the pulse signal from the pulse signal receiving unit, inputs the operation clock signal from the operation clock generation unit, and calculates the frequency deviation of the operation clock signal relative to the pulse signal and a counting completion value changing unit, which changes the counting completion value of an arbitrary cycle based on the clock deviation measured by the clock deviation measuring unit, and changes the counting completion value of any cycle by the counting completion value changing unit In the case of the count completion value, the counter completes the counting of the cycle when the counter finishes counting to the changed count completion value, and starts the counting of the next cycle.

Invention effect

According to the present invention, since the clock deviation is measured and the output timing of the control signal is adjusted based on the measured clock deviation, high-precision synchronous control can be performed even if a general-purpose oscillation circuit with a frequency deviation of about ±50 ppm is used.

Description of drawings

FIG. 1 is a diagram showing a configuration example of a data collection device according to Embodiment 1. As shown in FIG.

FIG. 2 is a diagram showing an example of the operation of the clock deviation measuring unit according to Embodiment 1. FIG.

3 is a diagram illustrating delays in output timing of sampling signals due to variations in operating clocks in Embodiment 1. FIG.

4 is a diagram illustrating an example of operations of a correction value calculation unit and a change timing calculation unit according to Embodiment 1. FIG.

FIG. 5 is a diagram showing a configuration example of a data collection device according to Embodiment 2. FIG.

FIG. 6 is a diagram showing a configuration example of a counter changing unit according to Embodiment 2. FIG.

FIG. 7 is a diagram showing a configuration example of a counter change completion notification unit according to Embodiment 2. FIG.

FIG. 8 is a diagram showing an example of a hardware configuration of a data collection device according to Embodiments 1 and 2. FIG.

Detailed ways

Implementation mode 1.

In this embodiment, a data acquisition unit (MU) that calculates a correction value of a counter (sampling period counter) that determines a sampling period of an electric quantity based on a clock frequency deviation will be described.

Thus, even if a general-purpose oscillation circuit with a frequency deviation of about ±50 ppm is used, high-precision synchronization can be achieved.

In addition, generally, oscillators used in assembled equipment can only count in units of tens of nanoseconds to tens of nanoseconds.

When the correction value of the sampling cycle counter is calculated from the deviation of the clock frequency as described above, if the correction value of the counter is in units of several nanoseconds, there is a problem that the resolution of several nanoseconds cannot be performed with the resolution of the crystal oscillator of the MU. adjust.

Therefore, it is necessary to perform several corrections in one time according to the counting unit of the crystal oscillator, and it is necessary to dynamically change the arrangement of the sampling cycle counter during the MU operation.

In the present embodiment, a sampling signal generation method capable of solving the above-mentioned problems and achieving high-precision synchronization between MUs will be described.

FIG. 1 shows a configuration example of a data collection device 100 according to this embodiment.

The data collection device 100 receives the 1PPS signal from the computing device 200 , and transmits data indicating the measured electric quantity to the computing device 200 .

The data collection device 100 corresponds to an example of a signal processing device.

The computing device 200 as an IED detects an abnormality in the power system, and suppresses the spread of the accident by shutting down the system.

In addition, the transmission source of the 1PPS signal is not limited to the IED, and for example, another device having a GPS receiver may be used as the transmission source.

In the data collection device 100, the 1PPS signal receiving unit 101 receives a 1PPS signal.

That is, the 1PPS signal receiving unit 101 receives a pulse signal every second.

The 1PPS signal receiving unit 101 corresponds to an example of a pulse signal receiving unit.

The operation clock generator 102 generates an operation clock signal (hereinafter, simply referred to as an operation clock) of the data collection device 100 .

The clock deviation measurement unit 103 measures a clock deviation which is a frequency deviation of the operating clock of the data collection device 100 with respect to the period of the 1PPS signal.

The clock offset measurement value holding unit 104 holds the clock offset measurement value measured by the clock offset measurement unit 103 .

The sampling period counter 105 counts the time interval of the power sampling timing.

The sampling period counter 105 inputs a 1PPS signal from the 1PPS signal receiving part 101, and inputs an operating clock from the operating clock generating part 102. When the 1PPS signal is input, it starts counting corresponding to the clock period of the operating clock, and when it is finished, it reaches the predetermined counting completion. When counting up to the value, the counting of one cycle is completed, and the counting of the next cycle is started.

In addition, the sampling cycle counter 105 is also written as counter 105 .

The sampling signal generator 106 generates a sampling signal as a pulse indicating sampling timing based on the count value of the sampling cycle counter 105 .

More specifically, the sampling signal generator 106 outputs the sampling signal every time the sampling period counter 105 completes counting one cycle.

The sampling signal is a control signal for controlling the measurement timing of the electric quantity.

The sampling signal generation unit 106 corresponds to an example of a control signal output unit.

The electric quantity measuring unit 107 measures the electric quantity of the power system at the timing of the pulse (sampling signal) generated by the sampling signal generating unit 106 .

The data generating unit 108 converts the electric power measured by the electric power measuring unit 107 into digital data in a communication frame format that can be transmitted to a local area network (program bus).

The data transmission unit 109 transmits the digital data generated by the data generation unit 108 to the computing device 200 via a local area network (program bus).

The correction value calculation unit 110 calculates a correction value of the count completion value of the sampling period counter 105 based on the clock deviation value held by the clock deviation measurement value holding unit 104 .

The change timing calculation unit 111 calculates the time when the correction value calculated by the correction value calculation unit 110 is applied to the sampling cycle counter 105, and changes the count completion value to the correction value at the calculated time.

The correction value calculation unit 110 and the change timing calculation unit 111 change the count completion value of an arbitrary cycle based on the clock deviation measured by the clock deviation measurement unit 103 to adjust the output timing of the sampling signal from the sampling signal generation unit 106 .

More specifically, the correction value calculation unit 110 determines the cycle to be changed as the changed counted value and the correction value to be the changed counted value based on the number of cycles that occur in one second, the clock deviation, and the clock period of the operating clock. value.

Then, the change timing calculation unit 111 changes the count completion value of the cycle to be changed determined by the correction value calculation unit 110 to a correction value.

The correction value calculation unit 110 and the change timing calculation unit 111 correspond to an example of a count completion value change unit.

The counter initial value holding unit 112 restores the count completed value of the sampling cycle counter 105 to the initial value after the sampling signal is output.

The counter initial value holding unit 112 corresponds to an example of a count completion value restoring unit.

Next, an example of the operation of the data collection device 100 of this embodiment will be described.

In the data collection device 100, a 1PPS signal is input from the computing device 200 using a transmission means such as an optical cable or an electric signal cable.

The 1PPS signal is a pulse signal with a period of 1 second representing an absolute time.

The 1PPS signal is received by the 1PPS signal receiving unit 101 and distributed to the clock deviation measuring unit 103 and the sampling cycle counter 105 .

In the operation clock generation unit 102 , an operation clock of the data collection device 100 is generated and distributed to the clock deviation measurement unit 103 and the sampling period counter 105 .

In the clock deviation measuring section 103, the clock deviation is measured as a difference between the receiving timing of the 1PPS signal and 1 second counted by the operating clock of the data collection device 100, and the measurement result is determined by the clock deviation The measured value holding unit 104 holds the measured value.

An example of the operation of the clock deviation measurement unit 103 will be described with reference to FIG. 2 .

When a 1PPS signal is input to the clock deviation measuring unit 103, a 10-millisecond counter that counts in accordance with the clock period of the operating clock operates.

For example, when the operating clock is 80 MHz, counts are performed in units of 12.5 nanoseconds, so 800,000 counts is 10 milliseconds.

When the count of 10 milliseconds is the 99th time, if the counter counts 800,000, it becomes a period of 1 second in the measurement of the operation clock of the data collection device 100 .

The difference between the 1-second period counted by this operating clock and the reception timing of the 1PPS signal becomes the measured value of the clock skew.

In Figure 2, since the 1PPS signal is received at the time when the 10-millisecond counter counts 798400, the action clock counts 20 microseconds slower in 1 second ((800000-798400) × 12.5 nanoseconds), and this value is the clock Measured value of deviation.

Through this operation, the clock deviation measurement unit 103 measures the clock deviation as the deviation time per second of the operating clock with respect to the 1PPS signal, and stores the deviation measurement value in the clock deviation measurement value holding unit 104 .

The sampling period counter 105 receives and operates a 1PPS signal and an operation clock.

For example, when the AC frequency of the power system is 50 Hz and the number of sampling times per AC cycle is 80, the sampling period is 250 microseconds.

When the operating clock is 80 MHz (counting in units of 12.5 nanoseconds), the number of counts of the sampling cycle counter 105 is 20000 counts, and the cycle is 250 microseconds.

Simultaneously with the input of the 1PPS signal, the sampling period counter 105 starts counting, and sends a count value indicating the number of counts to the sampling signal generating unit 106 .

The sampling signal generator 106 outputs a sampling signal when the count value is 20000 (count completion value).

That is, when the count value reaches 20000 as the upper limit value, the counting of one cycle is completed, and the sampling cycle counter 105 starts counting of the next cycle, and each time the sampling cycle counter 105 completes the counting of one cycle, the sampling signal generating part 106 Output sampled signal.

In the case that there is no deviation in the action clock, since the sampling signal is output at an interval of 250 microseconds, the sampling signal is output 4000 times in 1 second from receiving the 1PPS signal to receiving the next 1PPS signal (that is, in 4000 cycles in 1 second).

However, due to deviations in the operation clock, the 4000-time sampling signal is not actually output in most cases.

For example, when counting by the operation clock for 1 second is delayed by 20 microseconds compared to 1PPS signal, as shown in Figure 3, the sampling signal is output only 3999 times per second, and cannot be output at a cycle of 250 microseconds sample signal.

Therefore, in order to correct for 20 microseconds, it is necessary to change the count completion value of the sampling cycle count.

Regarding the correction method, first, the correction value calculation unit 110 determines the correction value of the count completion value of the sampling cycle counter 105 based on the deviation measurement value held in the clock deviation measurement value holding unit 104 .

When the deviation measurement value is 20 microseconds, the sampling period of one time is shortened by 5 nanoseconds (20 microseconds/4000 times), whereby the sampling signal is output at a cycle of 250 microseconds.

However, since the operating clock usually used in digital circuits is several MHz to several tens of MHz (counting from tens of nanoseconds to tens of nanoseconds), it is impossible to perform counter adjustments of several nanoseconds, and it is necessary to collectively adjustments of a few nanoseconds.

When the correction value is several nanoseconds, the correction value calculation unit 110 determines the correction value of the counted value and the timing of collective correction so as to match the count unit of the operating clock.

An example of the operation of the correction value calculation unit 110 and the change timing calculation unit 111 will be described with reference to FIG. 4 .

When the operating clock is 80 MHz, the counting of the sampling cycle counter 105 is in units of 12.5 nanoseconds, and when the correction amount of one time of 5 nanoseconds matches the counting unit, five times (25 nanoseconds) are collectively performed. Correction.

That is, the correction value of the sampling cycle counter 105 is 25 nanoseconds, and the timing of the correction is every 5 sampling cycles (every 5 cycles).

The change timing calculation section 111 counts the output times of the sampling signal (the number of cycles of the counter 105), and when counting 4 times, shortens the upper limit value (20000 counts) of the sampling period counter 105 by 25 nanoseconds (shortening by 2 counts). ).

In this way, the correction value calculation unit 110 and the change timing calculation unit 111 divide the measured value of the clock deviation (20 microseconds) by the number of cycles (4000 times) generated in 1 second, and calculate the value based on the quotient (5 nanoseconds) and the operating clock. The common multiple (25 nanoseconds) of the clock period (12.5 nanoseconds) to determine the correction value.

The sampling signal generator 106 outputs the sampling signal at the changed count completion value (19998 counts) of the sampling cycle counter 105 .

And, when the sampling signal is received, the counter initial value holding unit 112 restores the count completion value of the sampling period counter 105 to the initial value (20000 counts), and outputs the sampling signal at a period of 20000 counts in the following 4 cycles.

When observation is performed in a period of 5 times, the sampling signal is output 5 times within exactly 1.25 milliseconds (250 microseconds×5).

Through the above operations, it is possible to output a sampling signal corrected for a deviation of 20 microseconds, and it is possible to output a sampling signal of an accurate number of times (4000 times) within one second.

The electrical quantity measurement unit 107 receives the sampling signal subjected to clock offset correction in the above procedure, and the electrical quantity measurement unit 107 measures the electrical quantity (current value, voltage value) of the power system.

The data generating unit 108 generates the measured electric quantity in a communication frame format that can be transmitted to the computing device 200 , and the data transmitting unit 109 transmits the generated communication frame to the computing device 200 .

Thus, according to this embodiment, since the correction value of the sampling period counter is calculated according to the clock deviation, and the counting completion value of the sampling period counter is dynamically changed according to the calculated correction value, even if a general-purpose oscillator with a frequency deviation of about ±50ppm is used, The circuit can also output sampling signals at precise timing, and can measure power at precise timing.

In addition, the example in which the sampling signal generator 106 detects that the count value of the sampling period counter 105 has reached the count completion value (20000 count or 19998 count) and outputs a sampling signal has been described above.

Alternatively, when the count value of the sampling cycle counter 105 reaches the count completion value (20000 counts or 19998 counts), the sampling cycle counter 105 outputs a pulse signal to the sampling signal generating part 106, and the sampling signal generating part 106 is inputted The sampling signal is output when the pulse signal from the sampling period counter 105 is received.

In addition, the example in which the operating clock is delayed relative to the 1PPS signal has been described above. However, the same applies to the case where the operating clock is ahead of the 1PPS signal. By changing the count completion value, it is possible to output the sampling signal at an accurate time.

In addition, when the operating clock is advanced with respect to the 1PPS signal, a count completion value whose value is larger than the initial value is set in an arbitrary cycle.

In addition, the example in which the sampling cycle counter 105 counts up has been described above, so the count completion value is the upper limit value of the sampling cycle counter 105, but when the sampling cycle counter 105 is counted down, the count completion value becomes the upper limit value of the sampling cycle counter 105. the lower limit value of .

As mentioned above, in this embodiment, the data collection device which collects the electric quantity of an electric power system and transmits it to a computing device, and which has the following means was demonstrated.

(a) units receiving 1PPS signals,

(b) a unit for measuring the frequency deviation between the 1PPS signal and the internal clock of the device,

(c) a unit that maintains a measurement of the frequency deviation between the 1PPS signal and the clock within the device,

(d) means for changing the counting range of the sampling period counter according to the frequency deviation between the 1PPS signal and the internal clock of the device,

(e) a unit for measuring the timing of changing the count range of the sampling period counter,

(f) a unit for generating a sampling signal based on the count value of the sampling period counter,

(g) a unit for maintaining the initial value of the count value of the sampling period counter and restoring the count value of the sampling period counter to the initial value,

(h) A unit for measuring the electrical quantity of the power system at the timing of the sampling signal,

(i) A unit that digitizes the amount of electricity to form a communication frame,

(j) A unit that transmits a communication frame to an arithmetic device.

Implementation mode 2.

In this embodiment, a configuration in which the correction value and the timing of the correction of the count completion value of the sampling cycle counter 105 are changed within a period of one second will be described.

FIG. 5 shows a configuration example of the data collection device 100 of this embodiment.

In FIG. 5 , the counter changing unit 113 changes the upper limit value of the sampling cycle counter 105 .

The counter changing unit 113 corresponds to an example of a count completion value changing unit together with the correction value calculating unit 110 and the change timing calculating unit 111 .

The counter change completion notification unit 114 notifies the change timing calculation unit 111 and the counter initial value holding unit 112 that the upper limit value of the sampling cycle counter 105 has been changed.

In addition, elements other than the counter change unit 113 and the counter change completion notification unit 114 are the same as those shown in FIG. 1 , and thus description thereof will be omitted.

Next, an example of the operation of the data collection device 100 of this embodiment will be described.

Similar to Embodiment 1, the clock offset measuring unit 103 measures the clock offset and stores the measured offset value in the clock offset measured value holding unit 104 .

The correction value calculation unit 110 calculates the correction value of the sampling cycle counter 105 from the clock offset value as in the first embodiment.

Here, in the present embodiment, the change timing calculation unit 111 determines the timing to change the counter based on the counter change completion notification from the counter change completion notification unit 114 .

Then, the change timing calculation unit 111 sets the correction value of the count completion value of the sampling period counter 105 to the counter change unit 113 , and the counter change unit 113 changes the count completion value of the sampling period counter 105 .

For example, the correction value calculation unit 110 and the change timing calculation unit 111 are constituted by software processing of a CPU (Central Processing Unit: central processing unit), and the counter change unit 113 is constituted by a register for setting a correction value.

The counter change completion notification from the counter change completion notification unit 114 is realized by an interrupt to software or a polling process from software.

Specifically, the counter changing unit 113 is constituted by an 8-bit register as shown in FIG. 6 .

For example, the most significant bit (bit 7) in FIG. 6 is a bit in which positive or negative is set, and bits 6-bit 0 are bits in which a correction value is set.

If the highest bit (bit 7) is set to positive, the correction value set for bit 6-bit 0 is added to the count completion value of the sampling period counter 105, if the highest bit (bit 7) is set If negative, the correction value set for bit 6-bit 0 is subtracted from the count completion value of the sampling cycle counter 105 .

In this way, the upper limit value of the sampling period counter 105 can be changed up to ±127 counts (all bits 6-bit 0 are "1" and are 127 in decimal notation).

When the operating clock is 80 MHz (counting in units of 12.5 nanoseconds), correction can be performed from 12.5 nanoseconds to approximately 1.5 microseconds.

In addition, the counter change completion notification unit 114 can measure the sampling signal output after the count completion value of the sampling period counter 105 is corrected based on the reception of the sampling signal generated by the sampling signal generation unit 106 and the correction timing of the sampling period counter 105 .

Therefore, the counter change completion notification unit 114 can notify the change timing calculation unit 111 and the counter initial value holding unit 112 of the completion of the counter change.

The counter change completion notification unit 114 is configured, for example, as a 1-bit register as shown in FIG. 7 .

And, when this register is "1", the setting value of the counter changing unit 113 is reflected in the sampling period counter 105, indicating that the calibration is completed, and when it is "0", it indicates that the calibration is not completed.

The change timing calculation unit 111 and the counter initial value holding unit 112 can judge whether the calibration is completed or not by referring to the register in FIG. 7 .

When the calibration is completed and it is time to perform the next calibration, the change timing calculation unit 111 sets the correction value to the counter change unit 113 .

When the correction is completed, the counter initial value holding unit 112 restores the count completion value of the sampling period counter 105 to the initial value (20000 counts).

The sampling signal is output at the cycle of the initial value of the count completion value until the next count completion value is changed.

Through the above operations, the correction value of the sampling cycle counter 105 can be set variable, and the result of the correction value calculated from the clock deviation can be adjusted even if there is a mantissa.

For example, when the correction value calculated from the clock offset is 23 microseconds, the amount of correction per time is 5.75 nanoseconds.

In the case of 5.75 ns, when making it match the count in 12.5 ns units, there is a mantissa (3 microseconds overall when correcting for 25 ns every 5).

In order to correct the mantissa (3 microseconds) as well, it is necessary to perform a correction of 25 nanoseconds every 33 times in addition to performing a correction of 25 nanoseconds every 5 times.

Also, in this example, the correction value every 5 times and the correction value every 33 times are both 25 nanoseconds, and the value is common, but the correction value every 5 times and 1 time every 33 times The correction value of can also be a different value.

With an arrangement in which the correction value and the timing of correction are variable as in the present embodiment, correction can be performed even when the correction value has a mantissa.

That is, in the present embodiment, the correction value calculation unit 110 determines a plurality of cycles as the change target of the change count completion value and the set of the changed count completion value, and the change timing calculation unit 111 and the counter change unit 113 set the number of cycles as the change target. The completed count value of the cycle is changed to the changed count completed value (correction value) determined for the cycle to be changed.

In this way, the output timing of the sampling signal can be controlled with high precision.

As mentioned above, in this embodiment, the data collection device which collects the electric quantity of an electric power system and transmits it to a computing device, and which has the following means was demonstrated.

(a) units receiving 1PPS signals,

(b) a unit for measuring the frequency deviation between the 1PPS signal and the internal clock of the device,

(c) a unit that maintains a measurement of the frequency deviation between the 1PPS signal and the clock within the device,

(d) means for setting the change value of the counting range of the sampling period counter according to the frequency deviation between the 1PPS signal and the internal clock of the device,

(e) A unit that changes the count range according to the setting of the change value of the count range of the sampling cycle counter,

(f) means for measuring the timing of changing the count range of the sampling period counter,

(g) a unit for generating a sampling signal from the count value of the sampling period counter,

(h) a unit for maintaining the initial value of the count value of the sampling period counter and restoring the count value of the sampling period counter to the initial value,

(i) Notify the unit that generates the sampling signal according to the value of the count range of the sampling period counter changed,

(j) A unit for measuring the electrical quantity of the power system at the timing of the sampling signal,

(k) Digitizing the electric quantity and constituting the unit of the communication frame,

(l) A unit that transmits a communication frame to an arithmetic device.

Finally, an example of the hardware configuration of the data collection device 100 shown in Embodiments 1 and 2 will be described with reference to FIG. 8 .

The data collection device 100 is a computer, and each element of the data collection device 100 can be realized by a program.

As a hardware configuration of the data collection device 100, a control device 901, an external storage device 902, a main storage device 903, a communication device 904, an input/output device 905, a clock generation circuit 906, and a counter 907 are connected to a bus.

The control device 901 is a CPU that executes programs.

The external storage device 902 is, for example, a ROM (Read Only Memory), a flash memory, or a hard disk device.

The main storage device 903 is RAM (Random Access Memory: Random Access Memory).

The clock deviation measured value holding unit 104 is realized by, for example, the main storage device 903 .

The communication device 904 corresponds to the physical layer of the 1PPS signal receiving unit 101 and the data transmitting unit 109 .

The input/output device 905 is, for example, a mouse, a keyboard, a display device, and the like.

The clock generation circuit 906 has a quartz oscillator, and generates a clock signal for the operation of the data collection device 100 .

The operation clock generation unit 102 is realized by the clock generation circuit 906 .

Also, the sampling period counter 105 is realized by the counter 907 .

The program is usually stored in the external storage device 902 , loaded into the main storage device 903 , and sequentially read and executed by the control device 901 .

The program is implemented as the "~ part" shown in Fig. 1 and Fig. 5 (except for the operating clock generation part 102, the clock deviation measurement value holding part 104, the counter changing part 113, and the counter change completion notification part 114, the same applies below) A program that describes the function.

In addition, an operating system (OS) is also stored in the external storage device 902, at least a part of the OS is loaded into the main storage device 903, and the control device 901 executes the function of "-part" shown in FIG. 1 while executing the OS. program.

In addition, in the description of Embodiments 1 and 2, it will be expressed as "measurement of ~", "count of ~", "change of ~", "determination of ~", "setting of ~", "designation of ~ ", "calculation of ~", "judgment of ~", "judgment of ~", "selection of ~", "generation of ~", "input of ~", "reception of ~", etc. The information, data, signal values and variable values are stored in the main storage device 903 as files.

In addition, the structure of FIG. 8 shows only an example of the hardware structure of the data collection apparatus 100, and the hardware structure of the data collection apparatus 100 is not limited to the structure described in FIG. 8, and may be other structures.

Label description

100: Data collection device; 101: 1PPS signal receiving unit; 102: Operating clock generating unit; 103: Clock deviation measuring unit; 104: Clock deviation measured value holding unit; 105: Sampling cycle counter; 106: Sampling signal generating unit; 107 108: Data generation unit; 109: Data transmission unit; 110: Correction value calculation unit; 111: Change timing calculation unit; 112: Counter initial value holding unit; 113: Counter change unit; 114: Counter change completed Notify the Ministry.

Claims (8)

1. a signal processing apparatus, is characterized in that, described signal processing apparatus has:

Pulsed signal portion, its time per unit return pulse signal;

Action clock generating unit, the Action clock signal that its generated clock cycle is small compared with the described unit interval;

Counter, it inputs described pulse signal from described pulsed signal portion, described Action clock signal is inputted from described Action clock generating unit, start when the input of described pulse signal to carry out the counting corresponding to the clock period of described Action clock signal, complete the counting of 1 circulation during counting finishing set counting and completing value, and start counting of next circulation;

Control signal efferent, when described counter completes the counting of 1 circulation, this control signal efferent exports control signal;

Clock jitter determination part, it inputs described pulse signal from described pulsed signal portion, input described Action clock signal from described Action clock generating unit, measure relative to the clock jitter of the frequency departure of described pulse signal as described Action clock signal; And

Counted value changing unit, it is according to the clock jitter determined by described clock jitter determination part, and the counting changing Arbitrary cyclic completes value,

When the counting being completed value changing unit by described counting and change Arbitrary cyclic completes value, complete the counting of this circulation during the counting of described counter till finishing the counting after changing and completing value, and start counting of next circulation.

2. signal processing apparatus according to claim 1, is characterized in that,

Described signal processing apparatus also has counting and completes value recovery portion, and described counting completes value recovery portion and the counting being completed value changing unit by described counting and change next circulation of the circulation having counted value is completed value reverts to described set counting and complete value.

3. signal processing apparatus according to claim 1 and 2, wherein,

During the value changing unit that completes described counting circulates according to n, the ratio of 1 time changes counting and completes value, and wherein, n is the integer of more than 2.

4. the signal processing apparatus according to any one in claims 1 to 3, is characterized in that,

Described counting completes the clock period of value changing unit according to the number of times of the circulation produced in the described unit interval, the clock jitter determined by described clock jitter determination part and described Action clock signal, the counting determining to change after the circulation and change count value completes value, and the counting of the circulation determined is completed value and change to the counting determined and complete value.

5. signal processing apparatus according to claim 4, wherein,

Described counting completes clock jitter that value changing unit makes to be determined by the described clock jitter determination part number of times divided by the circulation produced in the described unit interval, according to the common multiple of the clock period of business and described Action clock signal, the counting determining to change after the circulation and change count value completes value.

6. the signal processing apparatus according to any one in claim 1 to 5, is characterized in that,

Described counting completes value changing unit and determines multiple as changing the circulation that count the change object of value and the counting after changing completes the group of value, changes to and completes value for this as the counting after the change that the circulation of change object determines using completing value as the counting of the circulation of changing object.

7. the signal processing apparatus according to any one in claim 1 to 6, is characterized in that,

When described counter completes the counting of 1 circulation, described control signal efferent exports sampled signal as described control signal,

Described signal processing apparatus also has coulometry portion, the sampled signal that the input of this coulometry portion exports from described control signal efferent, measures electricity on the opportunity that have input sampled signal.

8. signal processing apparatus according to claim 7, is characterized in that,

Described pulsed signal portion receives 1PPS (1 Pulse Per Second) signal from external device (ED),

Described signal processing apparatus also has data sending part, and this data sending part will notify that the data of the electricity determined by described coulometry portion send to described arithmetic unit.