CN105007074B - A kind of delay matching circuit for charge pump phase frequency detector - Google Patents

Abstract

The invention belongs to electronic circuit technology field, more particularly to a kind of delay matching circuit for charge pump phase frequency detector.The main technical schemes of the present invention are that the delay being output to from d type flip flop on two paths of charge pump switches pipe is accomplished to match well, while notice that the phase inverter time delay chain in upper and lower two transmission channel is full symmetric.Also it is delayed simultaneously by phase inverter and capacitor increase, the width of phase frequency detector reset pulse is widened, to solve the problems, such as charge pump phase frequency detector deadbanding.Invention has the beneficial effect that, can significantly eliminate the influence that general phase frequency detector is output to delay mismatches in the transmission path of charge pump input so that phase frequency detector precision is higher, and phaselocked loop frequency locking is more accurate.

Description

A Delayed Matching Circuit Used in Frequency and Phase Detector of Charge Pump

technical field

The invention belongs to the technical field of electronic circuits, and in particular relates to a time-delay matching circuit used for a frequency and phase detector of a charge pump.

Background technique

The charge pump phase-locked loop CPPLL has become the mainstream of the current phase-locked loop products due to its large frequency capture capability and zero phase difference in static state. As a key part of the phase-locked loop, it is suitable for identification Frequency phase detector has also become a research hotspot. The frequency and phase detector PFD, its main function is to detect the frequency and phase deviation between the input reference signal and the feedback signal, and use the phase or frequency deviation to generate a control signal, so that the output signal of the voltage-controlled oscillator VCO will reduce the phase or frequency deviation. change in direction.

A general phase-locked loop circuit with a charge pump is shown in Figure 1. Since the charging switch of the charge pump is generally a PMOS tube, its opening is controlled by a logic low level, and the discharge switch is generally an NMOS tube, which is controlled by a logic high level. its on. In this way, there must be an additional inverter on the transmission path from the output of the frequency detector to the input of the charge pump, so that the two signals from the output of the frequency detector to the switch tube of the charge pump exist in time. The mismatch causes ripples in the control voltage of the voltage-controlled oscillator, thereby increasing the phase noise. Therefore, the current circuit has the problem of delay in the two transmission paths.

Contents of the invention

What the present invention aims to solve is to propose a delay matching circuit for a frequency and phase detector of a charge pump, aiming at the problem of delay mismatch in the above-mentioned traditional charge-pump type phase-locked loop.

To achieve the above object, the present invention adopts the following technical solutions:

A delay matching circuit for a charge pump frequency and phase detector, comprising a first two-input NOR gate, a second two-input NOR gate, a third two-input NOR gate, a fourth two-input NOR gate, Fifth two-input NOR gate, sixth two-input NOR gate, seventh two-input NOR gate, first three-input NOR gate, second three-input NOR gate, four-input NOR gate, first inversion Inverter INV1, second inverter INV2, third inverter INV3, fourth inverter INV4, fifth inverter INV5, sixth inverter INV6, seventh inverter INV7, eighth inverter INV8, ninth inverter INV9, tenth inverter INV10, eleventh inverter INV11, twelfth inverter INV12, thirteenth inverter INV13, fourteenth inverter INV14, tenth inverter Fifth inverter INV15, sixteenth inverter INV16, seventeenth inverter INV17, eighteenth inverter INV18, nineteenth inverter INV19, twentieth inverter INV20, twenty-first inverter Inverter INV21 and capacitor C;

The first input of the first two-input NOR gate is connected to an external clock signal, its second input terminal is connected to the output terminal of the first three-input NOR gate, and its output terminal is connected to the second input terminal of the first three-input NOR gate and The first input terminal of the second two-input NOR gate; the output terminal of the first three-input NOR gate is connected to the input terminal of the first inverter INV1 and the input terminal of the fourth inverter INV4;

The output terminal of the first inverter INV1 is connected to the input terminal of the second inverter INV2; the output terminal of the second inverter INV2 is connected to the input terminal of the third inverter INV3 and the input terminal of the sixth inverter INV6;

The output end of the third inverter INV3 and the output end of the fourth inverter INV4 are connected to the input end of the fifth inverter INV5 and the input end of the eighth inverter INV8; the output of the fifth inverter INV5 The terminal is connected to the input terminal of the sixth inverter INV6; the output terminal of the sixth inverter INV6 is connected to the input terminal of the seventh inverter INV7; the output terminal of the seventh inverter INV7 is an invalid signal output terminal;

The output terminal of the eighth inverter INV8 is connected to the input terminal of the ninth inverter INV9; the output terminal of the ninth inverter INV9 is connected to the first input terminal of the four-input NOR gate; the output terminal of the ninth inverter INV9 The output terminal of the charge control signal for the charge pump;

The second input terminal of the four-input NOR gate is connected to the output terminal of the second two-input NOR gate, its third input terminal is connected to the output terminal of the fifth two-input NOR gate, and its fourth input terminal is connected to the fifteenth inverting phase The output terminal of the device INV15, its output terminal is connected to the first input terminal of the seventh two-input NOR gate;

The second input terminal of the seventh two-input NOR gate is connected to the enabling signal, and its output terminal is connected to the input terminal of the twenty-first inverter INV21; the output terminal of the twenty-first inverter INV21 is connected to the twentieth inversion The input end of the inverter INV20; the connection point between the output end of the twenty-first inverter INV21 and the input end of the twentieth inverter INV21 is grounded after passing through the capacitor C;

The output terminal of the twentieth inverter INV20 is connected to the input terminal of the nineteenth inverter INV19; the output terminal of the nineteenth inverter INV19 is connected to the second input terminal of the NOR gate of the third two-input terminal, the first three Input the first input terminal of the NOR gate, the first input terminal of the fourth two-input NOR gate and the third input terminal of the second three-input NOR gate;

The third input terminal of the first three-input NOR gate is connected to the output terminal of the second two-input NOR gate; the first input terminal of the fifth two-input NOR gate is connected to the output terminal of the first two-input NOR gate, and its first two-input NOR gate is connected to the output terminal of the first two-input NOR gate. The five input terminals are connected to the output terminal of the third two-input NOR gate; the first input terminal of the third two-input NOR gate is connected to the output terminal of the second two-input NOR gate;

The second input end of the fourth two-input NOR gate is connected to the output end of the fifth two-input NOR gate, and its output terminal is connected to the first input end of the second two-input NOR gate; Two input ends are connected to the output end of the sixth two-input NOR gate, and its output end is connected to the first input end of the second three-input NOR gate;

The second input terminal of the second three-input NOR gate is connected to the output terminal of the sixth two-input NOR gate, and its output terminal is connected to the first input terminal of the sixth two-input NOR gate and the input terminal of the tenth inverter INV10 and the input terminal of the eleventh inverter INV11; the second input terminal of the sixth two-input NOR gate is connected to an external feedback signal;

The output terminal of the eleventh inverter INV11 is connected to the input terminal of the twelfth inverter INV12; the output terminal of the twelfth inverter INV12 is connected to the input terminal of the thirteenth inverter INV13 and the seventeenth inverter Input terminal of INV17;

The output end of the thirteenth inverter INV13 and the output end of the tenth inverter INV10 are connected to the input end of the fourteenth inverter INV14 and the input end of the sixteenth inverter INV16; The output terminal of the inverter INV14 is connected to the input terminal of the fifteenth inverter INV15;

The output terminal of the sixteenth inverter INV16 is connected to the input terminal of the seventeenth inverter INV17; the output terminal of the seventeenth inverter INV17 is connected to the input terminal of the eighteenth inverter INV18; the eighteenth inverter The output terminal of INV18 is the output terminal of the discharge control signal of the charge pump.

The beneficial effect of the invention is that it can greatly eliminate the influence of delay mismatch on the transmission path from the output of the general frequency and phase detector to the input of the charge pump, so that the frequency and phase detector has higher precision and the phase-locked loop frequency locking is more accurate.

Description of drawings

Fig. 1 is the circuit diagram of the frequency discrimination phase detector of traditional belt charge pump;

Fig. 2 is the schematic diagram of the circuit structure of the delay matching circuit for the charge pump frequency and phase detector of the present invention;

FIG. 3 is a simulation verification diagram of the delay matching circuit of the present invention.

detailed description

The invention proposes a time-delay matching circuit suitable for the frequency and phase detector of the charge pump, which can reduce the delay mismatch on the transmission path from the output of the frequency and phase detector to the input of the charge pump, and improve the frequency locking precision of the phase-locked loop.

As shown in Figure 2 is the specific circuit diagram of the present invention, the first input terminal of two-input NOR gate NOR2_1 is connected to input A, the second input terminal is connected to the output of three-input NOR gate NOR3_1 and the input of inverters INV1 and INV4 Terminal C, the output terminal is connected to the second input terminal of the two-input NOR gate NOR3_1 and the first input terminal of the two-input NOR gate NOR2_2, and the first input terminal of the three-input NOR gate NOR3_1 is connected to the first input terminal of the three-input NOR gate NOR3_2 Three input terminals and the second input terminal of the two-input NOR gate NOR2_3, the first input terminal of the two-input NOR gate NOR2_4 and the output terminal of the inverter INV19, the third input terminal of the three-input NOR gate NOR3_1 is connected to the two inputs The output terminal of the NOR gate NOR2_2, the second input terminal of the two-input NOR gate NOR2_2 is connected to the output terminal of the two-input NOR gate NOR2_3, the first input terminal of the two-input NOR gate NOR2_3 is connected to the output of the two-input NOR gate NOR2_2 terminal and the second input terminal of the four-input NOR gate NOR4_1, the output terminal of the inverter INV1 is connected to the input terminal of the inverter INV2, and the output terminal of the inverter INV2 is connected to the input terminal of the inverter INV3 and the inverter INV6 The input terminal of the inverter INV3 and the output terminal of the inverter INV4 are connected to the input terminal of the inverter INV5 and the input terminal of the inverter INV8, and the output terminal of the inverter INV5 is connected to the input of the inverter INV6 terminal, the output terminal of inverter INV6 is connected to the input terminal of inverter INV7, the output terminal of inverter INV7 is connected to E, the output terminal of inverter INV8 is connected to the input terminal of inverter INV9, and the output terminal of inverter INV9 terminal and the first input terminal of the four-input NOR gate NOR4_1 is connected to the output terminal UP, the second input terminal of the two-input NOR gate NOR2_6 is connected to the input B, and the first input terminal is connected to the output terminal of the three-input NOR gate NOR gate NOR3_2 And the input terminal D of inverter INV10 and INV11, output terminal or the second input terminal of two-input NOR gate NOR3_2 and the second input terminal of two-input NOR gate NOR2_5, the third input terminal of three-input NOR gate NOR3_2 Connect the first input terminal of the three-input NOR gate NOR3_1 and the second input terminal of the two-input NOR gate NOR2_3, the first input terminal of the two-input NOR gate NOR2_4 and the output terminal of the inverter INV19, the three-input NOR gate The second input terminal of NOR3_2 is connected to the output terminal of the two-input NOR gate NOR2_5, the first input terminal of the two-input NOR gate NOR2_5 is connected to the output terminal of the two-input NOR gate NOR2_4, and the second input terminal of the two-input NOR gate NOR2_4 Connect the output terminal of the two-input NOR gate NOR2_5 and the third input terminal of the four-input NOR gate NOR4_1, the input terminal of the inverter INV11 is D, the output terminal of the inverter INV11 is connected to the input terminal of the inverter INV12, and the inverter The output terminal of the phaser INV12 is connected to the input terminals of the inverter INV13 and the inverter INV17, and the output terminals of the inverter INV10 and the inverter INV13 are connected to the inverter I NV14 and the input end of the inverter INV16, the output end of the inverter INV14 is connected to the input end of the inverter INV15, the output end of the inverter INV15 is connected to the fourth input end of the four-input NOR gate NOR4_1, and the inverter INV16 The output terminal of the inverter INV17 is connected to the input terminal of the inverter INV17, the output terminal of the inverter INV17 is connected to the input terminal of the inverter INV18, the output terminal of the inverter INV18 is output DOWN, and the output terminal of the four-input NOR gate NOR4_1 is connected to two inputs The second input terminal of the NOR gate NOR2_7, the first input terminal of the two-input NOR gate NOR2_7 is connected to the input signal EN, the output terminal of the two-input NOR gate NOR2_7 is connected to the input terminal of the inverter INV21, and the output of the inverter INV21 The input terminal of the terminal inverter INV20 is connected to the upper plate of the capacitor C, the lower plate of the capacitor C is grounded, and the output terminal of the inverter INV20 is connected to the input terminal of the inverter INV19.

Working principle of the present invention is:

As shown in Figure 2, A is the input reference clock, B is the signal fed back from the phase-locked loop output, EN is the enable signal of the frequency and phase detector, when EN is low, the circuit works normally, and UP is the charge pump The charge control signal of the charge pump, DOWN is the discharge control signal of the charge pump, and E is the invalid signal of the output. NOR2_1 and NOR3_1, NOR2_2 and NOR2_3 constitute RS flip-flops respectively, and these two RS flip-flops form a D flip-flop triggered by a rising edge with a reset terminal, A and B generate C and D signals after passing through the D flip-flop, and from C and D Signal to output signal UP, DOWN is the core structure of the present invention. It can be seen from Figure 2 that there are two paths ① and ② from the C signal to the output signal UP, the path ① passes through the delay of the five-stage inverter, and the path ② passes through the delay of the three-stage inverter; from the D signal to the output signal DOWN There are three paths ③, ④ and ⑤, the path ③ is delayed by the four-stage inverter, the path ④ is delayed by the six-stage inverter, and the path ⑤ is delayed by the four-stage inverter, so in general, from the D signal to the output The length of the inverter delay chain of the signal DOWN is greater than the length of the inverter delay chain from the C signal to the output signal UP, but at the same time there are two paths from the C signal to the output signal UP, and there are three paths from the D signal to the output signal DOWN , so it can be concluded that the driving capability on the path from the D signal to the output signal DOWN is greater than the driving capability on the path from the C signal to the output signal UP. Combining the analysis of the length of the delay chain and the driving ability, it can be obtained that although the length of the delay chain is large on the path from the D signal to the output signal DOWN, the driving ability is strong, while on the path from the C signal to the output signal UP, although the length of the delay chain is Small, but its driving ability is weak. By adjusting the size of the upper and lower side inverters, a good compromise between delay time and driving ability can be achieved, so that the two paths from the output of the D flip-flop to the switch tube of the charge pump At the same time, notice that the delay chains of the inverters on the upper and lower transmission channels are completely symmetrical. The purpose of the inverters INV5, INV6, and INV7 before the invalid output signal E is to match the delay chains before the DOWN signal. The inverters INV16, INV17, and INV18 are matched to reduce the mismatch to a greater extent. In addition, the function of the inverters INV19, INV20, INV21 and the capacitor C is to increase the delay time and widen the reset pulse width of the frequency and phase detector to solve the problem of the dead zone of the frequency and phase detector of the charge pump. Fig. 3 shows the simulation verification diagram of the delay matching circuit of the present invention, it can be seen that the delay difference on the two transmission paths before optimization is 360ps, and the two transmission paths after the delay matching circuit optimization of the present invention The delay difference on the path is 83 ps, so it shows that the delay matching circuit proposed by the present invention matches the time delay difference on the two paths very well.

In summary, the present invention proposes a delay matching circuit applicable to the frequency and phase detector of the charge pump, which can greatly reduce the mismatch of the delay on the transmission path from the output of the frequency and phase detector to the charge pump, and improve the phase-locking performance. Ring frequency lock accuracy.

Claims (1)

1. a kind of delay matching circuit for charge pump phase frequency detector, including first liang of input nor gate, second liang of input Nor gate, the 3rd liang of input nor gate, the 4th liang of input nor gate, the 5th liang of input nor gate, the 6th liang of input nor gate, the Seven liang input nor gates, the one or three input nor gate, the two or three input nor gate, four input nor gates, the first phase inverter INV1, Second phase inverter INV2, the 3rd phase inverter INV3, the 4th phase inverter INV4, the 5th phase inverter INV5, hex inverter INV6, Seven phase inverter INV7, the 8th phase inverter INV8, the 9th phase inverter INV9, the tenth phase inverter INV10, the 11st phase inverter INV11, 12nd phase inverter INV12, the 13rd phase inverter INV13, the 14th phase inverter INV14, the 15th phase inverter INV15, the tenth It is hex inverter INV16, the 17th phase inverter INV17, eighteen incompatibilities phase device INV18, the 19th phase inverter INV19, the 20th anti- Phase device INV20, the 21st phase inverter INV21 and electric capacity C；

First input of first liang of input nor gate connects external timing signal, its input nor gate of the second input termination the one or three Output end, it exports the first input end of the second input of the input nor gate of termination the one or three and second liang of input nor gate； The first phase inverter INV1 of the output termination input and the 4th phase inverter INV4 input of one or three input nor gate；

First phase inverter INV1 the second phase inverter INV2 of output termination input；Second phase inverter INV2 output termination the Three phase inverter INV3 input and hex inverter INV6 input；

3rd phase inverter INV3 output end connects with the 4th phase inverter INV4 output end is followed by the defeated of the 5th phase inverter INV5 Enter end and the 8th phase inverter INV8 input；5th phase inverter INV5 output termination hex inverter INV6 input； Hex inverter INV6 the 7th phase inverter INV7 of output termination input；7th phase inverter INV7 output end is invalid letter Number output end；

8th phase inverter INV8 the 9th phase inverter INV9 of output termination input；9th phase inverter INV9 output termination four Input the first input end of nor gate；9th phase inverter INV9 output end is charge pump charging control signal output end；

The output end of second second liang of input nor gate of input termination of four input nor gates, its 5th liang of the 3rd input termination are defeated Enter the output end of nor gate, the 15th phase inverter INV15 of its 4th input termination output end, it exports the 7th liang of input of termination The first input end of nor gate；

Second input termination enable signal of the 7th liang of input nor gate, it exports the defeated of the 21st phase inverter INV21 of termination Enter end；21st phase inverter INV21 the 20th phase inverter INV20 of output termination input；21st phase inverter The tie point of INV21 output ends and the 20th phase inverter INV21 inputs after electric capacity C by being grounded；

20th phase inverter INV20 the 19th phase inverter INV19 of output termination input；19th phase inverter INV19's Output termination the 3rd liang of input nor gate the second input, the one or three input nor gate first input end, the 4th liang it is defeated Enter the first input end of nor gate and the 3rd input of the two or three input nor gate；

The output end of 3rd second liang of input nor gate of input termination of the one or three input nor gate；Second liang inputs nor gate First input end connects the output end of first liang of input nor gate, the output end of its second input the 3rd liang of input nor gate of termination； The first input end of 3rd liang of input nor gate connects the output end of second liang of input nor gate；

The output end of second the 5th liang of input nor gate of input termination of the 4th liang of input nor gate, it is defeated that it exports the 5th liang of termination Enter the first input end of nor gate；The output end of second the 6th liang of input nor gate of input termination of the 5th liang of input nor gate, It exports the first input end of the input nor gate of termination the two or three；

The output end of second the 6th liang of input nor gate of input termination of the two or three input nor gate, it is defeated that it exports the 6th liang of termination Enter the first input end, the tenth phase inverter INV10 input and the 11st phase inverter INV11 input of nor gate；6th Second input termination external feedback signal of two input nor gates；

11st phase inverter INV11 the 12nd phase inverter INV12 of output termination input；12nd phase inverter INV12's The 13rd phase inverter INV13 of output termination input and the 17th phase inverter INV17 input；

13rd phase inverter INV13 output end connects with the tenth phase inverter INV10 output end is followed by the 14th phase inverter The input of INV14 input and the tenth hex inverter INV16；14th phase inverter INV14 output termination the 15th is anti- Phase device INV15 input；

Tenth hex inverter INV16 the 17th phase inverter INV17 of output termination input；17th phase inverter INV17's Output termination eighteen incompatibilities phase device INV18 input；Eighteen incompatibilities phase device INV18 output end is charge pump control letter Number output end.