CN105006479B - Display substrate and display device using same - Google Patents

Abstract

The present invention provides a display substrate and a display device using the same. The display substrate includes a substrate and a display structure, and the display structure is disposed on the substrate. The display structure includes a plurality of display units, and the display units are arranged in an array and each display unit has a core area and a peripheral area, wherein the core area includes at least one first sub-pixel and at least one second sub-pixel, and the peripheral area includes at least one third sub-pixel, and the peripheral area is located outside the core area.

Description

Display substrate and display device using same

technical field

The present invention relates to a display substrate and a display device using the same, and in particular to an organic light emitting diode display substrate with good display quality and an organic light emitting diode display device using the same.

Background technique

An organic light emitting diode display (Organic Light Emission Diode, OLED) has the advantages of being thin, actively emitting light without a backlight source, and having no viewing angle limitation. As consumers expect high display quality of electronic products, the image resolution of organic light-emitting diode displays must develop toward high-resolution pixels (High PPI; High Pixel perInch).

The emission layer (Emission Layer) in the OLED panel is mostly made by evaporation (Evaporating), in which, a fine metal mask (Fine Metal Mask) is used in the evaporation process of the emission layer of the OLED A light emitting film is coated in the pixel. Due to the limitations of the evaporation process, if there is no proper tolerance consideration in the design, different colors of light-emitting layer films may be superimposed on each other, resulting in uneven, abnormal, or color shift of the panel display. Therefore, the tolerance of the evaporation process is one of the important obstacles for improving the resolution of the OLED panel.

Contents of the invention

The invention relates to a display substrate and a display device using the same. In the display substrate of the embodiment, the peripheral area formed by the third sub-pixel in the display unit surrounds the core area formed by the first sub-pixel and the second pixel, and the side of the third sub-pixel is adjacent to the first sub-pixel or the second Both sides of the two sub-pixels can compensate display defects caused by unequal vertical or horizontal portions between pixels, thereby improving the quality of displayed images.

According to an embodiment of the present invention, a display substrate is provided. The display substrate includes a base and a display structure, and the display structure is arranged on the base. The display structure includes a plurality of display units arranged in an array and each display unit has a core area and a peripheral area, wherein the core area includes at least one first sub-pixel and at least one second sub-pixel, and the peripheral area includes At least one third sub-pixel, and the peripheral area is located outside the core area.

According to an embodiment of the present invention, a display device is proposed. The display device includes a display substrate and a cover substrate, and the cover substrate and the display substrate are paired. The display substrate includes a base and a display structure, and the display structure is arranged on the base. The display structure includes a plurality of display units arranged in an array and each display unit has a core area and a peripheral area, wherein the core area includes at least one first sub-pixel and at least one second sub-pixel, and the peripheral area includes At least one third sub-pixel, and the peripheral area is located outside the core area.

Description of drawings

In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and understandable, the specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

FIG. 1A is a schematic top view of a display unit in a display device according to an embodiment of the invention.

FIG. 1B shows a partially enlarged view of FIG. 1A .

FIG. 1C is a schematic cross-sectional view of FIG. 1A .

1D-1I are schematic top views of display units in a display device according to other embodiments of the present invention.

FIG. 2 is a schematic top view of a display unit matrix of a display structure according to another embodiment of the present invention.

FIG. 3 is a schematic top view of a display unit matrix of a display structure according to yet another embodiment of the present invention.

4A-4C are flow charts illustrating the evaporation process of the luminescent material according to an embodiment.

5-8 are schematic diagrams of a metal mask used for manufacturing a display unit according to an embodiment of the present invention.

Explanation of component numbers in the figure:

1: display device

10: Display substrate

20: Cover the substrate

100: base

110: Substrate

120: switch unit

130: passivation layer

135: Penetrating hole

200, 300: display structure

210: Luminescent layer

211: the first sub-pixel

211E, 215E, 215E1, 215E2: tolerance area

211L, 213L, 215L, 215L1, 215L2: Light emitting area

211s1～211s4, 213s1～213s2: side

213, 523p: Second sub-pixel

215, 215-1, 215-2, 215-3, 525p: the third sub-pixel

217: The fourth sub-pixel

220: first electrode layer

230: second electrode layer

240: Pixel definition layer

245: opening

400: protective layer

521: The first luminescent material

523: Second luminescent material

525: The third luminescent material

S, S1, S2, S3, S4, S5, S6: display unit

C: core area

P, P1, P2, P3, P4, P5, P6: peripheral area

L1～L4: opening length

U: Pixels

M1～M3, M5～M8: metal mask

M10～M30, M50～M80: opening

W1～W4: opening width

Detailed ways

According to an embodiment of the present invention, in the display substrate, the peripheral area formed by the third sub-pixel in the display unit surrounds the core area formed by the first sub-pixel and the second pixel, and the side of the third sub-pixel is adjacent to the first The two sides of the sub-pixel or the second sub-pixel can compensate display defects caused by unequal vertical or horizontal portions between pixels, thereby improving the quality of displayed images. Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The same reference numerals in the drawings are used to designate the same or similar parts. It should be noted that the drawings are simplified to clearly illustrate the content of the embodiments, and the detailed structures proposed in the embodiments are for illustration purposes only, and are not intended to limit the scope of protection of the present invention. Those skilled in the art may modify or change these structures according to the needs of actual implementation.

FIG. 1A shows a schematic top view of a display unit S in a display substrate of a display device 1 according to an embodiment of the present invention, FIG. 1B shows an enlarged display view of a part of the area in FIG. 1A , and FIG. 1C shows a display unit S in FIG. 1A A cross-sectional schematic diagram of an individual sub-pixel (Sub Pixel). As shown in FIG. 1C , the display device 1 includes a display substrate 10 and a cover substrate 20 , the cover substrate 20 and the display substrate 10 are paired to form a display module, and the display module is a part of the display device. The display device 1 may also have a driving module (not shown) including functions of power supply, signal generation, signal transmission, etc., an optical auxiliary module with optical modulation function, or a touch module with touch detection function.

As shown in FIGS. 1A˜1C , the display substrate 10 includes a base plate 100 and a display structure 200 , and the display structure 200 is disposed on the base 100 . Wherein, the base 100 includes a substrate, and a layout of circuit elements such as thin film transistors, capacitors, electrodes or transmission lines, and the display structure 200 is driven by the base 100 and provides signals. The display structure 200 includes a plurality of display units (display unit) S, the display units S are arranged in an array, and each display unit S includes a core region (CoreRegion) C and a peripheral region (Peripheral Region) P, the peripheral region P is located in the core The outside of the region C, for example, the peripheral region P may surround the core region C. The core area C includes a pair of first sub-pixels 211 and a pair of second sub-pixels 213, the first sub-pixels 211 and the second sub-pixels 213 are arranged in a staggered manner, and the first sub-pixels 211 are arranged diagonally to each other, and the second sub-pixels The pixels 213 are arranged diagonally to each other, and the sub-pixels in the overall core area C are arranged in a checkerboard shape (Damier Shape). The peripheral area P includes at least one third sub-pixel 215. In this embodiment, the number of third sub-pixels 215 located in the peripheral area P is 8. In other embodiments, the number of third sub-pixels 215 in the peripheral area P is also It can be 1, 2 or 4, and the number of the third sub-pixels 215 is the same as the number of regions that can be individually driven. One side of the third sub-pixel 215 is adjacent to the side of the first sub-pixel 211 or the second sub-pixel 213. In this embodiment, one side of the third sub-pixel 215 is only adjacent to the first sub-pixel 211 respectively. Or a side of one of the second sub-pixels 213 . The shape of each sub-pixel can be rectangle, circle or other polygons.

As shown in FIG. 1B, a first sub-pixel 211 and two third sub-pixels 215 form a pixel (Pixel) U, and a second sub-pixel 213 and two third sub-pixels 215 can also form a pixel U. , four pixels U will form a display unit S, and the resolution of the display device 1 is equal to the number of these pixels U. In the embodiment, the L-shaped appearance formed by the two third sub-pixels 215 has a vertical part and a horizontal part, and the horizontal part is inserted into the space where the first sub-pixel 211 and the second sub-pixel 213 are distributed, so that the horizontal and vertical distances can be compensated difference, and improve the imaging quality.

Please refer to FIG. 1C , in an embodiment, the substrate 100 may include a substrate 110 and a switch unit 120 , or other transmission circuit traces, and a collection of active/passive components. The substrate 110 can be made of glass, plastic, metal or the like. The switch unit 120 can be a thin film transistor, which is used to control the switching of each pixel to display a picture, and its structure can be top gate (Top Gate), bottom gate (Bottom Gate), double gate (Dual Gate) or Coplanar, the active layer can be amorphous silicon (Amorphous Silicon), low temperature polysilicon (Low Temperature Poly Silicon) or oxide semiconductor (Metal Oxide Semiconductor). The surface of the substrate 100 is covered with a passivation layer (Passivation Layer), and there are a plurality of through holes (Via) 135 corresponding to one of the source or the drain of the exposed switch unit 120 for signal transmission.

In an embodiment, the light emitting layers 210 of the first sub-pixel 211 , the second sub-pixel 213 and the third sub-pixel 215 have different primary colors. For example, the first sub-pixel 211 is red R, the second sub-pixel 213 is blue B, and the third sub-pixel 215 is green G, for example. However, the color of the light-emitting layer 210 of the first sub-pixel 211 , the second sub-pixel 213 and the third sub-pixel 215 can also be properly selected according to actual needs, and is not limited to the above arrangement. In the embodiment, the light-emitting layer 210 of the first sub-pixel 211 , the second sub-pixel 213 and the third sub-pixel 215 is made of organic light-emitting material, for example.

As shown in FIG. 1C , the display structure 200 ( 300 ) includes a first electrode layer 220 , a pixel definition layer (Pixel Define Layer) 240 , a light emitting layer (Emission Layer) 210 , and a second electrode layer 230 . The light emitting layer 210 is sandwiched between the first electrode layer 220 and the second electrode layer 230 to form a light emitting diode sandwich structure. The first electrode layer 220 is formed on the substrate 100, and is electrically connected to the switch unit through the through hole 135, and can be used as an anode (anode). Layer-formed structure, such as ITO/Ag/ITO. The pixel definition layer 240 is disposed on the first electrode layer 220 after it is formed, and has an opening 245 corresponding to and exposing part of the first electrode layer 220 . The area of the opening 245 is smaller than that of the first electrode layer 220 . The light-emitting layer 210 is, for example, an organic light-emitting material, and its coverage area is smaller than or equal to the area of each sub-pixel and larger than the area of the opening 245 or the first electrode layer 220 . The actual light-emitting area of the light-emitting layer 210 is equal to the area of the opening 245 . The second electrode layer 230 is located on the light-emitting layer 210 , and its material can be metal, alloy or metal oxide conductor, and a single-layer or multi-layer structure, such as Mg:Ag alloy, can be used as a cathode. The display substrate 10 may further include a capping layer 400 covering the display structure 200 .

As shown in FIG. 1B, each sub-pixel 211, 213, 215 has an actual light-emitting area, and the area of the light-emitting area is defined as the area of the opening 245 of the pixel definition layer 240 of each sub-pixel, and the area of each opening 245 is the area of each light-emitting area. There are corresponding light emitting areas 211L, 213L, 215L. Taking the pixel U composed of the first sub-pixel 211 and the third sub-pixel 215 as an example, the light-emitting layer 210 is evaporated. Due to the limitation of the evaporation process, the actual area of the light-emitting layer 210 will be smaller than the area occupied by the sub-pixels. That is to say, because the alignment accuracy of the evaporation machine in the evaporation process and the opening accuracy and positioning accuracy of the metal mask may have errors, part of the area occupied by the sub-pixel is based on the above-mentioned The tolerance area reserved for process constraints is to avoid improper mixing of luminescent materials of sub-pixels of different colors during the process, resulting in improper color mixing that will seriously affect the luminous effect. For example, in the pixel U, the first sub-pixel 211 has a light-emitting region 211L and a tolerance region 211E, the L-shaped third sub-pixel 215 has a light-emitting region 215L and a tolerance region 215E, and the light-emitting region 215L is a light-emitting region 215L1 and a light-emitting region 215L2 The sum of tolerance area 215E is the sum of tolerance area 215E1 and tolerance area 215E2. Due to different processes, the area ratio of the tolerance area and the light emitting area may vary.

In this embodiment, taking the evaporation process as an example, when two adjacent sub-pixels have the same luminous color, the error width or error length at the adjacent position is about 5 micrometers (μm); when two adjacent sub-pixels have different The error width or error length of the adjoining part is about 12 microns when the color is emitted; the minimum size of the opening allowed by the process is about 6 microns. In other words, there may be a smaller error distance between sub-pixels with the same luminous color, and a larger error distance between sub-pixels with different luminous colors. Therefore, according to the embodiment of the present invention, each display unit S is adjacent to each other with the third sub-pixel 215 having the same luminous color, which can reduce the error distance between the sub-pixels (for example, from 12 microns to 5 microns), and at the same time The effect of keeping the sub-pixels in the adjacent area from color mixing and reducing the size of the display unit S or the pixel U is achieved, thereby realizing high-resolution (High PPI) product design.

As shown in Figure 1B, the opening width W1 and the opening length L1 of the light emitting region are about 6 microns, the error width W2 and the error length L2 are about 12 microns, the error width W3 and the error length L3 are about 5 microns, the opening of the light emitting area 215L1 The width W4 is about 13 microns, and the opening length L4 of the light emitting region 215L2 is about 43 microns. In particular, since the third sub-pixels 215 adjacent to the display unit S are adjacent to each other, the error width W3 and the error length L3 need not be designed to be 12 microns, but can be reduced to 5 microns, thereby effectively reducing the error between the display units S distance, thereby reducing the size of the pixel U. According to this, the size of the pixel U is 53 microns, and the pixel U is used as the calculation unit of the resolution (Resolution), and the pixel per inch (actual PPI) is 369. A special algorithm is used to achieve the effect of simulating high resolution with low resolution by sharing sub-pixels between adjacent pixels U, so that the virtual pixels per inch (virtual PPI) of the pixel U can reach 479. The light emitting region 211L of the first sub-pixel 211 occupies 2.6% of the total area (opening size), and the light emitting region 215L of the third sub-pixel 215 occupies 23.9% of the total area (opening size). In other words, it is defined that the light-emitting region of the first sub-pixel has a first light-emitting area, and the light-emitting region of the third sub-pixel has a third light-emitting area. In this embodiment, the ratio of the first light-emitting area to the third light-emitting area is approximately 2.6%:23.9%, approximately 1:10.

In this embodiment, when the size of the pixel U as shown in Figure 1B is 93 microns, and its pixel per inch is 273, it can be obtained after calculation. A pixel structure with a striped RGB configuration with a size of 93 microns has an aperture ratio of only 10.6%. In the pixel U shown in FIG. 1B of this embodiment, the first sub-pixel 211 and The second sub-pixel 213 has an aperture ratio of 48.93%, and the third sub-pixel 215 has an aperture ratio of 18.87%, both of which are larger than the aperture ratio of the pixel structure of the traditional strip RGB configuration.

Similarly, in this embodiment, the proportion of the light emitting region 213L of the second subpixel 213 to the total area is approximately the proportion of the total area of the light emitting region 211L of the first subpixel 211, so the light emitting region of the second subpixel is defined to have the first Two light emitting areas, in this embodiment, the ratio of the second light emitting area to the third light emitting area is about 2.6%:23.9%, approximately 1:10.

In another embodiment, the opening width W1 and the opening length L1 of the light emitting region are about 6 microns, the error width W2 and the error length L2 are about 12 microns, the error width W3 and the error length L3 are about 6 microns, and the light emitting region 215L1 The opening width W4 is about 12 microns, and the opening length L4 of the light emitting region 215L2 is about 36 microns. According to this, the size of the pixel U is 60 microns, and taking the pixel U as the calculation unit of the resolution, 320 pixels per inch (actual PPI) can be obtained. Using a special algorithm, the virtual pixels per inch (virtual PPI) of the pixel U can reach 416 by sharing the sub-pixels of the adjacent pixels U. The light emitting region 211L of the first sub-pixel 211 occupies 10.53% of the total area (opening size), and the light emitting region 215L of the third sub-pixel 215 occupies 23.22% of the total area (opening size). In other words, it is defined that the light-emitting region of the first sub-pixel has a first light-emitting area, and the light-emitting region of the third sub-pixel has a third light-emitting area. In this embodiment, the ratio of the first light-emitting area to the third light-emitting area is approximately 10.53%:23.22%, approximately 1:2.

Similarly, in this embodiment, the proportion of the light emitting region 213L of the second subpixel 213 to the total area is approximately the proportion of the total area of the light emitting region 211L of the first subpixel 211, so the light emitting region of the second subpixel is defined to have the first Two light-emitting areas, in this embodiment, the ratio of the second light-emitting area to the third light-emitting area is about 10.53%:23.22%, which is approximately 1:2.

To sum up, according to the embodiment of the present invention, the ratio of the first light emitting area to the third light emitting area is about 1:2-1:10, and the ratio of the second light emitting area to the third light emitting area is about 1: 2～1:10.

1D-1I are schematic top views of display units in a display device according to other embodiments of the present invention. The components in this embodiment that are the same as those in the preceding embodiments use the same component numbers, and for related descriptions of the same components, please refer to the above, and details will not be repeated here.

As shown in FIG. 1D , in this embodiment, the peripheral area P1 of the display unit S1 surrounds the core area C, and the number of the third sub-pixel 215 - 1 in the peripheral area P1 is one. As shown in FIG. 1E , in this embodiment, the peripheral area P2 of the display unit S2 surrounds the core area C, and the number of third sub-pixels 215 - 2 in the peripheral area P2 is four. As shown in FIG. 1F, in this embodiment, the peripheral area P3 of the display unit S3 surrounds the core area C, the number of the third sub-pixels 215-3 in the peripheral area P3 is four, and the third sub-pixels 215-3 is not rectangular in shape.

As shown in FIG. 1G, in this embodiment, in the display unit S4, the core region C includes a plurality of first sub-pixels 211, a plurality of second sub-pixels 213, and a plurality of fourth sub-pixels 217. These first sub-pixels 211 and the second sub-pixels 213 are alternately arranged, and the fourth sub-pixels 217 are respectively located between one of the first sub-pixels 211 and one of the second sub-pixels 213 . The peripheral region P4 includes a plurality of third sub-pixels 215 , and the fourth sub-pixels 217 and the third sub-pixels 215 emit light having the same primary color. For example, as shown in FIG. 1G, a display unit S4 includes two first sub-pixels 211, two second sub-pixels 213, four third sub-pixels 215, and two fourth sub-pixels 217, in which The third sub-pixels 215 of the peripheral area P4 of the unit S4 are disposed on three sides of the core area C, and the fourth sub-pixels 217 in the core area C are arranged adjacent to each other. In an embodiment, as shown in FIG. 1G , the display units S4 are repeatedly and regularly arranged on the substrate 100 in a matrix pattern (Array).

As shown in FIG. 1H, in this embodiment, in the display unit S5, the core area C includes a plurality of first sub-pixels 211, a plurality of second sub-pixels 213, and a plurality of fourth sub-pixels 217. These first sub-pixels 211 and the second sub-pixels 213 are alternately arranged, and the fourth sub-pixels 217 are respectively located between one of the first sub-pixels 211 and one of the second sub-pixels 213 . The peripheral area P5 includes a plurality of third sub-pixels 215 , and the fourth sub-pixels 217 and the third sub-pixels 215 emit light having the same primary color. In the display unit S5, as shown in FIG. 1H, the third sub-pixel 215 of the peripheral region P5 of the display unit S5 is arranged on two opposite sides of the core region C, and in one display unit S5, on one of the two opposite sides A fourth sub-pixel 217, a first sub-pixel 211, a second sub-pixel 213 and a fourth sub-pixel 217 are arranged in sequence on one side, and a second sub-pixel is arranged in sequence on the other side of the two opposite sides. A sub-pixel 211 , a fourth sub-pixel 217 , a fourth sub-pixel 217 and a second sub-pixel 213 . As shown in FIG. 1H , the display units S5 are repeatedly and regularly arranged on the substrate 100 in a matrix pattern (Array).

As shown in FIG. 1I, in this embodiment, in one display unit S6, the core region C includes a plurality of first sub-pixels 211, a plurality of second sub-pixels 213, and a plurality of fourth sub-pixels 217. These first sub-pixels The pixels 211 and the second sub-pixels 213 are alternately arranged, and the fourth sub-pixels 217 are respectively located between one of the first sub-pixels 211 and one of the second sub-pixels 213 . The peripheral area P6 includes a plurality of third sub-pixels 215 , and the fourth sub-pixels 217 and the third sub-pixels 215 emit light having the same primary color. In one display unit S6, as shown in FIG. 1I, the third sub-pixel 215 of the peripheral region P6 of the display unit S6 is arranged on two opposite sides of the core region C, and in one display unit S6, on one of the two opposite sides A fourth sub-pixel 217, a first sub-pixel 211, a second sub-pixel 213 and a fourth sub-pixel 217 are arranged in sequence on one side, and a A first sub-pixel 211 , a fourth sub-pixel 217 , a fourth sub-pixel 217 and a second sub-pixel 213 . As shown in FIG. 1I, the display units S6 are repeatedly and regularly arranged on the substrate 100 in a matrix pattern (Array). symmetry.

The following examples will be further described. The calculation results of the aperture ratios of the display device having the display units S, S4, S5 and S6 are listed below to illustrate the characteristics of the display substrate and the display device applying the present invention. However, the following examples are for illustrative purposes only, and should not be construed as limitations on the practice of the present invention.

Table 1 lists the calculation results of a display device with a pixel per inch (PPI) of 350 and a pixel size of 72.5 microns*72.5 microns as an example, wherein the aperture ratios of the first sub-pixel 211 and the second sub-pixel 213 are the same .

Table 1

FIG. 2 is a schematic top view of a display unit S matrix of a display structure 200 according to the present embodiment. In this embodiment, the display structure 200 may include a plurality of pixels U, and the display units S are repeatedly and regularly arranged on the substrate 100 in a matrix pattern (Array). As shown in FIG. 2 , the display units S are adjacent to each other by the third sub-pixel 215 .

FIG. 3 is a schematic top view of a display structure 300 according to yet another embodiment of the present invention. The components in this embodiment that are the same as those in the preceding embodiments use the same component numbers, and for related descriptions of the same components, please refer to the above, and details will not be repeated here.

In an embodiment, the display structure 300 is disposed on the substrate 100 , and the display structure 300 includes at least one display unit S. As shown in FIG. As shown in FIG. 3 , the display structure 300 may include a plurality of display units S, and the display units S are repeatedly and regularly arranged on the substrate 100 . In the display structure 300 , each display unit S is adjacent to each other by the third sub-pixel 215 . A display unit S includes, for example, two first sub-pixels 211, two second sub-pixels 213 and four third sub-pixels 215, wherein the first sub-pixels 211 and the second sub-pixels 213 are located in the core area C, and the third The sub-pixels 215 are located in the peripheral area.

In this embodiment, the first sub-pixels 211 are adjacent to each other and the second sub-pixels 213 are adjacent to each other. As shown in FIG. 3 , the first sub-pixel 211 located at the upper left part of the pixel structure 310 is adjacent to a second sub-pixel 213 and a first sub-pixel 211 with two adjacent sides 211s3 and 211s4 respectively.

As shown in FIG. 1C , the cover substrate 20 may be a glass substrate or a plastic substrate. In an embodiment, the cover substrate 20 may include a plurality of color filters, spacers, electrodes or touch unit circuits. The color filter can be used to enhance the luminous color quality of each sub-pixel of the luminous unit having different luminous colors. In other embodiments, the positions of the display substrate 200 and the cover substrate 20 can be interchanged, and each sub-pixel of the display unit S can also be replaced by a color filter for the defined sub-pixel area of each color light-emitting layer.

Please refer to FIGS. 4A˜4C , which illustrate a flow chart of an evaporation process of a light-emitting layer material according to an embodiment. The following is an example of evaporating multiple sub-pixels with three emission colors. As shown in FIG. 4A , a metal mask M1 is provided, and the metal mask M1 has a plurality of openings M10 corresponding to positions where the first sub-pixel 521p is to be formed. During evaporation, the first luminescent material 521 is plated on predetermined regions through the opening M10, and these regions are defined by the pixel definition layer 240 and separated from each other. Next, as shown in FIG. 4B , another metal mask M2 is provided. The metal mask M2 has a plurality of openings M20 corresponding to positions where the second sub-pixel 523p is to be formed. During vapor deposition, the second luminescent material 523 is plated on a predetermined area through the opening M20. Finally, as shown in FIG. 4C , another metal mask M3 is provided, and the metal mask M3 has a plurality of openings M30 corresponding to positions where the third sub-pixel 525p is to be formed. During vapor deposition, the third luminescent material 525 is plated on a predetermined area through the opening M20.

According to an embodiment of the present invention, the display unit S can be fabricated by using a suitable metal mask through an evaporation process. 5-8 are schematic diagrams of a metal mask for manufacturing a display unit S according to an embodiment of the present invention.

When manufacturing the display unit S of the embodiment, a metal mask as shown in FIGS. 5-7 can be used for vapor deposition. For example, the metal mask M5 shown in FIG. 5 has a plurality of openings M50, the metal mask M6 shown in FIG. 6 has a plurality of openings M60, and the metal mask M7 shown in FIG. 7 has a plurality of openings. M70. Two first sub-pixels 211 and two second sub-pixels 213 are produced by using the moving metal mask M5 for 4 times of vapor deposition, and an L-shaped third sub-pixel 215 is produced by using the metal mask M6 for one time of vapor deposition The vertical part of the vertical part, and the horizontal part of the L-shaped third sub-pixel 215 is fabricated by performing one vapor deposition using the metal mask M7. In the embodiment, the size of an opening is equal to the sum of the actual light-emitting area and the tolerance area of a sub-pixel, so the opening size of the metal mask can determine the size of the sub-pixel, and then determine the size of the display unit S and pixel U and affect the display device 1 resolution.

In particular, as shown in FIGS. 6-7, the openings M60/M70 of the metal masks M6/M7 can simultaneously produce sub-pixels 215 with the same luminescent color in different display units S, and further, without improving the accuracy of the evaporation process. In this case, the error distance between the display units S can be reduced, and the tolerance requirements on the manufacturing process can be effectively reduced, the tolerance area can be reduced, and the problem of color mixing of sub-pixels in the adjacent area and the problem that the light-emitting material cannot completely cover the area corresponding to the opening can be improved. And then realize high resolution (High PPI) product design.

Similarly, the metal mask M8 shown in FIG. 8 has a plurality of openings M80. Since the two first sub-pixels 211 and the two second sub-pixels 213 in the display unit S are adjacent to each other, two first sub-pixels can be produced by using the mobile metal mask M8 for only two evaporations. For the pixel 211 and the two second sub-pixels 213, the vertical part of the L-shaped third sub-pixel 215 is made by using the metal mask M6 for one evaporation, and the L-shaped third sub-pixel 215 is made by using the metal mask M7 for one evaporation. The horizontal portion of the third sub-pixel 215 is formed. In other words, in the display unit S, the two first sub-pixels 211 are adjacent to each other, and the two second sub-pixels 213 are adjacent to each other. The arrangement of the sub-pixels can effectively simplify the evaporation process.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection should be defined by the claims.

Claims (19)

1. a kind of display base plate, including：

One substrate；And

One display structure, is arranged in the substrate, which includes：

Multiple display units, the plurality of display unit is arranged in an array and respectively the display unit has a core space and a periphery Area, the wherein core space include at least one first sub-pixel and at least one second sub-pixel, which includes at least one the 3rd Sub-pixel, and the peripheral region is located at the outside of the core space, and the peripheral region is adjacent to the two neighboring side of the core space.

2. display base plate as claimed in claim 1, it is characterised in that the core space includes a pair of first sub-pixel and a pair Second sub-pixel, wherein the plurality of first sub-pixel and the plurality of second sub-pixel are staggered, the plurality of first sub-pixel Setting diagonally to each other, the plurality of second sub-pixel setting diagonally to each other.

3. display base plate as claimed in claim 1, it is characterised in that the side of the 3rd sub-pixel abuts first sub-pixel Or the side of second sub-pixel.

4. display base plate as claimed in claim 3, it is characterised in that the peripheral region includes multiple 3rd sub-pixels, this is more The side of a 3rd sub-pixel abuts the side of one of the plurality of first sub-pixel or the plurality of second sub-pixel respectively.

5. display base plate as claimed in claim 1, it is characterised in that respectively respectively first sub-pixel of the display unit, this Two sub-pixels and the 3rd sub-pixel include：

One first electrode layer, the neighbouring substrate；

One pixel defining layer, in the first electrode layer and has an opening portion；

One the second electrode lay, in the pixel defining layer；And

One luminescent layer, between the first electrode layer and the second electrode lay；

Wherein, which is more than the opening portion, and the first electrode layer area is more than the opening portion.

6. display base plate as claimed in claim 5, it is characterised in that the opening portion area definition respectively first sub-pixel, One light-emitting area of second sub-pixel and the 3rd sub-pixel, the core space include multiple first sub-pixels and it is multiple this Two sub-pixels, the peripheral region include multiple 3rd sub-pixels, and the plurality of first sub-pixel has one first light-emitting area, this is more A second sub-pixel has one second light-emitting area, and the plurality of 3rd sub-pixel has one the 3rd light-emitting area, this first shine Area or second light-emitting area are about 1 relative to the ratio of the 3rd light-emitting area:2~1:10.

7. display base plate as claimed in claim 1, it is characterised in that in the respectively display unit, which includes multiple First sub-pixel, multiple second sub-pixels and multiple 4th sub-pixels, the plurality of first sub-pixel and the plurality of second son Pixel is staggered, and the plurality of 4th sub-pixel is respectively positioned at one of the plurality of first sub-pixel and the plurality of second son Between one of pixel, and the peripheral region includes multiple 3rd sub-pixels.

8. display base plate as claimed in claim 7, it is characterised in that the plurality of 4th sub-pixel and the plurality of 3rd sub-pixel Send the light with identical light primary colors.

9. display base plate as claimed in claim 8, it is characterised in that the plurality of 3rd sub-pixel of the peripheral region is arranged at this Three sides of core space, the plurality of 4th sub-pixel in the core space is arranged adjacent one another.

10. display base plate as claimed in claim 8, it is characterised in that respectively in the display unit, the plurality of the of the peripheral region Three sub-pixels are arranged at the two opposite sides side of the core space, and a side therein on the two opposite sides side is sequential one 4th sub-pixel, first sub-pixel, second sub-pixel and the 4th sub-pixel, in the two opposite sides While other side while be sequential one first sub-pixel, the 4th sub-pixel, the 4th sub-pixel and One second sub-pixel.

11. display base plate as claimed in claim 10, it is characterised in that in the array that the plurality of display unit is arranged in In, two of the two adjacent columns display units are symmetrical.

12. a kind of display device, including：

One covering substrate；And

One display base plate, forms group the display device, which includes with the covering substrate：

One substrate；And

One display structure, is arranged in the substrate, which includes multiple display units, and the plurality of display unit is arranged in An array and the respectively display unit have a core space and a peripheral region, wherein the core space include at least one first sub-pixel and At least one second sub-pixel, the peripheral region include at least one the 3rd sub-pixel, and the peripheral region is located at the outside of the core space, And the peripheral region is adjacent to the two neighboring side of the core space.

13. display device as claimed in claim 12, it is characterised in that the core space of display base plate include it is a pair of this first Sub-pixel and a pair of second sub-pixel, wherein the plurality of first sub-pixel and the plurality of second sub-pixel are staggered, this is more A first sub-pixel setting diagonally to each other, the plurality of second sub-pixel setting diagonally to each other.

14. display device as claimed in claim 12, it is characterised in that the side adjoining of the 3rd sub-pixel of display base plate The side of first sub-pixel or second sub-pixel.

15. display device as claimed in claim 14, it is characterised in that the peripheral region of display base plate includes multiple three Sub-pixel, the side of the plurality of 3rd sub-pixel abut respectively the plurality of first sub-pixel or the plurality of second sub-pixel wherein it One side.

16. display device as claimed in claim 12, it is characterised in that in the respectively display unit, which includes more A first sub-pixel, multiple second sub-pixels and multiple 4th sub-pixels, the plurality of first sub-pixel and the plurality of second Sub-pixel is staggered, and the plurality of 4th sub-pixel is respectively positioned at one of the plurality of first sub-pixel and the plurality of second Between one of sub-pixel, and the peripheral region includes multiple 3rd sub-pixels, the plurality of 4th sub-pixel with it is the plurality of 3rd sub-pixel is sent with identical light primary colors light.

17. display device as claimed in claim 16, it is characterised in that the plurality of 3rd sub-pixel of the peripheral region is arranged at Three sides of the core space, the plurality of 4th sub-pixel in the core space is arranged adjacent one another.

18. display device as claimed in claim 16, it is characterised in that respectively in the display unit, the peripheral region it is the plurality of 3rd sub-pixel is arranged at the two opposite sides side of the core space, the core space include multiple first sub-pixels and it is multiple this second Sub-pixel, is one the 4th sub-pixel of sequential, the first sub- picture in one of two opposite sides side side Element, second sub-pixel and the 4th sub-pixel, the two opposite sides while other side while be sequential one A first sub-pixel, the 4th sub-pixel, the 4th sub-pixel and second sub-pixel.

19. display device as claimed in claim 12, it is characterised in that in the array that the plurality of display unit is arranged in In, two of the two adjacent columns display units are symmetrical.