CN105005450B - Data writing method, memory storage device and memory control circuit unit - Google Patents

Abstract

The present invention provides a data writing method, a memory storage device and a memory control circuit unit. The method includes: receiving a write instruction, wherein the write instruction indicates that data is written to a logical address, and the logical address belongs to a logical programming unit; when the physical erasing unit to which the physical programming unit mapped by the logical programming unit belongs is a first type of physical erasing unit, programming the data and the check code corresponding to the data into the physical programming unit according to a first code rate; and when the physical erasing unit is a second type of physical erasing unit, programming the data and the check code corresponding to the data into the physical programming unit according to a second code rate, wherein the first code rate is higher than the second code rate. In this way, the service life of the physical erasing unit with a higher bit error rate can be extended.

Description

Data writing method, memory storage device and memory control circuit unit

technical field

The present invention relates to a data writing mechanism, and in particular to a data writing method for a rewritable non-volatile memory module, a memory storage device and a memory control circuit unit.

Background technique

Digital cameras, mobile phones, and MP3 players have grown rapidly in recent years, making consumers' demand for storage media also increase rapidly. Since the rewritable non-volatile memory module (for example, flash memory) has the characteristics of data non-volatility, power saving, small size, and no mechanical structure, it is very suitable for being embedded in various portable multimedia devices listed above. device.

Generally speaking, the service life of each physical block in the rewritable non-volatile memory module is related to the erasing times of the physical block. After a physical block is repeatedly erased, error bits of data stored in the physical block will gradually increase. When the number of erroneous bits in the data exceeds the number that can be correctly corrected (for example, the erasure times of the physical block exceeds an upper limit of erasure times), the physical block is often discarded.

Contents of the invention

The present invention provides a data writing method, a memory storage device and a memory control circuit unit. When the bit error rate of the physical erasing unit increases, the physical erasing unit can be continuously used in a way with higher reliability , rather than discarding it directly.

The present invention provides a data writing method for controlling a rewritable non-volatile memory module. The rewritable non-volatile memory module includes a plurality of physical erasing units, each of which includes multiple physical erasing units. physical programming units, and the data writing method includes: receiving a write instruction, wherein the write instruction indicates to write a data to at least one of a plurality of logical units, wherein at least one of the logical units Mapping to the first physical programming unit in the physical programming unit, and the first physical programming unit belongs to the first physical erasing unit in the physical erasing unit; judging that the first physical erasing unit belongs to the first physical erasing unit A physical erasing unit of the type or a physical erasing unit of the second type, wherein the first bit error rate of the physical erasing unit of the first type is lower than the second bit error rate of the physical erasing unit of the second type; when the first physical erasing unit When the unit belongs to the first physical erasing unit, data and a check code corresponding to the data are programmed to the first physical programming unit according to a first code rate; and when the first physical erasing unit belongs to When the second type of physical unit is erased, the data and the check code corresponding to the data are programmed into the first physical programming unit according to the second code rate, wherein the first code rate is higher than the second code rate.

In an exemplary embodiment of the present invention, the step of judging that the first physical erasing unit belongs to the first type of physical erasing unit or the second type of physical erasing unit includes: judging the bit error rate of the first physical erasing unit Whether the evaluation value meets the threshold condition; if the bit error rate evaluation value of the first physical erasing unit does not meet the threshold condition, it is determined that the first physical erasing unit belongs to the first type of physical erasing unit; and if the first physical erasing unit’s The bit error rate evaluation value meets the threshold condition, and it is determined that the first physical erasing unit belongs to the second type of physical erasing unit.

In an exemplary embodiment of the present invention, the data writing method further includes: according to the erasing times information, writing times information, reading times information, error bit number information, error bit rate of the first physical erasing unit Information, at least one of data storage time information and temperature information, or a combination of at least two, to determine the bit error rate evaluation value of the first physical erasing unit.

In an exemplary embodiment of the present invention, the step of writing data and a check code corresponding to the data into the first physical programming unit according to the first code rate includes: dividing the data into at least one first data segment And generating at least one first check code segment, wherein each of the first check code segments corresponds to one of the first data segments. The step of writing the data and the check code corresponding to the data into the first physical programming unit according to the second code rate includes: dividing the data into at least one second data segment and generating at least one second check code segment , wherein each of the second check code segments corresponds to one of the second data segments. wherein a data length of each of the first data segments is the same as a data length of each of the second data segments, and a data length of each of the first check code segments is shorter than that of each of the first data segments A data length of the two-check code segment.

In an exemplary embodiment of the present invention, the step of writing the data and the check code corresponding to the data into the first physical programming unit according to the first code rate includes: dividing the data into at least one first data segments and generate at least one first check code segment, wherein each of the first check code segments corresponds to one of the first data segments. The step of writing the data and the check code corresponding to the data into the first physical programming unit according to the second code rate includes: dividing the data into at least one second data segment and generating at least one second check code segment , wherein each of the second check code segments corresponds to one of the second data segments. wherein a data length of each of the first data segments is longer than a data length of each of the second data segments, and a data length of each of the first check code segments is the same as that of each of the second A data length of the check code segment.

In an exemplary embodiment of the present invention, the step of writing the data and the check code corresponding to the data into the first physical programming unit according to the second code rate includes: judging whether the data length of the data exceeds N The data length of the basic management unit, where N is a positive integer, and the data length of N+1 basic management units is equal to the capacity of the first entity programming unit; when the data length of the data does not exceed the data length of N basic management units , only write the data and the check code corresponding to the data into the first physical programming unit according to the second code rate; and when the data length of the data exceeds the data length of N basic management units, write the data according to the second code rate The data of the first part and the check code of the first part are written into the first entity programming unit, and the data of the second part and the check code of the second part are written into the second entity program in the program entity unit. unit.

In an exemplary embodiment of the present invention, the second physical programming unit belongs to the first physical erasing unit or a second physical erasing unit among the physical erasing units also belongs to the second type of physical erasing unit.

In an exemplary embodiment of the present invention, the data length of the first part of data conforms to the data length of N basic management units, and the data writing method further includes: writing at least one first invalid bit into the first a physical programming unit to fill the unfilled part of the first part of the data and the first part of the check code; and writing at least one second invalid bit into the second physical programming unit to fill the unfilled part The part filled with the data of the second part and the check code of the second part.

The present invention further provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module and a memory control circuit unit. The connection interface unit is used to electrically connect to the host system. The rewritable non-volatile memory module includes a plurality of physical erasing units, and each of the physical erasing units includes a plurality of physical programming units. The memory control circuit unit is electrically connected to the connection interface unit and the rewritable non-volatile memory module. Wherein the memory control circuit unit is used to receive a write instruction, wherein the write instruction indicates to write data into at least one of a plurality of logic units, wherein at least one of the logic units is mapped to the physical programming unit The first physical programming unit, and the first physical programming unit belongs to the first physical erasing unit in the physical erasing unit. The memory control circuit unit is also used to determine whether the first physical erasing unit belongs to the first type of physical erasing unit or the second type of physical erasing unit, wherein the first bit error rate of the first type of physical erasing unit is lower than that of the second type The second bit error rate of the physical erasing unit. When the first physical erasing unit belongs to the first type of physical erasing unit, the memory control circuit unit is further configured to program data and a check code corresponding to the data into the first physical programming unit according to the first code rate. When the first physical erasing unit belongs to the second type of physical erasing unit, the memory control circuit unit is also used to program data and a check code corresponding to the data into the first physical programming unit according to the second code rate, wherein The first code rate is higher than the second code rate.

In an exemplary embodiment of the present invention, the operation of the memory control circuit unit judging that the first physical erasing unit belongs to the first type of physical erasing unit or the second type of physical erasing unit includes: judging the first physical erasing unit Whether the bit error rate evaluation value of the first physical erasing unit meets the threshold condition; if the bit error rate evaluation value of the first physical erasing unit does not meet the threshold condition, it is determined that the first physical erasing unit belongs to the first type of physical erasing unit; and if the first physical erasing unit The bit error rate evaluation value of the erasing unit meets the threshold condition, and it is determined that the first physical erasing unit belongs to the second type of physical erasing unit.

In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to, according to the erase count information, write count information, read count information, error bit number information, and error bit rate of the first entity erasing unit Information, at least one of data storage time information and temperature information, or a combination of at least two, to determine the bit error rate evaluation value of the first physical erasing unit.

In an exemplary embodiment of the present invention, the operation of the memory control circuit unit writing data and a check code corresponding to the data into the first physical programming unit according to the first code rate includes: dividing the data into at least one The first data segment and generating at least one first check code segment, wherein each of the first check code segments corresponds to one of the first data segments. The operation of the memory control circuit unit writing the data and the check code corresponding to the data into the first physical programming unit according to the second code rate includes: dividing the data into at least one second data segment and generating at least one second Check code segments, wherein each of the second check code segments corresponds to one of the second data segments. wherein a data length of each of the first data segments is the same as a data length of each of the second data segments, and a data length of each of the first check code segments is shorter than that of each of the first data segments A data length of the two-check code segment.

In an exemplary embodiment of the present invention, the operation of the memory control circuit unit writing data and a check code corresponding to the data into the first physical programming unit according to the first code rate includes: dividing the data into at least one The first data segment and generating at least one first check code segment, wherein each of the first check code segments corresponds to one of the first data segments. The operation of the memory control circuit unit writing the data and the check code corresponding to the data into the first physical programming unit according to the second code rate includes: dividing the data into at least one second data segment and generating at least one second Check code segments, wherein each of the second check code segments corresponds to one of the second data segments. wherein a data length of each of the first data segments is longer than a data length of each of the second data segments, and a data length of each of the first check code segments is the same as that of each of the second A data length of the check code segment.

In an exemplary embodiment of the present invention, the operation of the memory control circuit unit writing the data and the check code corresponding to the data into the first physical programming unit according to the second code rate includes: judging the data length of the data Whether it exceeds the data length of N basic management units, where N is a positive integer, and the data length of N+1 basic management units is equal to the capacity of the first entity programming unit; when the data length of the data does not exceed N basic management units When the data length of the data is longer than the second code rate, the data and the check code corresponding to the data are written to the first entity programming unit; and when the data length of the data exceeds the data length of N basic management units, according to the second code rate Write the data of the first part and the verification code of the first part into the first physical programming unit and write the data of the second part and the verification code of the second part into the physical programming unit A second entity programmatic unit.

In an exemplary embodiment of the present invention, a data length of the first part of data corresponds to a data length of N basic management units. The memory control circuit unit is also used for writing at least one first invalid bit into the first physical programming unit to fill up the part not filled by the first part of data and the first part of check code. The memory control circuit unit is also used for writing at least one second invalid bit into the second physical programming unit to fill up the part not filled by the second part of data and the second part of check code.

The present invention further provides a memory control circuit unit, which is used for controlling a rewritable non-volatile memory module. Wherein the rewritable non-volatile memory module includes a plurality of physical erasing units, each of which includes a plurality of physical programming units, and the memory control circuit unit includes a host interface, a memory interface, error checking and correction circuit and memory management circuit. The host interface is used to electrically connect to the host system. The memory interface is used for electrically connecting to the rewritable non-volatile memory module. The memory management circuit is electrically connected to the host interface, the memory interface and the error checking and correction circuit. Wherein the memory management circuit is used to receive a write instruction, wherein the write instruction indicates to write data to at least one of a plurality of logic units, wherein at least one of the logic units is mapped to the physical programming unit The first physical programming unit in the first physical programming unit, and the first physical programming unit belongs to a first physical erasing unit in the physical erasing unit. The memory control circuit unit is also used to determine whether the first physical erasing unit belongs to the first type of physical erasing unit or the second type of physical erasing unit, wherein the first bit error rate of the first type of physical erasing unit is lower than that of the second type The second bit error rate of the physical erasing unit. When the first physical erasing unit belongs to the first type of physical erasing unit, the memory management circuit is further configured to send a first instruction sequence, wherein the first instruction sequence indicates to convert the data to the calibration corresponding to the data according to the first code rate Code verification is programmed to the first entity programming unit. When the first physical erasing unit belongs to the second type of physical erasing unit, the memory management circuit is also used to send a second instruction sequence, wherein the second instruction sequence indicates to convert the data to the calibration corresponding to the data according to the second code rate Code checking is programmed to the first physical programming unit, wherein the first code rate is higher than the second code rate.

In an exemplary embodiment of the present invention, the operation of the memory management circuit judging that the first physical erasing unit belongs to the first type of physical erasing unit or the second type of physical erasing unit includes: judging the first physical erasing unit Whether the bit error rate evaluation value meets the threshold condition; if the bit error rate evaluation value of the first physical erasing unit does not meet the threshold condition, it is determined that the first physical erasing unit belongs to the first type of physical erasing unit; and if the first physical erasing unit The bit error rate evaluation value of the erasing unit meets the threshold condition, and it is determined that the first physical erasing unit belongs to the second type of physical erasing unit.

In an exemplary embodiment of the present invention, the memory management circuit is further configured to, according to the erase count information, write count information, read count information, error bit number information, and error bit rate information of the first physical erasing unit , at least one of data storage time information and temperature information or a combination of at least two of them to determine the bit error rate evaluation value of the first physical erasing unit.

In an exemplary embodiment of the present invention, the operation of the memory management circuit sending the first command sequence further includes: dividing the data into at least one first data segment and controlling the error checking and correction circuit to generate at least one first check code segments, wherein each of the first check code segments corresponds to one of the first data segments. The operation wherein the memory management circuit sends the second command sequence further includes: dividing the data into at least one second data segment and controlling the error checking and correction circuit to generate at least one second check code segment, wherein each of the second check code segments The code segment corresponds to one of the second data segments. wherein a data length of each of the first data segments is the same as a data length of each of the second data segments, and a data length of each of the first check code segments is shorter than that of each of the first data segments A data length of the two-check code segment.

In an exemplary embodiment of the present invention, the operation of the memory management circuit sending the first command sequence further includes: dividing the data into at least one first data segment and controlling the error checking and correction circuit to generate at least one first check code segments, wherein each of the first check code segments corresponds to one of the first data segments. The operation wherein the memory management circuit sends the second command sequence further includes: dividing the data into at least one second data segment and controlling the error checking and correction circuit to generate at least one second check code segment, wherein each of the second check code segments The code segment corresponds to one of the second data segments. wherein a data length of each of the first data segments is longer than a data length of each of the second data segments, and a data length of each of the first check code segments is the same as that of each of the second A data length of the check code segment.

In an exemplary embodiment of the present invention, the operation of the memory management circuit sending the second command sequence includes: judging whether the data length of the data exceeds the data length of N basic management units, where N is a positive integer, and N+1 The data length of a basic management unit is equal to the capacity of the first entity programming unit. When the data length of the data does not exceed the data length of N basic management units, send the second instruction sequence, wherein the second instruction sequence indicates that only the data and the check code corresponding to the data are written according to the second code rate To the first entity programming unit. When the data length of the data exceeds the data length of N basic management units, send the second command sequence, wherein the second command sequence indicates that the first part of the data and the first part of the check code need to be written according to the second code rate to the first physical programming unit and write the second part of the data and the second part of the verification code into a second physical programming unit of the physical programming unit.

In an exemplary embodiment of the present invention, the data length of the first part of data conforms to the data length of N basic management units. The second instruction sequence also indicates that at least one first invalid bit needs to be written into the first physical programming unit to fill up the part not filled by the first part of data and the first part of check code, and at least one The second invalid bit needs to be written into the second physical programming unit to fill up the part not filled by the second part of data and the second part of check code.

Based on the above, the data writing method, memory storage device and memory control circuit unit proposed by the present invention can be based on whether the physical erasing unit in the rewritable non-volatile memory module is the first type of physical erasing unit or the second type The physical erasing unit adaptively programs data and a check code corresponding to the data into the physical programming unit of the physical erasing unit according to the first code rate or a second code rate higher than the first code rate. In this way, even if the bit error rate of the physical erasing unit exceeds the preset allowable range, the physical erasing unit can still be used continuously instead of being discarded directly.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

Figure 1A illustrates a host system and memory storage device of an exemplary embodiment of the present invention;

FIG. 1B shows a schematic diagram of a computer, an input/output device, and a memory storage device according to an exemplary embodiment of the present invention;

FIG. 1C shows a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention;

Figure 2 shows a schematic block diagram of the memory storage device shown in Figure 1A;

FIG. 3 shows a schematic block diagram of a memory control circuit unit of an exemplary embodiment of the present invention;

FIG. 4 shows an exemplary schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention;

FIG. 5 shows an exemplary schematic diagram of sending data and a check code corresponding to the data to a physical programming unit according to a first code rate according to an exemplary embodiment of the present invention;

FIG. 6 shows an exemplary schematic diagram of writing data and a check code corresponding to the data into a physical programming unit according to a second code rate according to an exemplary embodiment of the present invention;

FIG. 7 shows an exemplary schematic diagram of writing data and a check code corresponding to the data into the physical programming unit according to another exemplary embodiment of the present invention;

FIG. 8 shows an exemplary schematic diagram of writing data and a check code corresponding to the data into a physical programming unit according to another exemplary embodiment of the present invention;

FIG. 9 shows a flowchart of a data writing method according to an exemplary embodiment of the present invention;

FIG. 10 shows a flowchart of a data writing method according to another exemplary embodiment of the present invention.

Explanation of reference signs:

1000: host system;

1100: computer;

1102: microprocessor;

1104: random access memory;

1106: input/output device;

1108: system bus;

1110: data transmission interface;

1202: mouse;

1204: keyboard;

1206: display;

1208: printer;

1212: U disk;

1214: memory card;

1216: SSD;

1310: digital camera;

1312: SD card;

1314: MMC card;

1316: memory stick;

1318: CF card;

1320: embedded storage device;

100: memory storage device;

102: connect the interface unit;

104: memory control circuit unit;

106: a rewritable non-volatile memory module;

304(0)～304(R): Entity erasing unit;

202: memory management circuit;

204: host interface;

206: memory interface;

252: buffer memory;

254: power management circuit;

256: error checking and correction circuit;

402: storage area;

406: system area;

410(0)～410(D): logical address;

501, 601, 701, 801: data;

510(0), 610(0), 710(0), 810(0): logic programming unit;

512(0), 612(0), 712(0), 812(0), 812(1): entity programming unit;

501_1～501_4, 601_1～601_4, 701_1～701_8, 801_1～801_5: data segment;

502_1～502_4, 602_1～602_4, 702_1～702_8, 802_1～802_5: check code segment;

S902, S904, S906, S908: each step of the data writing method;

S1002, S1004, S1006, S1008, S1010, S1012: each step of the data writing method.

Detailed ways

Generally speaking, a memory storage device (also called a memory storage system) includes a rewritable non-volatile memory module and a controller (also called a control circuit). Typically memory storage devices are used with a host system such that the host system can write data to or read data from the memory storage device.

Figure 1A shows a host system and a memory storage device of an exemplary embodiment of the present invention; Figure 1B shows a schematic diagram of a computer, an input/output device, and a memory storage device of an exemplary embodiment of the present invention; Figure 1C illustrates the present invention A schematic diagram of a host system and a memory storage device of an exemplary embodiment of FIG.

Referring to FIG. 1A , the host system 1000 generally includes a computer 1100 and an input/output (I/O) device 1106 . The computer 1100 includes a microprocessor 1102 , a random access memory (random access memory, RAM) 1104 , a system bus 1108 and a data transmission interface 1110 . The input/output device 1106 includes a mouse 1202, a keyboard 1204, a monitor 1206 and a printer 1208 as shown in FIG. 1B. It must be understood that the device shown in FIG. 2 is not limited to the input/output device 1106, and the input/output device 1106 may also include other devices.

In the embodiment of the present invention, the memory storage device 100 is electrically connected to other components of the host system 1000 through the data transmission interface 1110 . Data can be written into or read from the memory storage device 100 through the operations of the microprocessor 1102 , the random access memory 1104 and the input/output device 1106 . For example, the memory storage device 100 may be a rewritable non-volatile memory storage device such as a USB flash drive 1212, a memory card 1214, or a solid state drive (Solid State Drive, SSD) 1216 as shown in FIG. 2 .

In general, host system 1000 is any system that can cooperate substantially with memory storage device 100 to store data. Although in this exemplary embodiment, the host system 1000 is described as a computer system, however, in another exemplary embodiment of the present invention, the host system 1000 may be a digital camera, video camera, communication device, audio player or video player and other systems. For example, when the host system is a digital camera (video camera) 1310, the rewritable nonvolatile memory storage device 100 is an SD card 1312, an MMC card 1314, a memory stick (memory stick) 1316, and a CF card 1318. Or an embedded storage device 1320 (as shown in FIG. 1C ). The embedded storage device 1320 includes an embedded multimedia card (Embedded MMC, eMMC). It is worth mentioning that the embedded multimedia card is directly electrically connected to the substrate of the host system.

FIG. 2 shows a schematic block diagram of the memory storage device shown in FIG. 1A.

Referring to FIG. 2 , the memory storage device 100 includes a connection interface unit 102 , a memory control circuit unit 104 and a rewritable non-volatile memory module 106 .

In this exemplary embodiment, the connection interface unit 102 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it must be understood that the present invention is not limited thereto, and that the connection interface unit 102 may also be in accordance with the Parallel Advanced Technology Attachment (Parallel Advanced Technology Attachment, PATA) standard, the Institute of Electrical and Electronic Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standard , Peripheral Component Interconnect Express (PCI Express) standard, Universal Serial Bus (Universal Serial Bus, USB) standard, Ultra High Speed-I (UHS-I) interface standard, Ultra High Speed II (Ultra High Speed-II, UHS-II) interface standard, Secure Digital (Secure Digital, SD) interface standard, Memory Stick (MemoryStick, MS) interface standard, Multi Media Card (Multi Media Card, MMC) interface standard, small flash (CompactFlash, CF) interface standard, Integrated Device Electronics (IDE) standard, or other suitable standards. In this exemplary embodiment, the connection interface unit 102 and the memory control circuit unit 104 can be packaged in one chip, or arranged outside a chip including the memory control circuit unit 104 .

The memory control circuit unit 104 is used to execute a plurality of logic gates or control instructions implemented in the form of hardware or firmware, and write data in the rewritable non-volatile memory module 106 according to the instructions of the host system 1000, Read and erase operations.

The rewritable non-volatile memory module 106 is electrically connected to the memory control circuit unit 104 and used for storing data written by the host system 1000 . The rewritable non-volatile memory module 106 has physical erasing units 304 ( 0 )˜ 304 (R). For example, the physical erasing units 304(0)˜304(R) may belong to the same memory die or belong to different memory dies. Each physical erasing unit has a plurality of physical programming units, and the physical programming units belonging to the same physical erasing unit can be written independently and erased simultaneously. For example, each physical erasing unit is composed of 128 physical programming units. However, it must be understood that the present invention is not limited thereto, and each physical erasing unit may be composed of 64 physical programming units, 256 physical programming units, or any other number of physical programming units.

More specifically, each physical erasing unit includes a plurality of word lines and a plurality of bit lines, and a storage unit is arranged at the intersection of each word line and each bit line. Each memory cell can store one or more bits. In the same physical erasing unit, all storage units will be erased together. In this exemplary embodiment, the physical erasing unit is the smallest unit of erasing. That is, each physical erase unit contains a minimum number of memory cells that are erased. For example, the physical erasing unit is a physical block. On the other hand, storage units on the same word line will form one or more physical programming units. If each storage unit can store more than 2 bits, the physical programming units on the same word line can be classified into lower physical programming units and upper physical programming units. Generally speaking, the writing speed of the lower physical programming unit is greater than that of the upper physical programming unit. In this exemplary embodiment, the entity programming unit is the smallest unit of programming. That is, the entity programming unit is the smallest unit for writing data. For example, the entity programming unit is an entity page or an entity sector. In this exemplary embodiment, the physical programming unit is a physical page, and each physical programming unit includes a data bit area and a redundant bit area. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area is used for storing system data (eg, check code). In this exemplary embodiment, each data bit area includes 32 physical sectors, and the size of one physical sector is 512 bytes (byte, B). However, in other exemplary embodiments, the data bit area may also include 8, 16 or more or less physical sectors, and the present invention does not limit the size and number of physical sectors.

In this exemplary embodiment, the rewritable non-volatile memory module 106 is a multi-level cell (MultiLevel Cell, MLC) NAND flash memory module, that is, at least 2 bits can be stored in one memory cell. However, the present invention is not limited thereto, and the rewritable nonvolatile memory module 106 may also be a single-level memory cell (Single Level Cell, SLC) NAND flash memory module, a complex number-level memory cell (Trinary Level Cell, TLC) NAND type Flash memory modules, other flash memory modules, or other memory modules with the same characteristics.

FIG. 3 shows a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.

Referring to FIG. 3 , the memory control circuit unit 104 includes a memory management circuit 202 , a host interface 204 and a memory interface 206 .

The memory management circuit 202 is used to control the overall operation of the memory control circuit unit 104 . Specifically, the memory management circuit 202 has a plurality of control instructions, and when the memory storage device 100 is operating, these control instructions are executed to perform operations such as writing, reading, and erasing data. The following description of the operation of the memory management circuit 202 is equivalent to the description of the operation of the memory control circuit unit 104 , which will not be repeated below.

In this exemplary embodiment, the control commands of the memory management circuit 202 are implemented in the form of firmware. For example, the memory management circuit 202 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 100 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

In another exemplary embodiment of the present invention, the control instructions of the memory management circuit 202 may also be stored in a specific area of the rewritable non-volatile memory module 106 in the form of program codes (for example, in the memory module 106 dedicated to storing system data system area). In addition, the memory management circuit 202 has a microprocessor unit (not shown), a read only memory (not shown) and a random access memory (not shown). In particular, the ROM has a boot code (boot code), and when the memory control circuit unit 104 is enabled, the microprocessor unit will first execute the boot code to store in the rewritable non-volatile memory module The control instructions in 106 are loaded into the random access memory of the memory management circuit 202 . Afterwards, the microprocessor unit will execute these control instructions to perform operations such as writing, reading and erasing data.

In addition, in another exemplary embodiment of the present invention, the control instructions of the memory management circuit 202 may also be implemented in a hardware form. For example, the memory management circuit 202 includes a microcontroller, a memory management unit, a memory writing unit, a memory reading unit, a memory erasing unit and a data processing unit. The memory management unit, the memory writing unit, the memory reading unit, the memory erasing unit and the data processing unit are electrically connected to the microcontroller. Wherein, the memory management unit is used to manage the physical erasing unit of the rewritable non-volatile memory module 106; the memory write unit is used to issue a write command to the rewritable non-volatile memory module 106 to write data In the rewritable non-volatile memory module 106; the memory reading unit is used to issue a read instruction to the rewritable non-volatile memory module 106 to read data from the rewritable non-volatile memory module 106 ; The memory erasing unit is used to issue an erase command to the rewritable non-volatile memory module 106 to erase data from the rewritable non-volatile memory module 106; and the data processing unit is used to process the write-in Data to the rewritable nonvolatile memory module 106 and data read from the rewritable nonvolatile memory module 106 .

The host interface 204 is electrically connected to the memory management circuit 202 and is used for receiving and identifying commands and data transmitted by the host system 1000 . That is to say, the commands and data transmitted by the host system 1000 are transmitted to the memory management circuit 202 through the host interface 204 . In this exemplary embodiment, the host interface 204 is compatible with the SATA standard. However, it must be understood that the present invention is not limited thereto, and the host interface 204 may also be compatible with PATA standard, IEEE1394 standard, PCIExpress standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard , eMMC standard, UFS standard, CF standard, IDE standard or other suitable data transmission standards.

The memory interface 206 is electrically connected to the memory management circuit 202 and used for accessing the rewritable non-volatile memory module 106 . That is to say, the data to be written into the rewritable nonvolatile memory module 106 will be converted into a format acceptable to the rewritable nonvolatile memory module 106 via the memory interface 206 .

In an exemplary embodiment of the present invention, the memory control circuit unit 104 further includes a buffer memory 252 , a power management circuit 254 and an error checking and correction circuit 256 .

The buffer memory 252 is electrically connected to the memory management circuit 202 and used for temporarily storing data and instructions from the host system 1000 or data from the rewritable non-volatile memory module 106 .

The power management circuit 254 is electrically connected to the memory management circuit 202 and used for controlling the power of the memory storage device 100 .

The error checking and correcting circuit 256 is electrically connected to the memory management circuit 202 and used for executing error checking and correcting procedures to ensure the correctness of data. Specifically, when the memory management circuit 202 receives a write command from the host system 1000, the error checking and correction circuit 256 will generate a corresponding check code for the data corresponding to the write command, and the memory management circuit 202 will The data corresponding to the write command and the corresponding check code are written into the rewritable non-volatile memory module 106 . For example, the check code includes at least one of an error correcting code (ECC code) and an error detecting code (EDC code). In addition, the check code may also include any code that can be used to verify the correctness of the data, which is not limited in the present invention. Afterwards, when the memory management circuit 202 reads data from the rewritable non-volatile memory module 106, it will read the check code corresponding to the data at the same time, and the error checking and correction circuit 256 will check all the data according to the check code. The read data is subjected to error checking and correction procedures.

FIG. 4 shows an exemplary schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention.

It must be understood that when describing the operation of the physical erasing unit of the rewritable non-volatile memory module 106, words such as "extract", "group", "divide", and "associate" are used to operate the physical erase. A unit is a logical concept. That is to say, the actual position of the physical erasing unit of the rewritable non-volatile memory module 106 is not changed, but the physical erasing unit of the rewritable non-volatile memory module 106 is logically operated.

Please refer to FIG. 4, the memory management circuit 202 can logically divide the physical erasing units 304(0)-304(R) of the rewritable non-volatile memory module 106 into multiple areas, for example, the storage area 402 and the system District 406.

The physical erase unit of the storage area 402 is used to store data from the host system 1000 . Valid data and invalid data are stored in the storage area 402 . For example, when the host system wants to delete a piece of valid data, the deleted data may still be stored in the storage area 402, but it will be marked as invalid data. A physical erasing unit that does not store valid data is also called an idle physical erasing unit. Physical programming units that do not store valid data are also referred to as idle physical programming units. For example, the erased physical erasing unit becomes an idle physical erasing unit. If a physical erasing unit in the storage area 402 or the system area 406 is damaged, the physical erasing unit in the storage area 402 can also be used to replace the damaged physical erasing unit. If there is no available physical erasing unit in the storage area 402 to replace the damaged physical erasing unit, the memory management circuit 202 will declare the entire memory storage device 100 as a write-protected (write protect) state, and can no longer write data.

The physical erasing unit of the system area 406 is used to record system data, wherein the system data includes the manufacturer and model of the memory chip, the number of physical erasing units of the memory chip, and the number of physical programming units of each physical erasing unit Wait.

The number of physical erasing units in the storage area 402 and the system area 406 varies according to different memory specifications. In addition, it must be understood that during the operation of the memory storage device 100 , the grouping relationship of the physical erasing unit associated with the storage area 402 and the system area 406 will change dynamically. For example, when the physical erasing unit in the system area 406 is damaged and replaced by the physical erasing unit in the storage area 402 , the original physical erasing unit in the storage area 402 will be associated with the system area 406 .

The memory management circuit 202 configures the logical addresses 410(0)˜410(D) to be mapped to some of the physical erasing units 304(0)˜304(A) in the storage area 402 . The host system 1000 accesses the data in the storage area 402 through logical addresses 410(0)˜410(D). In this exemplary embodiment, one logical address is mapped to one physical sector, multiple logical addresses form a logical programming unit, and multiple logical programming units form a logical erasing unit. A logical programming unit may be mapped to one or more physical programming units, and a logical erasing unit may be mapped to one or more physical erasing units.

The memory management circuit 202 receives a write command from the host system 1000 . The write command indicates to write a data to one or more logical units. In this exemplary embodiment, a logical unit refers to a logical address (also referred to as a first logical address) among the logical addresses 410(0)˜410(D). The first logical address belongs to one or more first logical programming units, and the first logical programming units are mapped to one or more first physical programming units of the memory area 402 . However, in another exemplary embodiment, a logic unit may also refer to a logic programming unit (eg, the first logic programming unit). Before writing data into the first physical programming unit, the memory management circuit 202 will determine that the physical erasing unit (also referred to as the first physical erasing unit) to which the first physical programming unit belongs is the first type of physical erasing unit. unit or second-class entity programmatic unit. Among them, the bit error rate (bit error rate of the first type of physical erasing unit, the bit error rate of the first type of physical erasing unit is also called the first bit error rate) will be lower than that of the second type of physical programming unit. Error rate (also known as the second bit error rate). The bit error rate of the physical erasing unit refers to the proportion of error bits in the read data after the data stored in the physical erasing unit is read. In an exemplary embodiment, the second type of physical programming unit may also be called a high error rate physical programming unit.

In an exemplary embodiment, the memory management circuit 202 determines whether the evaluation value of the bit error rate of the first physical erasing unit meets a threshold condition. If the bit error rate evaluation value of the first physical erasing unit does not meet the threshold condition, the memory management circuit 202 determines that the first physical erasing unit belongs to the first type of physical erasing unit. If the bit error rate evaluation value of the first physical erasing unit meets the threshold condition, the memory management circuit 202 determines that the first physical erasing unit belongs to the second type of physical erasing unit. For example, in an exemplary embodiment, the bit error rate evaluation value of a physical erasing unit has two states, which are "0" or "1". Only when the estimated bit error rate of a physical erasing unit is "1", the memory management circuit 202 determines that the estimated bit error rate of the physical erasing unit meets the threshold condition.

Furthermore, in another exemplary embodiment, the bit error rate evaluation value of a physical erasing unit may have more than two states, and each state is related to the bit error rate of the physical erasing unit. In an exemplary embodiment, the evaluation value of the bit error rate may be any value in the range of 0-100. The higher the bit error rate evaluation value of a physical erasing unit is, the higher the bit error rate of the physical erasing unit is. The lower the bit error rate evaluation value of a physical erasing unit is, the lower the bit error rate of the physical erasing unit is. Only when the estimated bit error rate of the physical erasing unit reaches a threshold (for example, 70), the memory management circuit 202 determines that the estimated bit error rate of the physical erasing unit meets the threshold condition. In addition, the bit error rate evaluation value may also be expressed in any form, and is not limited to the above.

Generally, the bit error rate of the physical erasing unit is positively correlated with the times of erasing, writing and reading of the physical erasing unit. Wherein, the times of erasing, writing and reading of the physical erasing unit refer to the times of erasing, writing and reading of the physical erasing unit respectively. The higher at least one of the erasing times, the writing times and the reading times of a physical erasing unit is, the higher the number of error bits may be when the data stored in the physical erasing unit is read. many. Among them, the number of times of erasing has the greatest impact on the bit error rate of the physical erasing unit. In addition, in some cases, the bit error rate of the physical erasing unit may also be related to the data storage time and/or temperature of the physical erasing unit. The data storage time of the physical erasing unit refers to how long the data has been stored in the physical erasing unit, and can be the maximum or the average value of the storage time of each piece of data in a physical erasing unit, and Not limited to this. In addition, the temperature of each physical erasing unit in the rewritable non-volatile memory module 106 may be the same or different, but usually slightly different.

When at least one of the erasing times, writing times and reading times of a physical erasing unit exceeds a preset number of times, the data storage time of a physical erasing unit exceeds a preset time and/or a physical erasing unit When the temperature exceeds a preset temperature range, the number of error bits and/or the error bit rate contained in the data stored in the physical erasing unit will increase significantly when the data is read, and there is a high probability that it will exceed the error bit rate. The maximum number of erroneous bits that the check and correct circuitry 256 is capable of detecting and/or correcting. Therefore, in an exemplary embodiment, the memory management circuit 202 can, according to the erasure count information, write count information, read count information, error bit number information, error bit rate information, and data storage time information of a physical erasing unit and temperature information to determine the bit error rate evaluation value of the physical erasing unit. For example, in an exemplary embodiment, according to the erase count information, the memory management circuit 202 determines whether the erase count of the first physical erasing unit exceeds a preset count. The default number of times is, for example, preset by the manufacturer or set by the user. For example, the preset number of times may be 3000 or more or less. When the erasing times of the first physical erasing unit exceed the preset times, the memory management circuit 202 sets the bit error rate evaluation value of the first physical erasing unit to “1” or any corresponding value. Conversely, when the erasing times of the first physical erasing unit do not exceed the preset times, the memory management circuit 202 will set the bit error rate evaluation value of the first physical erasing unit to “0” or any corresponding value. value.

In other words, for a brand new rewritable nonvolatile memory module, all the physical erasing units in the rewritable nonvolatile memory module will be the first type of physical erasing units. However, as the usage time of the rewritable non-volatile memory module increases, more and more entity erasing units in the rewritable non-volatile memory module will be erased, The number of writing and/or reading operations is increased to become the second type of physical erasing unit. Or, according to the increase of data storage time and the change of temperature, part of the first-type physical erasing units may also be transformed into the second-type physical erasing units. In other words, any factor that affects the bit error rate of the physical erasing unit can be used as a basis for judging whether a physical erasing unit is the first type of physical erasing unit or the second type of physical erasing unit.

The memory management circuit 202 may record the physical erasing units determined to be the second type of physical erasing units in a table. When the memory management circuit 202 intends to write data into the first physical programming unit belonging to the first physical erasing unit, the memory management circuit 202 can query this table to know that the first physical erasing unit is a first type entity The erasing unit or the second type of entity erasing unit. In addition, the memory management circuit 202 may also associate the physical erasing unit determined as the second type of physical erasing unit with a high error rate area or a high error rate area in the storage area 402 in a partition or grouping manner. group, the present invention is not limited.

According to whether the first physical erasing unit is a first-type physical erasing unit or a second-type physical erasing unit, the memory management circuit 202 will selectively perform a code rate according to a first code rate or a second code rate The data and the check code corresponding to the data are programmed to the first physical programming unit, wherein the first code rate is higher than the second code rate. For example, when the first physical erasing unit is the first type of physical erasing unit, the memory management circuit 202 will program the data and the check code corresponding to the data into the first physical programming unit according to the first code rate . When the first physical erasing unit is the second type of physical erasing unit, the memory management circuit 202 programs the data and the check code corresponding to the data into the first physical programming unit according to the second code rate. In an example embodiment, programming may also be referred to as writing. That is to say, programming a piece of data into a physical programming unit is equivalent to writing a piece of data into a physical programming unit.

In detail, the memory management circuit 202 divides the data to be written into one or more data segments and controls the check and correction circuit 256 to generate one or more check code segments, wherein each check code segment corresponds to a data segment part. Here, a data segment is a unit used to generate a check code segment, and a check code segment is used to verify and/or correct its corresponding data segment. For example, assuming that k is the data length of a data segment, and n-k is the data length of a parity code segment corresponding to this data segment, the ratio of k to n (ie, k/n) can be called a code rate. In particular, if the data length of the data to be written matches the data length of a data segment, the data itself is a data segment, and the check code corresponding to the data is the check code segment corresponding to the data segment. If the data length of the data to be written conforms to the sum of the data lengths of multiple data segments, the data can be divided into multiple data segments, and the check code corresponding to this data will include corresponding to these data segments Multiple checksum segments.

In this exemplary embodiment, when the first physical erasing unit is the first type of physical erasing unit, the memory management circuit 202 performs the operation according to the preset data length of the data segment and the data length of the check code segment (that is, the first A code rate) to write the data to be written and the corresponding check code into the first physical programming unit.

FIG. 5 shows an exemplary schematic diagram of sending data and a check code corresponding to the data to a physical programming unit according to a first code rate according to an exemplary embodiment of the present invention.

Referring to FIG. 5 , assume that the write command from the host system 1000 indicates to write data 501 to the logical address 410 (0). For example, the data length of the data 501 is 4KB (1KB=1024bytes). Assuming that the logical address 410(0) belongs to the logical programming unit 510(0), the memory management circuit 202 will write the data 501 into the logical programming unit 510(0). Logical programming unit 510(0) maps to physical programming unit 512(0). When the physical erasing unit 304(0) to which the physical programming unit 512(0) belongs is the first type of physical erasing unit, based on the data length of the data 501, the memory management circuit 202 divides the data 501 into data segments 501_1~ 501_4. For example, the data length of each data segment 501_1-501_4 is 1KB. The checking and correcting circuit 256 generates check code segments 502_1 - 502_4 corresponding to the data segments 501_1 - 501_4 . For example, the data length of each check code segment 502_1˜502_4 is 70B (1B=1bytes). That is to say, when a data segment with a data length of 1KB is read, the data segment can be verified and/or corrected according to a check code segment with a data length of 70B. The memory management circuit 202 writes the data segments 501_1 - 501_4 and the check code segments 502_1 - 502_4 into the physical programming unit 512 ( 0 ) according to a preset rule. For example, in this exemplary embodiment, each physical address range for storing the verification code segment is continuous with the physical address range for storing the data segment corresponding to the verification code segment (as shown in FIG. 5 ). However, in another exemplary embodiment, all data segments and check code segments may also be stored separately. For example, all data segments are stored in the physical address range where user data is stored, and all check code segments are stored in the physical address range where redundant data is stored.

On the other hand, in this exemplary embodiment, when the first physical erasing unit is the second type of physical erasing unit, the memory management circuit 202 will increase the data length of the check code segment corresponding to each data segment to Write the data to be written and the corresponding check code into the first physical programming unit according to the preset data length of the data segment and the longer data length of the check code segment (that is, the second code rate). .

FIG. 6 shows an exemplary schematic diagram of writing data and a check code corresponding to the data into a physical programming unit according to a second code rate according to an exemplary embodiment of the present invention.

Referring to FIG. 6 , assume that the write command from the host system 1000 indicates to write data 601 to the logical address 410(1). For example, the data length of the data 501 is 4KB. Assuming that the logical address 410(1) belongs to the logical programming unit 610(0), the memory management circuit 202 will write the data 601 into the logical programming unit 610(0). Logical programming unit 610(0) maps to physical programming unit 612(0). When the physical erasing unit 304(1) to which the physical programming unit 612(0) belongs is the second type of physical erasing unit, based on the data length of the data 601, the memory management circuit 202 divides the data 601 into data segments 601_1~ 601_4. For example, the data length of each data segment 601_1~601_4 is 1KB. The checking and correcting circuit 256 generates check code segments 602_1 - 602_4 corresponding to the data segments 601_1 - 601_4 . For example, the data length of each check code segment 602_1 - 602_4 is 140B. That is to say, in this exemplary embodiment, the data length of each check code segment is twice the data length of each check code segment in the exemplary embodiment of FIG. 5 , and is not limited thereto. For example, this multiple can also be 3 times, 4 times or more. The memory management circuit 202 writes the data segments 601_1 - 601_4 and the check code segments 602_1 - 602_4 into the physical programming unit 612 ( 0 ) according to the above preset rules. That is to say, when a data segment with a data length of 1KB is read, the data segment can be verified and/or corrected according to a check code segment with a data length of 140B. Thus, even if the physical erasing unit used to store data is the second type of physical erasing unit, more error bits in the read data can be found and/or corrected. For example, in the exemplary embodiment of Fig. 5, 1 data length is that the error bit of 40bits can be found in the data segment of 1KB approximately, and in this exemplary embodiment, 1 data length is that in the data segment of 1KB may There are 80bits of error bits that can be found.

However, in another exemplary embodiment, when the first physical erasing unit is the second type of physical erasing unit, the memory management circuit 202 does not change the data length of the check code segment, but reduces each data segment to write the data to be written and the corresponding check code into the A first entity programming unit.

FIG. 7 shows an exemplary schematic diagram of writing data and a check code corresponding to the data into a physical programming unit according to another exemplary embodiment of the present invention.

Referring to FIG. 7 , assume that the write command from the host system 1000 indicates to write data 701 to the logical address 410 ( 2 ). For example, the data length of data 701 is 4KB. Assuming that the logical address 410(2) belongs to the logical programming unit 710(0), the memory management circuit 202 will write the data 701 into the logical programming unit 710(0). Logical programming unit 710(0) maps to physical programming unit 712(0). When the physical erasing unit 304(2) to which the physical programming unit 712(0) belongs is the second type of physical erasing unit, based on the data length of the data 701, the memory management circuit 202 divides the data 701 into data segments 701_1~ 701_8. For example, the data length of each data segment 701_1-701_8 is 512B. That is to say, in this exemplary embodiment, the data length of each data segment is 1/2 times the data length of each data segment in the exemplary embodiment of FIG. 5 , and is not limited thereto. For example, this multiple can also be 1/3 times, 1/4 times or less. The checking and correcting circuit 256 generates check code segments 702_1 - 702_8 corresponding to the data segments 701_1 - 701_8 . For example, the data length of each check code segment 702_1 - 702_8 is 70B. The memory management circuit 202 writes the data segments 701_1 - 701_8 and the check code segments 702_1 - 702_8 into the physical programming unit 712 ( 0 ) according to the above preset rules. That is to say, when a data segment with a data length of 512B is read, the data segment can be verified and/or corrected according to a check code segment with a data length of 70B. Thus, even if the physical erasing unit used to store data is the second type of physical erasing unit, more error bits in the read data can be found and/or corrected. For example, in the exemplary embodiment of Fig. 5, about 40 bits of erroneous bits can be found in a data segment whose data length is 1KB, and in this exemplary embodiment, may be found in a data segment whose data length is 512B There are 40bits of error bits that can be found. By analogy, in two data segments whose total data length is 1KB, there may be 80 bits of error bits that can be found.

It is worth mentioning that, according to the definition of the above code rate (that is, k/n), the first code rate in the exemplary embodiment of FIG. 5 can be represented by 1024/(1024+70), and the The second code rate in the exemplary embodiment may be represented by 1024/(1024+140), and the second code rate in the exemplary embodiment of FIG. 7 may be represented by 512/(512+70). That is to say, when the bit error rate of a physical erasing unit is increased to the point that the preset error detection mechanism cannot be used to detect errors, by using a lower code rate to encode the data to be written into this physical erasing unit, This physical erasing unit can still continue to be used, and it does not need to be immediately regarded as an unusable or damaged physical erasing unit.

It is worth mentioning that, in the exemplary embodiment shown in Figure 5, only one physical programming unit is needed to completely store the data whose data length does not exceed the capacity of one logical programming unit and the check code corresponding to this data . For example, assuming that the capacity of the entity programming unit 512(0) is 8KB, as long as the data length of the data 501 does not exceed 8KB, then the data 501 and the check code corresponding to the data 501 can be completely written into the entity program UL unit 512(0). In another embodiment of writing data and a check code corresponding to the data according to the second code rate, assuming that the capacity of the entity programming unit 512(0) is 16KB, as long as the data length of the data 501 does not exceed 16KB, the data 501 and the check code corresponding to the data 501 can be completely written into the physical programming unit 512(0). In addition, the capacity of the entity programming unit may also be 32KB or larger, but is not limited thereto. However, in the exemplary embodiments of FIG. 6 and FIG. 7 , the data length of the data to be written remains unchanged, but the data length of the check code corresponding to the data increases. Therefore, in some examples, even if the desired The data length of the written data does not exceed the capacity of a logical programming unit, but the sum of the data length of this data and the data length of the check code corresponding to this data may still exceed the capacity of a physical programming unit size. In this case, the memory management circuit 202 usually uses two or more physical programming units to store data and a check code corresponding to the data. That is, a part of the data to be written (also referred to as the first part) is written into the first physical programming unit, and another part of the data to be written (also referred to as the second part) is written into a A second entity programmatic unit. For example, assuming that the capacity of the first physical programming unit is 8KB, then in an exemplary embodiment, the first physical programming unit can be used to store data with a data length of 7KB at most and a corresponding data length of 980B (that is, , 7×140 or 14×70) check code. If the data length of the data to be written is 8KB, the first part of the data with a data length of 7KB will be written to the first entity programming unit, and the second part of the data with a data length of 1KB will be will be written to the second physical programming unit. For example, the second physical programming unit may be any physical erasing unit that belongs to the above-mentioned first physical erasing unit, and also belongs to the second type of physical erasing unit in the storage area 402, or any physical erasing unit. The present invention does not be restricted.

In an exemplary embodiment, the memory management circuit 202 uses a specific data length as a basic management unit, and writes data into the rewritable non-volatile memory module 106 according to the basic management unit. For example, the data length of one basic management unit is 4KB, and is not limited thereto. The capacity of a physical programming unit can be the data length corresponding to one or more basic management units. For example, when the capacity of the physical programming unit is 8KB, the capacity of the physical programming unit corresponds to the data length of 2 basic management units. When the capacity of the physical programming unit is 16KB, the capacity of the physical programming unit corresponds to the data length of 4 basic management units, and so on. Taking the physical programming unit with a capacity of 8KB as an example, when the data length of the data to be written into the physical programming unit does not exceed the data length of a basic management unit, the memory management circuit 202 uses a basic management unit to write This data is written to this entity programmatic unit. When the data length of the data to be written exceeds the data length of one basic management unit and does not exceed the data length of two basic management units, the memory management circuit 202 writes the data into the entity program in two basic management units unit.

In this exemplary embodiment, it is assumed that the capacity of a physical programming unit corresponds to the data length of N+1 basic management units, where N is a positive integer. For example, N may be 1, 3 or 5, and is not limited thereto. When the first physical programming unit is the second type of physical erasing unit, the memory management circuit 202 will judge whether the data length of the data to be written exceeds the data length of N basic management units, where N is the data length of the first physical program Depends on the capacity of the unit. For example, when the capacity of the physical programming unit is 8KB, it means that the capacity of the physical programming unit conforms to the data length of 2 basic management units, so N is 1. When the capacity of the physical programming unit is 16KB, it means that the capacity of the physical programming unit conforms to the data length of 4 basic management units, so N is 3, and so on. When the first physical erasing unit is the second type of physical erasing unit and the data length of the data to be written does not exceed the data length of N basic management units, the memory management circuit 202 can write the data to be written only according to the second code rate. The written data and the verification code corresponding to the data are written into the first physical programming unit. Conversely, when the first physical erasing unit is the second type of physical erasing unit and the data length of the data to be written exceeds the data length of N basic management units, the memory management circuit 202 will write the data to be written according to the second code rate. A first part of the input data and a first part of the verification code corresponding to the data are written into the first physical programming unit, and a second part of the data to be written and corresponding to the verification code are written according to the second code rate A second part of the verification code of the data is written into the second physical programming unit. For example, the second physical programming unit may be any physical erasing unit that belongs to the above-mentioned first physical erasing unit, and also belongs to the second type of physical erasing unit in the storage area 402, or any physical erasing unit. The present invention does not be restricted.

FIG. 8 shows an exemplary schematic diagram of writing data and a check code corresponding to the data into a physical programming unit according to another exemplary embodiment of the present invention.

Referring to FIG. 8 , assume that a write command from the host system 1000 indicates to write data 801 to the logical address 410 ( 3 ). For example, the data length of the data 801 is 5KB. Assuming that the logical address 410(3) belongs to the logical programming unit 810(0), the memory management circuit 202 will write the data 801 into the logical programming unit 810(0). Logical programming unit 810(0) maps to physical programming unit 812(0). When the physical erasing unit 304(3) to which the physical programming unit 812(0) belongs is the second type of physical erasing unit, based on the data length of the data 801, the memory management circuit 202 divides the data 801 into data segments 801_1~ 801_5. For example, the data length of each data segment 801_1-801_5 is 1KB. The checking and correcting circuit 256 generates check code segments 802_1 - 802_5 corresponding to the data segments 801_1 - 801_5 . For example, the data length of each check code segment 802_1 - 802_5 is 140B. In addition, the data 801 can also be divided into more data segments (for example, 10 data segments whose data length is 512B, etc.) in the manner of the exemplary embodiment of FIG. 7 , and the data length of each check code segment can be The data length (for example, 70B) set as the preset check code segment is not limited by the present invention. The memory management circuit 202 determines whether the data length of the data 801 exceeds the data length of N basic management units. Here, it is assumed that the capacity of the physical programming unit 812(0) is 8KB, so N is 1. The memory management circuit 202 will determine whether the data length of the data 801 (for example, 5KB) exceeds the data length of a basic management unit (for example, 4KB). When the data length of the data 801 exceeds the data length of a basic management unit, the memory management circuit 202 will write the data segments 801_1-801_4 and the check code segments 802_1-802_4 corresponding to the data segments 801_1-801_4 into the physical programming unit 812(0), and write the data segment 801_5 and the check code segment 802_5 corresponding to the data segment 801_5 into the entity programming unit 812(1), wherein the data lengths of the data segments 801_1~801_4 conform to the requirements of a basic management unit Data length. Although in this exemplary embodiment the second physical programming unit is an example of the physical programming unit 812(1) that also belongs to the physical erasing unit 304(3), in another exemplary embodiment, the second physical The programming unit may also be any physical erasing unit that belongs to the second type of physical erasing unit in the storage area 402 or any physical erasing unit. That is, after data 801 is written to physical programming units 812(0) and 812(1), logical programming unit 810(0) is mapped to physical programming units 812(0) and 812(1) . In addition, if the capacity of the physical programming unit 812(0) is 16KB or more, it is only necessary to set N to 3 or a corresponding value.

In addition, in the exemplary embodiments of FIG. 5 to FIG. 8 , when the memory management circuit 202 writes the data segment and the check code segment into the first physical programming unit, the memory management circuit 202 will simultaneously write one or more A first invalid bit is written into the part of the first physical programming unit that is not filled by the data segment and the check code segment. Similarly, when the memory management circuit 202 writes the data segment and the check code segment into the programming unit of the second entity, the memory management circuit 202 will also write one or more second invalid bits into the second entity The part of the programming unit that is not filled by the data segment and the check code segment. The first invalid bit and the second invalid bit may be any invalid data.

FIG. 9 shows a flowchart of a data writing method according to an exemplary embodiment of the present invention.

Please refer to FIG. 9 , in step S902, a write instruction is received, wherein the write instruction indicates to write data to at least one of a plurality of logical units, wherein at least one of the logical units is mapped to the first A physical programming unit, and the first physical programming unit belongs to the first physical erasing unit.

In step S904, it is determined whether the first physical erasing unit is a first type physical erasing unit or a second type physical erasing unit.

When the first physical erasing unit is the first type of physical erasing unit, in step S906, the data and the check code corresponding to the data are programmed into the first physical programming unit according to the first coding rate.

When the first physical erasing unit is the second type of physical erasing unit, in step S908, program the data and the check code corresponding to the data into the first physical programming unit according to the second code rate, Wherein the first code rate is higher than the second code rate.

FIG. 10 shows a flowchart of a data writing method according to another exemplary embodiment of the present invention.

Please refer to FIG. 10 , in step S1002, a write instruction is received, wherein the write instruction indicates to write data to at least one of a plurality of logical units, wherein at least one of the logical units is mapped to the first A physical programming unit, and the first physical programming unit belongs to the first physical erasing unit.

In step S1004, it is determined whether the first entity erasing unit is a first type entity erasing unit or a second type entity erasing unit.

When the first physical erasing unit is the first type of physical erasing unit, in step S1006, write the data and the check code corresponding to the data into the first physical programming unit according to the first code rate.

When the first physical erasing unit is the second type of physical erasing unit, in step S1008, it is judged whether the data length of this data exceeds the data length of N basic management units, wherein N is a positive integer, and N+1 basic management units The data length of the management unit is equal to the capacity of the first entity programming unit.

When the data length of the data does not exceed the data length of N basic management units, in step S1010, write the data and the check code corresponding to the data into the first entity programming unit only according to the second code rate .

When the data length of the data exceeds the data length of N basic management units, in step S1012, write the first part of the data and the first part of the check code into the first entity programming unit according to the second code rate And write the data of the second part and the verification code of the second part into the second entity programming unit.

However, each step in FIG. 9 and FIG. 10 has been described in detail above, and will not be repeated here. It should be noted that each step in FIG. 9 and FIG. 10 can be implemented as a plurality of program codes or circuits, and the present invention is not limited thereto. In addition, the methods shown in FIG. 9 and FIG. 10 can be used together with the above embodiments, or can be used alone, and the present invention is not limited thereto. In particular, in this exemplary embodiment, various operations of the rewritable non-volatile memory module 106, such as writing or reading data and/or verification codes performed by the memory management circuit 202, are performed, for example, by Send at least one command sequence to the rewritable non-volatile memory module 106 to complete, wherein each command sequence includes at least one command. The rewritable non-volatile memory module 106 can perform corresponding operations in series according to the received instructions.

In addition, in another exemplary embodiment, the above-mentioned judging steps can also be applied to the physical programming unit or the physical fan. For example, it can be judged according to the methods mentioned in the above exemplary embodiments that the first physical programming unit is the first type of physical programming unit or the second type of physical programming unit, and according to the judgment result, it is determined whether the first code rate or The second code rate is used to write the data and the corresponding check code into the first physical programming unit. In particular, different physical programming units or physical sectors in the same physical erasing unit may also have different bit error rates, so this approach may be closer to the actual memory usage.

In summary, the data writing method, memory storage device and memory control circuit unit proposed by the present invention can be based on whether the physical erasing unit in the rewritable non-volatile memory module is the first type of physical erasing unit or the second type of physical erasing unit. The second type of physical erasing unit adaptively writes data and a check code corresponding to the data into the physical erasing unit according to the first code rate or a second code rate higher than the first code rate. In this way, even if the bit error rate of a certain physical erasing unit exceeds the preset allowable range, the physical erasing unit can still be used continuously instead of being discarded directly.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present invention. scope.

Claims (24)

1. a kind of method for writing data, for controlling a reproducible nonvolatile memorizer module, the duplicative is non-volatile Property memory module includes multiple entity erased cells, and each of entity erased cell includes multiple entity program units, It is characterized in that, and the method for writing data include：

Receive a write instruction, wherein write instruction instruction by a data be written into multiple logic units at least within it One, wherein in those logic units this at least one map to the first instance journey in those entity program units Sequence unit, and the first instance programmed cell belongs to the first instance erased cell in those entity erased cells；

Judge that the first instance erased cell belongs to a first kind entity erased cell or one second class entity erased cell；

When the first instance erased cell belongs to the first kind entity erased cell, according to one first code check by the data with It is programmed to the first instance programmed cell corresponding to a check code of the data；And

When the first instance erased cell belongs to the second class entity erased cell, according to one second code check by the data with It is programmed to the first instance programmed cell corresponding to the check code of the data, wherein first code check is higher than the second code Rate,

The data and the check code corresponding to the data are wherein programmed to the first instance program according to second code check Change unit the step of include：

When the data length of the data is no more than the data length of N number of basic management unit, according to second code check by the number It is programmed to the first instance programmed cell according to the check code corresponding to the data；And

It, will according to second code check when the data length of the data is more than the data length of N number of basic management unit The data of one first part and the check code of a first part are programmed to the first instance programmed cell and by one the The data of two parts are programmed to the second instance journey in those entity program units with the check code of a second part Sequence unit.

2. method for writing data according to claim 1, which is characterized in that judge that the first instance erased cell belongs to this The step of first kind entity erased cell or the second class entity erased cell includes：

Judge whether a bit error rate assessed value of the first instance erased cell meets a Sharp criteria；

If the bit error rate assessed value of the first instance erased cell does not meet the Sharp criteria, judge that the first instance is smeared Except unit belongs to the first kind entity erased cell；And

If the bit error rate assessed value of the first instance erased cell meets the Sharp criteria, judge that the first instance is erased Unit belongs to the second class entity erased cell.

3. method for writing data according to claim 2, which is characterized in that further include：

It erases a number information, write-in number information, a reading times information, one wrong according to the one of the first instance erased cell Errored bit number information, a wrong bitrate information, a data resting period information and a temperature information at least one or At least combination, to determine the bit error rate assessed value of the first instance erased cell.

4. method for writing data according to claim 1, which is characterized in that

The data and the check code corresponding to the data are programmed to the first instance sequencing list according to first code check Member step include：

The data are divided at least one first data segment and generate at least one first check code section, wherein it is each this at least 1 the One check code section corresponds at least one of one first data segment,

The data and the check code corresponding to the data are wherein programmed to the first instance program according to second code check Change unit the step of include：

The data are divided at least one second data segment and generate at least one second check code section, wherein it is each this at least 1 the Two check code sections correspond at least one of one second data segment,

One data length of wherein each at least one first data segment is identical to a number of each at least one second data segment It is shorter than each at least one second check code section according to a data length of length, and each at least one first check code section One data length.

5. method for writing data according to claim 1, which is characterized in that

The data and the check code corresponding to the data are programmed to the first instance sequencing list according to first code check Member step include：

The data are divided at least one first data segment and generate at least one first check code section, wherein it is each this at least 1 the One check code section corresponds at least one of one first data segment,

The data and the check code corresponding to the data are wherein programmed to the first instance program according to second code check Change unit the step of include：

The data are divided at least one second data segment and generate at least one second check code section, wherein it is each this at least 1 the Two check code sections correspond at least one of one second data segment,

One data length of wherein each at least one first data segment is longer than a data of each at least one second data segment Length, and a data length of each at least one first check code section is identical to each at least one second check code section One data length.

6. method for writing data according to claim 1, which is characterized in that according to second code check by the data with it is right Should include the step of the check code of the data is programmed to the first instance programmed cell：

Judge the data the data length whether be more than N number of basic management unit the data length, wherein N is just whole Number, and a data length of N+1 basic management unit is equal to an amount of capacity of the first instance programmed cell.

7. method for writing data according to claim 6, which is characterized in that the second instance programmed cell belong to this The second instance that the second class entity erased cell is also belonged in one entity erased cell or those entity erased cells is smeared Except unit.

8. method for writing data according to claim 5, which is characterized in that a data of the data of the first part are long Degree meets the data length of N number of basic management unit, and the method for writing data further includes：

At least one first inactive bit is programmed in the first instance programmed cell to fill up not being somebody's turn to do by the first part Data and the check code of the first part write full part；And

At least one second inactive bit is programmed in the second instance programmed cell to fill up not being somebody's turn to do by the second part Data and the check code of the second part write full part.

9. a kind of memory storage apparatus, which is characterized in that including：

One connecting interface unit, to be electrically connected to a host system；

One reproducible nonvolatile memorizer module, including multiple entity erased cells, and each of entity is erased list Member includes multiple entity program units；And

One memorizer control circuit unit is electrically connected to the connecting interface unit and the type nonvolatile mould Block,

To receive a write instruction, one data are written the wherein memorizer control circuit unit for wherein write instruction instruction To at least one of multiple logic units, wherein in those logic units this at least one map to those entities A first instance programmed cell in programmed cell, and the first instance programmed cell belongs to those entities and erases list A first instance erased cell in member,

The memorizer control circuit unit is also judging that the first instance erased cell belongs to a first kind entity erased cell Or one second class entity erased cell, wherein one first bit error rate of the first kind entity erased cell are less than second class One second bit error rate of entity erased cell,

When the first instance erased cell belongs to the first kind entity erased cell, the memorizer control circuit unit also to The data and the check code corresponding to the data are programmed to the first instance programmed cell according to one first code check,

When the first instance erased cell belongs to the second class entity erased cell, the memorizer control circuit unit also to The data and the check code corresponding to the data are programmed to the first instance programmed cell according to one second code check, In first code check be higher than second code check,

Wherein the memorizer control circuit unit according to second code check by the data with corresponding to the data the check code The operation for being programmed to the first instance programmed cell includes：

When the data length of the data is no more than the data length of N number of basic management unit, according to second code check by the number It is programmed to the first instance programmed cell according to the check code corresponding to the data；And

It, will according to second code check when the data length of the data is more than the data length of N number of basic management unit The data of one first part and the check code of a first part are programmed to the first instance programmed cell and by one the The data of two parts are programmed to the second instance journey in those entity program units with the check code of a second part Sequence unit.

10. memory storage apparatus according to claim 9, which is characterized in that the memorizer control circuit unit judges The first instance erased cell belongs to the first kind entity erased cell or the operation of the second class entity erased cell includes：

Judge whether a bit error rate assessed value of the first instance erased cell meets a Sharp criteria；

If the bit error rate assessed value of the first instance erased cell does not meet the Sharp criteria, judge that the first instance is smeared Except unit belongs to the first kind entity erased cell；And

If the bit error rate assessed value of the first instance erased cell meets the Sharp criteria, judge that the first instance is erased Unit belongs to the second class entity erased cell.

11. memory storage apparatus according to claim 10, which is characterized in that the memorizer control circuit unit is also used With according to the one of the first instance erased cell erase number information, one write-in number information, a reading times information, a mistake Bit number information, a wrong bitrate information, a data resting period information and a temperature information at least one or extremely Few combination, to determine the bit error rate assessed value of the first instance erased cell.

12. memory storage apparatus according to claim 9, which is characterized in that

The memorizer control circuit unit programs the data and the check code corresponding to the data according to first code check Operation to the first instance programmed cell includes：

The data are divided at least one first data segment and generate at least one first check code section, wherein it is each this at least 1 the One check code section corresponds at least one of one first data segment,

Wherein the memorizer control circuit unit according to second code check by the data with corresponding to the data the check code The operation for being programmed to the first instance programmed cell includes：

The data are divided at least one second data segment and generate at least one second check code section, wherein it is each this at least 1 the Two check code sections correspond at least one of one second data segment,

One data length of wherein each at least one first data segment is identical to a number of each at least one second data segment It is shorter than each at least one second check code section according to a data length of length, and each at least one first check code section One data length.

13. memory storage apparatus according to claim 9, which is characterized in that

The memorizer control circuit unit programs the data and the check code corresponding to the data according to first code check Operation to the first instance programmed cell includes：

The data are divided at least one first data segment and generate at least one first check code section, wherein it is each this at least 1 the One check code section corresponds at least one of one first data segment,

Wherein the memorizer control circuit unit according to second code check by the data with corresponding to the data the check code The operation for being programmed to the first instance programmed cell includes：

The data are divided at least one second data segment and generate at least one second check code section, wherein it is each this at least 1 the Two check code sections correspond at least one of one second data segment,

One data length of wherein each at least one first data segment is longer than a data of each at least one second data segment Length, and a data length of each at least one first check code section is identical to each at least one second check code section One data length.

14. memory storage apparatus according to claim 9, which is characterized in that the memorizer control circuit unit foundation The data are programmed to the operation of the first instance programmed cell by second code check with the check code corresponding to the data Including：

Judge the data the data length whether be more than N number of basic management unit the data length, wherein N is just whole Number, and a data length of N+1 basic management unit is equal to an amount of capacity of the first instance programmed cell.

15. memory storage apparatus according to claim 14, which is characterized in that the second instance programmed cell belongs to One second that the second class entity erased cell is also belonged in the first instance erased cell or those entity erased cells is real Body erased cell.

16. memory storage apparatus according to claim 14, which is characterized in that a number of the data of the first part Meet the data length of N number of basic management unit according to length,

The memorizer control circuit unit will be also being at least programmed to the first instance programmed cell by one first inactive bit In full part write with the check code for filling up the not data by the first part and the first part,

The memorizer control circuit unit will be also being at least programmed to the second instance programmed cell by one second inactive bit In full part write with the check code for filling up the not data by the second part and the second part.

17. a kind of memorizer control circuit unit, which is characterized in that for controlling a type nonvolatile mould Block, the wherein reproducible nonvolatile memorizer module include multiple entity erased cells, each of entity erased cell Including multiple entity program units, and the memorizer control circuit unit includes：

One host interface, to be electrically connected to a host system；

One memory interface, to be electrically connected to the reproducible nonvolatile memorizer module；

One error checking and correcting circuit；And

One memory management circuitry is electrically connected to the host interface, the memory interface and the error checking and correcting circuit,

To receive a write instruction, one data are written at most the wherein memory management circuitry for wherein write instruction instruction At least one in a logic unit, wherein in those logic units this at least one map to those entity journeys A first instance programmed cell in sequence unit, and the first instance programmed cell belongs to those entity erased cells In a first instance erased cell,

The memorizer control circuit unit is also judging that the first instance erased cell belongs to a first kind entity erased cell Or one second class entity erased cell, wherein one first bit error rate of the first kind entity erased cell are less than second class One second bit error rate of entity erased cell,

When the first instance erased cell belongs to the first kind entity erased cell, the memory management circuitry is also sending The instruction of one first command serial, wherein first command serial is according to one first code check by the data and corresponding to the one of the data Check code is programmed to the first instance programmed cell,

When the first instance erased cell belongs to the second class entity erased cell, the memory management circuitry is also sending The instruction of one second command serial, wherein second command serial by the data and corresponds to being somebody's turn to do for the data according to one second code check Check code is programmed to the first instance programmed cell, and wherein first code check is higher than second code check,

The operation that the memory management circuitry sends second command serial includes：

When the data length of the data is no more than the data length of N number of basic management unit, second command serial is sent, In second command serial instruction according to second code check and only the data are programmed to the check code for corresponding to the data The first instance programmed cell,

When the data length of the data is more than the data length of N number of basic management unit, second strings of commands is sent The instruction of row, wherein second command serial is according to second code check by the school of the data of a first part and a first part It tests code and is programmed to the first instance programmed cell and by the check code of the data of a second part and a second part The second instance programmed cell being programmed in those entity program units.

18. memorizer control circuit unit according to claim 17, which is characterized in that the memory management circuitry judges The first instance erased cell belongs to the first kind entity erased cell or the operation of the second class entity erased cell includes：

Judge whether a bit error rate assessed value of the first instance erased cell meets a Sharp criteria；

If the bit error rate assessed value of the first instance erased cell does not meet the Sharp criteria, judge that the first instance is smeared Except unit belongs to the first kind entity erased cell；And

If the bit error rate assessed value of the first instance erased cell meets the Sharp criteria, judge that the first instance is erased Unit belongs to the second class entity erased cell.

19. memorizer control circuit unit according to claim 18, which is characterized in that the memory management circuitry is also used With according to the one of the first instance erased cell erase number information, one write-in number information, a reading times information, a mistake Bit number information, a wrong bitrate information, a data resting period information and a temperature information at least one or extremely Few combination, to determine the bit error rate assessed value of the first instance erased cell.

20. memorizer control circuit unit according to claim 17, which is characterized in that

The operation that the memory management circuitry sends first command serial further includes：

The data are divided at least one first data segment and control the error checking and generate at least one first school with correcting circuit Code section is tested, wherein each at least one first check code section corresponds at least one of one first data segment,

The operation that wherein memory management circuitry sends second command serial further includes：

The data are divided at least one second data segment and control the error checking and generate at least one second school with correcting circuit Code section is tested, wherein each at least one second check code section corresponds at least one of one second data segment,

One data length of wherein each at least one first data segment is identical to a number of each at least one second data segment It is shorter than each at least one second check code section according to a data length of length, and each at least one first check code section One data length.

21. memorizer control circuit unit according to claim 17, which is characterized in that

The operation that the memory management circuitry sends first command serial further includes：

The data are divided at least one first data segment and control the error checking and generate at least one first school with correcting circuit Code section is tested, wherein each at least one first check code section corresponds at least one of one first data segment,

The operation that wherein memory management circuitry sends second command serial further includes：

The data are divided at least one second data segment and control the error checking and generate at least one second school with correcting circuit Code section is tested, wherein each at least one second check code section corresponds at least one of one second data segment,

One data length of wherein each at least one first data segment is longer than a data of each at least one second data segment Length, and a data length of each at least one first check code section is identical to each at least one second check code section One data length.

22. memorizer control circuit unit according to claim 17, which is characterized in that the memory management circuitry is sent The operation of second command serial includes：

Judge the data the data length whether be more than N number of basic management unit the data length, wherein N is just whole Number, and a data length of N+1 basic management unit is equal to an amount of capacity of the first instance programmed cell.

23. memorizer control circuit unit according to claim 22, which is characterized in that the second instance programmed cell Belong to and also belongs to the one of the second class entity erased cell in the first instance erased cell or those entity erased cells Two entity erased cells.

24. memorizer control circuit unit according to claim 22, which is characterized in that the data of the first part One data length meets the data length of N number of basic management unit,

Second command serial also indicate at least one first inactive bit need to be programmed in the first instance programmed cell with It fills up not data by the first part and the check code of the first part writes full part, and at least one second nothing Effect is programmed in the second instance programmed cell than special procuring to fill up not data by the second part and this second The check code divided writes full part.