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CN104979303A - High-density integrated circuit package structure - Google Patents

High-density integrated circuit package structure Download PDF

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Publication number
CN104979303A
CN104979303A CN201510399162.1A CN201510399162A CN104979303A CN 104979303 A CN104979303 A CN 104979303A CN 201510399162 A CN201510399162 A CN 201510399162A CN 104979303 A CN104979303 A CN 104979303A
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lead frame
integrated circuit
plastic package
packaging structure
length
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CN104979303B (en
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刘兴波
周维
宋波
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CHINA CHIPPACKING TECHNOLOGY Co Ltd
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CHINA CHIPPACKING TECHNOLOGY Co Ltd
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    • H10W72/0198
    • H10W74/00

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Abstract

本发明公开了一种高密度集成电路封装结构,包括由引线框基岛、内引脚线和外引脚构成的金属引线框架,引线框基岛上固定有芯片,芯片和内引脚线之间设有微连接线,所述的引线框架、芯片和微连接线密封在长方体的塑封体内,所述塑封体的长度A1满足5.13mm≤A1≤5.23mm,塑封体的宽度A2满足5.18mm≤A2≤5.38mm,塑封体的厚度A3满足1.70mm≤A3≤1.90mm;本发明的封装结构能够用于对高频、高带宽、低噪声、高导热、高导电性能有特殊需求的中小规模集成电路,克服了现有技术中的封装结构电路集成度低、封装成本高、性能低的缺点。

The invention discloses a high-density integrated circuit packaging structure, which comprises a metal lead frame composed of a lead frame base island, inner lead wires and outer leads, a chip is fixed on the lead frame base island, and the chip and the inner lead wire There is a micro-connection line between them, and the lead frame, chip and micro-connection line are sealed in a cuboid plastic package, the length A1 of the plastic package satisfies 5.13mm≤A1≤5.23mm, and the width A2 of the plastic package satisfies 5.18mm≤ A2≤5.38mm, the thickness A3 of the plastic package satisfies 1.70mm≤A3≤1.90mm; the packaging structure of the present invention can be used for small and medium scale integration with special requirements for high frequency, high bandwidth, low noise, high thermal conductivity, and high electrical conductivity The circuit overcomes the disadvantages of low circuit integration, high packaging cost and low performance of the packaging structure in the prior art.

Description

一种高密度集成电路封装结构A high-density integrated circuit packaging structure

技术领域technical field

本发明属于集成电路封装技术领域,特别涉及一种高密度集成电路封装结构。The invention belongs to the technical field of integrated circuit packaging, in particular to a high-density integrated circuit packaging structure.

背景技术Background technique

集成电路封装不仅起到集成电路芯片内键合点与外部进行电气连接的作用,也为集成电路芯片提供了一个稳定可靠的工作环境,对集成电路芯片起到机械或环境保护的作用,从而使集成电路芯片能够发挥正常的功能,并保证其具有高稳定性和可靠性。总之,集成电路封装质量的好坏,对集成电路整体性能的影响很大。因此,封装应具有较强的机械性能、良好的电气性能、散热性能和化学稳定性。Integrated circuit packaging not only plays the role of electrical connection between the bonding points in the integrated circuit chip and the outside, but also provides a stable and reliable working environment for the integrated circuit chip, and plays a role in mechanical or environmental protection for the integrated circuit chip, so that the integration The circuit chip can perform normal functions and guarantee its high stability and reliability. In short, the quality of integrated circuit packaging has a great influence on the overall performance of integrated circuits. Therefore, the package should have strong mechanical properties, good electrical properties, heat dissipation performance and chemical stability.

虽然IC的物理结构、应用领域、I/O数量差异很大,但是IC封装的作用和功能却差别不大,封装的目的也相当的一致。作为“芯片的保护者”,封装起到了好几个作用,归纳起来主要有以下两个:Although the physical structure, application field, and I/O quantity of IC vary greatly, the role and function of IC packaging are not much different, and the purpose of packaging is quite consistent. As the "protector of the chip", packaging plays several roles, which can be summarized as follows:

(1)保护芯片,使其免受物理损伤;(1) Protect the chip from physical damage;

(2)重新分布I/O,获得更易于装配处理的引脚节距。封装还有其他一些次要的作用,比如提供一种更易于标准化的结构,为芯片提供散热通路,避免使芯片产生α粒子造成的软错误,以及提供一种更便于测试和老化试验的结构。封装还能用于多个IC的互连。(2) Redistribute the I/O to obtain a pin pitch that is easier to assemble and handle. Packaging also has other secondary functions, such as providing a structure that is easier to standardize, providing a heat dissipation path for the chip, avoiding soft errors caused by alpha particles on the chip, and providing a structure that is easier to test and burn-in. The package can also be used for the interconnection of multiple ICs.

随着微电子机械系统(MEMS)器件和片上实验室(lab-on-chip)器件的不断发展,封装起到了更多的作用:如限制芯片与外界的接触、满足压差的要求以及满足化学和大气环境的要求。最近几年人们对IC封装的重要性和不断增加的功能的看法发生了很大的转变,IC封装已经成为了和IC本身一样重要的一个领域,这是因为在很多情况下,IC的性能受到IC封装的制约。因此,人们越来越注重发展IC封装技术以应对新的挑战。With the continuous development of microelectromechanical systems (MEMS) devices and lab-on-chip (lab-on-chip) devices, packaging plays more roles: such as limiting the contact between the chip and the outside world, meeting the requirements of differential pressure, and meeting the chemical requirements. and atmospheric environment requirements. In recent years, people's perception of the importance and increasing functions of IC packaging has undergone a great change. IC packaging has become an area as important as IC itself. This is because in many cases, the performance of IC is affected by IC packaging constraints. Therefore, people pay more and more attention to the development of IC packaging technology to meet new challenges.

随着人们对智能设备功能要求的不断增加,特别是智能家电的兴起,产品需要更多的存储器,以208mil SOP8为封装载体的Flash Memory(闪存)的需求量急剧上升,以前这块芯片封装市场被韩国、中国台湾的企业所垄断,随着国内设计公司的兴起,技术能力不提高,目前国内已经撑握该芯片设计技术,但封装技术方面韩国、台湾地区的封装厂技术比较成熟,大陆封装厂正在追赶中。With the continuous increase of people's functional requirements for smart devices, especially the rise of smart home appliances, products need more memory. The demand for Flash Memory (flash memory) with 208mil SOP8 as the packaging carrier has risen sharply. In the past, this chip packaging market It is monopolized by companies in South Korea and Taiwan. With the rise of domestic design companies, the technical capabilities have not improved. At present, the chip design technology has been supported in China, but the packaging technology in South Korea and Taiwan is relatively mature. Plants are catching up.

目前,国内封装厂还很少有这种208mil宽体SOP8封装技术,即使有也是技术不够完善,可靠性比较低。而台湾企业在封装代工方面积累了多年的经验,在208mil宽体SOP8封装技术上比较成熟和完善,在行业内处于垄断地位。因此开发此项电路封装结构及封装技术极为必要。At present, domestic packaging factories rarely have this kind of 208mil wide-body SOP8 packaging technology, and even if they do, the technology is not perfect and the reliability is relatively low. Taiwanese companies have accumulated many years of experience in packaging foundry, and they are relatively mature and perfect in 208mil wide-body SOP8 packaging technology, and they are in a monopoly position in the industry. Therefore, it is extremely necessary to develop this circuit packaging structure and packaging technology.

发明内容Contents of the invention

本发明的目的是针对上述现有技术的不足,提供一种高密度集成电路封装结构,以增加封装体内的电路积集度、降低封装成本以及提高集成电路封装的可靠性。The object of the present invention is to provide a high-density integrated circuit packaging structure to address the above-mentioned deficiencies in the prior art, so as to increase the integration of circuits in the package, reduce packaging costs and improve the reliability of integrated circuit packaging.

本发明解决其技术问题所采用的技术方案是:一种高密度集成电路封装结构,包括由引线框基岛、内引脚线和外引脚构成的金属引线框架,引线框基岛上固定有芯片,芯片和内引脚线之间设有微连接线,所述的引线框架、芯片和微连接线密封在长方体的塑封体内,所述塑封体的长度A1满足5.13mm≤A1≤5.23mm,塑封体的宽度A2满足5.18mm≤A2≤5.38mm,塑封体的厚度A3满足1.70mm≤A3≤1.90mm。The technical solution adopted by the present invention to solve the technical problem is: a high-density integrated circuit packaging structure, including a metal lead frame composed of a lead frame base island, inner lead wires and outer leads, and a metal lead frame is fixed on the lead frame base island. The chip has a micro-connection line between the chip and the inner lead wire, and the lead frame, the chip and the micro-connection line are sealed in a rectangular parallelepiped plastic package, and the length A1 of the plastic package satisfies 5.13mm≤A1≤5.23mm, The width A2 of the plastic package satisfies 5.18mm≤A2≤5.38mm, and the thickness A3 of the plastic package meets 1.70mm≤A3≤1.90mm.

所述的一种高密度集成电路封装结构,其外引脚的跨度B1满足7.70mm≤B1≤8.10mm,外引脚的间距B2满足1.250mm≤B2≤2.540mm,外引脚的长度B3满足B3=(B1-A2)/2,外引脚的脚掌长度A6满足0.60mm≤A6≤0.70mm,外引脚的宽度B4满足0.38mm≤B4≤0.48mm。In the high-density integrated circuit packaging structure, the span B1 of the outer pins satisfies 7.70mm≤B1≤8.10mm, the spacing B2 of the outer pins satisfies 1.250mm≤B2≤2.540mm, and the length B3 of the outer pins satisfies B3=(B1-A2)/2, the sole length A6 of the outer pin satisfies 0.60mm≤A6≤0.70mm, and the width B4 of the outer pin satisfies 0.38mm≤B4≤0.48mm.

所述的一种高密度集成电路封装结构,其塑封体的宽度A2为5.28mm,塑封体的厚度A3为1.80mm,所述外引脚的个数B满足6≤B≤40的整数,外引脚的跨度B1为7.90mm,外引脚的间距B2为1.27mm,外引脚的长度B3为1.31mm,外引脚的脚掌长度A6为0.65mm,外引脚的宽度B4为0.415mm,塑封体的长度A1与外引脚的个数B之间满足A1=5.23+(B-8)×1.8/2mm。In the high-density integrated circuit packaging structure described above, the width A2 of the plastic package is 5.28mm, the thickness A3 of the plastic package is 1.80mm, and the number B of the outer pins satisfies an integer of 6≤B≤40, and the outer The span B1 of the pins is 7.90mm, the spacing B2 of the outer pins is 1.27mm, the length B3 of the outer pins is 1.31mm, the length A6 of the soles of the outer pins is 0.65mm, and the width B4 of the outer pins is 0.415mm. The length A1 of the plastic package and the number B of the outer pins satisfy A1=5.23+(B-8)×1.8/2mm.

所述的一种高密度集成电路封装结构,其外引脚的个数B为八个,塑封体的长度A1为5.23mm。In the high-density integrated circuit packaging structure described above, the number B of external pins is eight, and the length A1 of the plastic package is 5.23mm.

所述的一种高密度集成电路封装结构,其引线框基岛背面开设有呈阵列分布的多个锥形的凹坑。In the high-density integrated circuit packaging structure, the back of the base island of the lead frame is provided with a plurality of conical pits arranged in an array.

所述的一种高密度集成电路封装结构,其引线框基岛内开有八个长方形孔。Said high-density integrated circuit packaging structure has eight rectangular holes in the base island of the lead frame.

所述的一种高密度集成电路封装结构,其内引脚线为铜线、铜合金线、铁线、铁合金线、铝线或铝合金线,内引脚线上还设有厚度为17-76um的银合金镀层,所述的银合金由质量百分数为1.8-2.5%的Cu、1.2-1.5%的Ge、1.5-2.5%的Sn、0.8-1.2%的In和余量的Ag组成。Said a kind of high-density integrated circuit packaging structure, its inner lead wire is copper wire, copper alloy wire, iron wire, iron alloy wire, aluminum wire or aluminum alloy wire, and the inner lead wire is also provided with a thickness of 17- 76um silver alloy coating, the silver alloy is composed of 1.8-2.5% of Cu, 1.2-1.5% of Ge, 1.5-2.5% of Sn, 0.8-1.2% of In and the balance of Ag.

所述的一种高密度集成电路封装结构,其引线框基岛由铜、铜合金、铁、铁合金、铝或铝合金制成,引线框基岛的外部边缘表面镀有一圈厚度为17-76nm的氧化层,所述的氧化层的通过溅射沉积,该氧化层由质量百分数为45-50%的氧化铟、25-30%的氧化锡、8-10%的氧化锗和余量的氧化锌组成。The high-density integrated circuit packaging structure, the base island of the lead frame is made of copper, copper alloy, iron, iron alloy, aluminum or aluminum alloy, and the outer edge surface of the base island of the lead frame is plated with a ring thickness of 17-76nm The oxide layer is deposited by sputtering, and the oxide layer is composed of 45-50% indium oxide, 25-30% tin oxide, 8-10% germanium oxide and the balance of oxide Zinc composition.

所述的一种高密度集成电路封装结构,其引线框基岛到内引脚线顶端的距离为0.203mm,引线框基岛的下沉距离为0.203mm,内引脚线的长度为0.659mm,所述的塑封体所使用的封装材料为环保树脂塑封料。Said a kind of high-density integrated circuit packaging structure, the distance from the base island of the lead frame to the top of the inner lead line is 0.203mm, the sinking distance of the base island of the lead frame is 0.203mm, and the length of the inner lead line is 0.659mm , the packaging material used in the plastic packaging body is an environmentally friendly resin molding compound.

所述的一种高密度集成电路封装结构,其引线框架尺寸为长300±0.100mm、宽100mm和厚0.203mm,引线框架上设置有多个安装单元,所述的安装单元沿宽度方向列成11排,沿长度方向排成36列,所述的引线框架中间设置有多个工艺孔,所述的工艺孔包括长椭圆孔和方形孔。The high-density integrated circuit packaging structure has a lead frame size of 300±0.100 mm in length, 100 mm in width and 0.203 mm in thickness, and a plurality of installation units are arranged on the lead frame, and the installation units are arranged along the width direction 11 rows, arranged in 36 rows along the length direction, a plurality of process holes are arranged in the middle of the lead frame, and the process holes include oblong holes and square holes.

本发明的有益效果是:The beneficial effects of the present invention are:

1、通过对塑封体长、宽、高的尺寸设计,使得本封装集成电路产品能够用于对高频、高带宽、低噪声、高导热、高导电性能有特殊需求(如闪存芯片)的大规模集成电路,克服了现有技术中的封装结构电路积集度低、封装成本高、性能较低的缺点。1. Through the size design of the length, width and height of the plastic package, this packaged integrated circuit product can be used for large devices with special requirements for high frequency, high bandwidth, low noise, high thermal conductivity, and high electrical conductivity (such as flash memory chips). The scale integrated circuit overcomes the disadvantages of low circuit integration, high packaging cost and low performance of the packaging structure in the prior art.

2、通过对引线框基岛到内引脚线间距的设计,使得集成电路产品的电性能明显改善,生产效率、生产合格率、成本等综合效果较好;引线框基岛背面的凹坑和长方形孔能够提高基岛密封塑料的结合强度,避免分层,提高了封装的可靠性。2. Through the design of the distance from the base island of the lead frame to the inner pin line, the electrical performance of the integrated circuit product is significantly improved, and the comprehensive effects of production efficiency, production pass rate, and cost are better; the pits on the back of the base island of the lead frame and The rectangular hole can improve the bonding strength of the sealing plastic of the base island, avoid delamination, and improve the reliability of the package.

3、本发明所公布的引线框架,每条上的安装单元数量增加了106.25%,安装单元面积单只减少21.65%,引线框架的利用率≥71.4%,极大的节约了材料;塑封生产效率高达≥80000颗/小时,增大生产效率。3. In the lead frame disclosed by the present invention, the number of installation units on each piece increases by 106.25%, the area of each installation unit decreases by 21.65%, and the utilization rate of the lead frame is ≥ 71.4%, which greatly saves materials; plastic packaging production efficiency Up to ≥80,000 pieces/hour, increasing production efficiency.

4、本发明所采用的设备为自动设备,塑封时每两片框架组成一组,塑封料从中间溢料填充,最大化的节约了塑封料,塑封料利用率≥70.0%,增大了塑封料的利用率;4. The equipment used in the present invention is an automatic device. During plastic sealing, every two frames form a group, and the plastic sealing material is filled from the overflow in the middle, which saves the plastic sealing material to the greatest extent, and the utilization rate of the plastic sealing material is ≥ 70.0%, which increases the plastic sealing material utilization;

5、本发明使用的切筋成型技术使切筋成型生产效率达到≥112000颗/小时,增大生产效率;5. The rib cutting and forming technology used in the present invention makes the production efficiency of rib cutting and forming reach ≥ 112,000 pieces per hour, increasing the production efficiency;

6、本发明塑封后引线框架的翘曲度(warp)在10mm以下,增强了产品的可靠性;潮湿度敏感等级(MSL)3级以上;封装体热胀冷缩的耐久性(TCT)500次;高温加速老化试验(HAST)168小时;高温使用寿命测试(HTOL)1000小时。6. The warp (warp) of the lead frame after plastic sealing of the present invention is below 10 mm, which enhances the reliability of the product; the humidity sensitivity level (MSL) is above level 3; the durability of the thermal expansion and contraction of the package body (TCT) is 500 times; high temperature accelerated aging test (HAST) 168 hours; high temperature service life test (HTOL) 1000 hours.

附图说明Description of drawings

图1为本发明的结构示意图;Fig. 1 is a structural representation of the present invention;

图2为本发明引线框基岛的结构示意图;Fig. 2 is the structural representation of lead frame base island of the present invention;

图3为本发明引线框架正面结构的示意图;Fig. 3 is the schematic diagram of the front structure of the lead frame of the present invention;

图4为本发明引线框架塑封的结构示意图。Fig. 4 is a schematic structural view of the plastic package of the lead frame of the present invention.

其中各标记名称为:1—外引脚、2—塑封体、3—内引脚线、4—凹坑、5—引线框基岛、6—长方形孔、7—引线框架、8—工艺孔、9—溢胶槽。The names of the marks are: 1—outer pin, 2—plastic package, 3—inner lead line, 4—pit, 5—lead frame base island, 6—rectangular hole, 7—lead frame, 8—process hole , 9—overflow glue tank.

具体实施方式Detailed ways

下面结合附图对本发明作进一步详细说明。The present invention will be described in further detail below in conjunction with the accompanying drawings.

如图1所示,是本发明一种高密度集成电路封装结构的示意图,包括外引脚1和塑封体2,塑封体2的长度A1满足关系5.13mm≤A1≤5.23mm,塑封体2的宽度A2满足关系5.18mm≤A2≤5.38mm,塑封体2的厚度A3满足关系1.70mm≤A3≤1.90mm,外引脚1的跨度B1满足3.123mm≤B1≤5.123mm,外引脚1的跨度B1满足7.70mm≤B1≤8.10mm,外引脚1的间距B2满足1.250mm≤B2≤2.540mm,外引脚1的长度B3满足B3=(B1-A2)/2,即1.26mm≤B3≤1.36mm,外引脚1脚掌A6满足0.60mm≤A6≤0.70mm,外引脚1的宽度B4满足0.38mm≤B4≤0.48mm;通过对以上尺寸的设计,使得本封装集成电路产品能够用于对高频、高带宽、低噪声、高导热、高导电性能有特殊需求(如闪存芯片)的大规模集成电路,克服了现有技术中的封装结构电路积集度低、封装成本高、性能较低的缺点。As shown in Figure 1, it is a schematic diagram of a high-density integrated circuit packaging structure of the present invention, including an outer pin 1 and a plastic package body 2, the length A1 of the plastic package body 2 satisfies the relationship 5.13mm≤A1≤5.23mm, and the length A1 of the plastic package body 2 The width A2 satisfies the relationship 5.18mm≤A2≤5.38mm, the thickness A3 of the plastic package 2 satisfies the relationship 1.70mm≤A3≤1.90mm, the span B1 of the outer pin 1 satisfies 3.123mm≤B1≤5.123mm, and the span of the outer pin 1 B1 satisfies 7.70mm≤B1≤8.10mm, the spacing B2 of outer pin 1 satisfies 1.250mm≤B2≤2.540mm, and the length B3 of outer pin 1 satisfies B3=(B1-A2)/2, that is, 1.26mm≤B3≤ 1.36mm, A6 of the outer pin 1 satisfies 0.60mm≤A6≤0.70mm, and the width B4 of the outer pin 1 meets 0.38mm≤B4≤0.48mm; through the design of the above dimensions, this packaged integrated circuit product can be used in Large-scale integrated circuits that have special requirements for high frequency, high bandwidth, low noise, high thermal conductivity, and high electrical conductivity (such as flash memory chips), overcome the low integration of packaging structures, high packaging costs, and high performance in the prior art. Lower downside.

进一步,所述塑封体2的宽度A2为5.28mm,塑封体2的厚度A3为1.80mm,所述外引脚1的个数B满足6≤B≤40的整数,外引脚1的跨度B1为7.90mm,外引脚1的间距B2为1.27mm,外引脚1的长度B3为1.31mm,外引脚1的脚掌长度A6为0.65mm,外引脚1的宽度B4为0.415mm,塑封体2的长度A1与外引脚1的个数B之间满足A1=5.23+(B-8)×1.8/2mm,外引脚1的个数B为八个,塑封体2的长度A1为5.23mm。Further, the width A2 of the plastic package 2 is 5.28mm, the thickness A3 of the plastic package 2 is 1.80mm, the number B of the outer pins 1 satisfies an integer of 6≤B≤40, and the span B1 of the outer pins 1 is 7.90mm, the spacing B2 of the outer pin 1 is 1.27mm, the length B3 of the outer pin 1 is 1.31mm, the length A6 of the sole of the outer pin 1 is 0.65mm, and the width B4 of the outer pin 1 is 0.415mm. The length A1 of the body 2 and the number B of the outer pins 1 satisfy A1=5.23+(B-8)×1.8/2mm, the number B of the outer pins 1 is eight, and the length A1 of the plastic package body 2 is 5.23mm.

如图2所示是本发明引线框基岛5的结构示意图,引线框基岛5上固定有芯片,芯片和内引脚线3之间设有微连接线,所述的引线框架7、芯片和微连接线密封在长方体的塑封体2内,塑封体2所使用的封装材料为环保树脂塑封料,引线框基岛5到内引脚线3间距为0.203mm时,电性能明显改善,生产效率、生产合格率、成本等综合效果较好;引线框基岛5背面开设有呈阵列分布的多个锥形结构的凹坑4,引线框基岛5内开有八个长方形孔6,凹坑4和长方形孔6能够提高基岛密封塑料的结合强度,避免分层,提高了封装的可靠性。As shown in Figure 2 is the structural representation of lead frame base island 5 of the present invention, chip is fixed on the lead frame base island 5, is provided with micro connecting line between chip and inner lead line 3, described lead frame 7, chip and the micro-connecting wires are sealed in the rectangular parallelepiped plastic package 2. The packaging material used in the plastic package 2 is an environmentally friendly resin molding compound. When the distance between the base island 5 of the lead frame and the inner lead line 3 is 0.203mm, the electrical performance is significantly improved, and the production The overall effect of efficiency, production pass rate, cost, etc. is better; the back of the lead frame base island 5 is provided with a plurality of conical pits 4 distributed in an array, and eight rectangular holes 6 are opened in the lead frame base island 5. The pit 4 and the rectangular hole 6 can improve the bonding strength of the sealing plastic of the base island, avoid delamination, and improve the reliability of the package.

进一步,所述的内引脚线3为铜线、铜合金线、铁线、铁合金线、铝线或铝合金线,内引脚线3上还设有厚度为17-76um的银合金镀层,其中银合金由质量百分数为1.8-2.5%的Cu、1.2-1.5%的Ge、1.5-2.5%的Sn、0.8-1.2%的In和余量的Ag组成;所述的引线框基岛5由铜、铜合金、铁、铁合金、铝或铝合金制成,引线框基岛5的外部边缘表面镀有一圈厚度为17-76nm的氧化层,其中氧化层的通过溅射沉积,该氧化层由质量百分数为45-50%的氧化铟、25-30%的氧化锡、8-10%的氧化锗和余量的氧化锌组成;引线框基岛5到内引脚线3顶端的距离为0.203mm,引线框基岛5的下沉距离为0.203mm,内引脚线3的长度为0.659mm。Further, the inner lead wire 3 is copper wire, copper alloy wire, iron wire, iron alloy wire, aluminum wire or aluminum alloy wire, and the inner lead wire 3 is also provided with a silver alloy coating with a thickness of 17-76um. Wherein the silver alloy is composed of 1.8-2.5% Cu, 1.2-1.5% Ge, 1.5-2.5% Sn, 0.8-1.2% In and the rest of Ag in mass percent; the lead frame base island 5 is composed of Made of copper, copper alloy, iron, iron alloy, aluminum or aluminum alloy, the outer edge surface of the lead frame base island 5 is plated with an oxide layer with a thickness of 17-76nm, wherein the oxide layer is deposited by sputtering, and the oxide layer is formed by The mass percentage is composed of 45-50% indium oxide, 25-30% tin oxide, 8-10% germanium oxide and the rest of zinc oxide; the distance from the base island 5 of the lead frame to the top of the inner lead line 3 is 0.203 mm, the sinking distance of the base island 5 of the lead frame is 0.203 mm, and the length of the inner lead line 3 is 0.659 mm.

如图3所示为本发明引线框架正面结构的示意图,引线框架7的长度为300.00±0.100mm、宽度为100.00±0.050mm,厚0.203mm,引线框架7上设置有多个安装单元,所述的安装单元沿引线框架7的宽度方向列成11排,沿引线框架7的长度方向排成36列,排成11x36的IDF矩阵式结构,塑封时能封装39个芯片,从第一列安装单元开始,每相邻两列安装单元组成一个结构单元,并且上下相邻两列的结构单元相互交错在一起,结构单元左右之间的框架基板上设有多个长椭圆孔的和方形的工艺孔8,相邻安装单元之间的步距为6.436mm,相邻两个结构单元之间的步距为16.622mm。本发明的引线框架与目前行业内排的引线框架尺寸对比,如表1所示:As shown in Figure 3, it is a schematic diagram of the front structure of the lead frame of the present invention. The length of the lead frame 7 is 300.00 ± 0.100mm, the width is 100.00 ± 0.050mm, and the thickness is 0.203mm. The lead frame 7 is provided with a plurality of installation units. The installation units are arranged in 11 rows along the width direction of the lead frame 7, and arranged in 36 rows along the length direction of the lead frame 7, forming an IDF matrix structure of 11x36. When plastic packaging, 39 chips can be packaged, and the installation units from the first row At the beginning, every two adjacent columns of installation units form a structural unit, and the structural units of the upper and lower adjacent columns are interlaced with each other. The frame substrate between the left and right of the structural unit is provided with a number of oblong holes and square process holes. 8. The step distance between adjacent installation units is 6.436mm, and the step distance between two adjacent structural units is 16.622mm. The lead frame of the present invention is compared with the size of the lead frame in the current industry, as shown in Table 1:

表1本发明引线框架与现有6排引线框架尺寸对比Table 1 lead frame of the present invention compares with existing 6 rows of lead frame sizes

项目project 总长(mm)total length (mm) 总宽(mm)Overall width (mm) 只/条only/article 面积(mm2/只)Area (mm 2 /piece) 本设计引线框架This Design Lead Frame 300.00300.00 100.00100.00 396396 75.7675.76 现有6排引线框架Existing 6 row lead frame 238.00238.00 78.0078.00 192192 96.6996.69

从表1可以看出,与现有的6排208mil SOP8封装引线框结构相比,本设计所述的引线框架,每条上的安装单元数量增加了106.25%,安装单元面积单只减少21.65%,节约了原材料。It can be seen from Table 1 that compared with the existing 6-row 208mil SOP8 package lead frame structure, the number of mounting units on each lead frame in this design increases by 106.25%, and the area of each mounting unit only decreases by 21.65% , saving raw materials.

如图4所示为本发明引线框架塑封的结构示意图,塑封时每两片引线框架7的中间设有方形的溢胶槽9,本发明所采用的设备为自动设备,塑封时每两片框架组成一组,塑封料从中间溢料填充,最大化的节约了塑封料。As shown in Figure 4, it is a structural schematic diagram of the lead frame plastic packaging of the present invention. During plastic sealing, a square glue overflow groove 9 is provided in the middle of every two lead frames 7. The equipment used in the present invention is automatic equipment. When plastic sealing, every two frames To form a group, the plastic sealing compound is filled from the overflow in the middle, which saves the plastic sealing compound to the greatest extent.

本发明的引线框结构中,分布有11排引线框单元,这样每条引线框结构上的引线框单元共计396个,可装396只电路。以每模可产出8片封装引线框结构来计算,可封装电路数达到3168只。In the lead frame structure of the present invention, there are 11 rows of lead frame units distributed, so that there are 396 lead frame units on each lead frame structure in total, which can hold 396 circuits. Calculated on the basis that each mold can produce 8 pieces of packaged lead frame structure, the number of packages that can be packaged reaches 3168.

表2本发明引线框架与现有6排引线框架塑封生产效率对比Table 2 lead frame of the present invention and existing 6 rows of lead frame plastic packaging production efficiency contrast

项目project 只/条only/article 只/模Only/Model 本设计引线框架This Design Lead Frame 396396 31683168 现有6排引线框架Existing 6 row lead frame 192192 15361536

同时在塑封料的利用率方面,本发明也将显著提高,目前普通6排框架每模塑封料的用量为2598.4g/模,而本发明所使用的塑封方法为2923.2g/模,从而可得到如表3所示的塑封料利用率,采用本发明的方法,塑封料的利用率可以提高13.8%,因而技术效果明显。由于本发明所采用的塑封设备为自动化设备,每小时可塑封12模的框架,生产效率高达36950颗/小时以上。Simultaneously, the present invention will also significantly improve the utilization rate of the molding compound. At present, the amount of molding compound used for each molding of a common 6-row frame is 2598.4g/mold, while the plastic sealing method used in the present invention is 2923.2g/mold, thereby obtaining As shown in Table 3, the utilization rate of the molding compound can be increased by 13.8% by adopting the method of the present invention, thus the technical effect is obvious. Because the plastic sealing equipment adopted in the present invention is automatic equipment, it can plastic seal 12 frames per hour, and the production efficiency is as high as 36950 pieces per hour.

表3本发明引线框架与现有6排引线框架塑封生产效率对比Table 3 Comparison of lead frame of the present invention and existing 6 rows of lead frame plastic packaging production efficiency

项目project 只/模Only/Model 塑封料(g)/只Plastic compound (g)/piece 塑封料(g)/模具Plastic compound (g)/mold 利用率Utilization 本设计引线框架This Design Lead Frame 396396 4.24.2 2105.62105.6 78.9%78.9% 现有6排引线框架Existing 6 row lead frame 192192 4.24.2 1240.61240.6 65.1%65.1%

如图3可以看出本发明的框架结构为每两列一组,共11排,为提高生产率,适应大矩阵高密度生产方式,提供了一种切筋成型技术,在本发明的切筋方法中,每次同时冲切4列框架单元,这样每次冲切的引线框单元共计44个,以每每分钟可以冲切55次来计算,则每每分钟的冲切引线框单元数量为2420颗,而目前普通的6排引线框架,每次冲切24颗,每分钟冲切1320颗,因此在切筋效率上本发明可提高83.3%。As shown in Figure 3, it can be seen that the frame structure of the present invention is a group of every two rows, 11 rows in total, for improving productivity, adapting to the large matrix high-density production mode, a kind of rib cutting forming technology is provided, in the rib cutting method of the present invention Among them, 4 rows of frame units are punched at the same time at the same time, so that a total of 44 lead frame units are punched each time. Calculated by punching 55 times per minute, the number of punched lead frame units per minute is 2420. However, the current common 6-row lead frame punches 24 pieces each time, and punches 1320 pieces per minute, so the present invention can improve the rib cutting efficiency by 83.3%.

本发明与现有技术相比具有以下有益的技术效果:Compared with the prior art, the present invention has the following beneficial technical effects:

1.框架利用率≥71.4%,极大的节约了材料;1. The utilization rate of the frame is ≥71.4%, which greatly saves materials;

2.塑封料利用率≥70.0%,增大了塑封料的利用率;2. The utilization rate of plastic sealing compound is ≥70.0%, which increases the utilization rate of plastic sealing compound;

3.塑封生产效率高达≥80000颗/小时,增大生产效率;3. The production efficiency of plastic packaging is as high as ≥80000 pieces per hour, which increases the production efficiency;

4.切筋成型生产效率达到≥112000颗/小时,增大生产效率;4. The production efficiency of rib cutting and forming reaches ≥112,000 pieces per hour, increasing production efficiency;

5.塑封后引线框的翘曲度(warp)在10mm以下,增强了产品的可靠性;5. The warp of the lead frame after plastic sealing is less than 10mm, which enhances the reliability of the product;

6.潮湿度敏感等级(MSL)3级以上;6. Moisture sensitivity level (MSL) level 3 or above;

7.封装体热胀冷缩的耐久性(TCT)500次;7. The thermal expansion and contraction durability (TCT) of the package is 500 times;

8.高温加速老化试验(HAST)168小时;8. High temperature accelerated aging test (HAST) for 168 hours;

9.高温使用寿命测试(HTOL)1000小时9. High temperature service life test (HTOL) 1000 hours

上述实施例仅例示性说明本发明的原理及其功效,以及部分运用的实施例,对于本领域的普通技术人员来说,在不脱离本发明创造构思的前提下,还可以做出若干变形和改进,这些都属于本发明的保护范围。The above-mentioned embodiments only illustrate the principles and effects of the present invention, as well as the partially used embodiments. For those of ordinary skill in the art, without departing from the inventive concept of the present invention, some deformations and modifications can also be made. Improvements, these all belong to the protection scope of the present invention.

Claims (10)

1.一种高密度集成电路封装结构,其特征在于:包括由引线框基岛(5)、内引脚线(3)和外引脚(1)构成的金属引线框架(7),引线框基岛(5)上固定有芯片,芯片和内引脚线(3)之间设有微连接线,所述的引线框架(7)、芯片和微连接线密封在长方体的塑封体(2)内,所述塑封体(2)的长度A1满足5.13mm≤A1≤5.23mm,塑封体(2)的宽度A2满足5.18mm≤A2≤5.38mm,塑封体(2)的厚度A3满足1.70mm≤A3≤1.90mm。 1. A high-density integrated circuit packaging structure, characterized in that: it includes a metal lead frame (7) composed of a lead frame base island (5), an inner lead wire (3) and an outer lead (1), and the lead frame A chip is fixed on the base island (5), and a micro-connection line is provided between the chip and the inner lead wire (3), and the lead frame (7), the chip and the micro-connection line are sealed in a rectangular parallelepiped plastic package (2) Inside, the length A1 of the plastic package (2) satisfies 5.13mm≤A1≤5.23mm, the width A2 of the plastic package (2) meets 5.18mm≤A2≤5.38mm, and the thickness A3 of the plastic package (2) meets 1.70mm≤ A3≤1.90mm. 2.根据权利要求1所述的一种高密度集成电路封装结构,其特征在于,所述外引脚(1)的跨度B1满足7.70mm≤B1≤8.10mm,外引脚(1)的间距B2满足1.250mm≤B2≤2.540mm,外引脚(1)的长度B3满足B3=(B1-A2)/2,外引脚(1)的脚掌长度A6满足0.60mm≤A6≤0.70mm,外引脚(1)的宽度B4满足0.38mm≤B4≤0.48mm。 2. A high-density integrated circuit packaging structure according to claim 1, characterized in that the span B1 of the outer pins (1) satisfies 7.70mm≤B1≤8.10mm, and the distance between the outer pins (1) B2 satisfies 1.250mm≤B2≤2.540mm, the length B3 of the outer pin (1) satisfies B3=(B1-A2)/2, the sole length A6 of the outer pin (1) satisfies 0.60mm≤A6≤0.70mm, the outer pin (1) meets the The width B4 of the pin (1) satisfies 0.38mm≤B4≤0.48mm. 3.根据权利要求1或2所述的一种高密度集成电路封装结构,其特征在于,所述塑封体(2)的宽度A2为5.28mm,塑封体(2)的厚度A3为1.80mm,所述外引脚(1)的个数B满足6≤B≤40的整数,外引脚(1)的跨度B1为7.90mm,外引脚(1)的间距B2为1.27mm,外引脚(1)的长度B3为1.31mm,外引脚(1)的脚掌长度A6为0.65mm,外引脚(1)的宽度B4为0.415mm,塑封体(2)的长度A1与外引脚(1)的个数B之间满足A1=5.23+(B-8)×1.8/2mm。 3. A high-density integrated circuit packaging structure according to claim 1 or 2, characterized in that the width A2 of the plastic package (2) is 5.28mm, and the thickness A3 of the plastic package (2) is 1.80mm, The number B of the outer pins (1) satisfies an integer of 6≤B≤40, the span B1 of the outer pins (1) is 7.90 mm, the distance B2 of the outer pins (1) is 1.27 mm, and the outer pins (1) The length B3 of (1) is 1.31mm, the sole length A6 of the outer pin (1) is 0.65mm, the width B4 of the outer pin (1) is 0.415mm, and the length A1 of the plastic package (2) is the same as that of the outer pin ( 1) A1=5.23+(B-8)×1.8/2mm is satisfied between the number B. 4.根据权利要求3所述的一种高密度集成电路封装结构,其特征在于,所述的外引脚(1)的个数B为八个,塑封体(2)的长度A1为5.23mm。 4. A high-density integrated circuit packaging structure according to claim 3, characterized in that, the number B of the outer pins (1) is eight, and the length A1 of the plastic package (2) is 5.23mm . 5.根据权利要求1至4任一项所述的一种高密度集成电路封装结构,其特征在于,所述的引线框基岛(5)背面开设有呈阵列分布的多个锥形的凹坑(4)。 5. A high-density integrated circuit packaging structure according to any one of claims 1 to 4, characterized in that the back of the lead frame base island (5) is provided with a plurality of tapered recesses arranged in an array. Pit (4). 6.根据权利要求5所述的一种高密度集成电路封装结构,其特征在于,所述的引线框基岛(5)内开有八个长方形孔(6)。 6. A high-density integrated circuit packaging structure according to claim 5, characterized in that eight rectangular holes (6) are opened in the base island (5) of the lead frame. 7.根据权利要求1或2或4或6任一项所述的一种高密度集成电路封装结构,其特征在于,所述的内引脚线(3)为铜线、铜合金线、铁线、铁合金线、铝线或铝合金线,内引脚线(3)上还设有厚度为17-76um的银合金镀层,所述的银合金由质量百分数为1.8-2.5%的Cu、1.2-1.5%的Ge、1.5-2.5%的Sn、0.8-1.2%的In和余量的Ag组成。 7. A high-density integrated circuit packaging structure according to any one of claims 1 or 2 or 4 or 6, characterized in that, the inner lead wires (3) are copper wires, copper alloy wires, iron wire, iron alloy wire, aluminum wire or aluminum alloy wire, the inner pin wire (3) is also provided with a silver alloy coating with a thickness of 17-76um, and the silver alloy is composed of 1.8-2.5% by mass of Cu, 1.2 - Composition of 1.5% Ge, 1.5-2.5% Sn, 0.8-1.2% In and balance Ag. 8.根据权利要求7所述的一种高密度集成电路封装结构,其特征在于,所述的引线框基岛(5)由铜、铜合金、铁、铁合金、铝或铝合金制成,引线框基岛(5)的外部边缘表面镀有一圈厚度为17-76nm的氧化层,所述的氧化层的通过溅射沉积,该氧化层由质量百分数为45-50%的氧化铟、25-30%的氧化锡、8-10%的氧化锗和余量的氧化锌组成。 8. A high-density integrated circuit packaging structure according to claim 7, characterized in that, the lead frame base island (5) is made of copper, copper alloy, iron, iron alloy, aluminum or aluminum alloy, and the lead wire The outer edge surface of the frame base island (5) is coated with an oxide layer with a thickness of 17-76nm, the oxide layer is deposited by sputtering, and the oxide layer is composed of indium oxide with a mass percentage of 45-50%, 25- It consists of 30% tin oxide, 8-10% germanium oxide and the rest zinc oxide. 9.根据权利要求8所述的一种高密度集成电路封装结构,其特征在于,所述的引线框基岛(5)到内引脚线(3)顶端的距离为0.203mm,引线框基岛(5)的下沉距离为0.203mm,内引脚线(3)的长度为0.659mm,所述的塑封体(2)所使用的封装材料为环保树脂塑封料。 9. A high-density integrated circuit packaging structure according to claim 8, characterized in that the distance from the lead frame base island (5) to the top of the inner lead line (3) is 0.203 mm, and the lead frame base The sinking distance of the island (5) is 0.203 mm, the length of the inner lead line (3) is 0.659 mm, and the packaging material used for the plastic package (2) is an environmentally friendly resin plastic packaging compound. 10.根据权利要求1至8任意一项所述的一种高密度集成电路封装结构,其特征在于,所述的引线框架(7)尺寸为长300±0.100mm、宽100±0.050mm和厚0.203mm,引线框架(7)上设置有多个安装单元,所述的安装单元沿宽度方向列成11排,沿长度方向排成36列,所述的引线框架(7)中间设置有多个工艺孔(8),所述的工艺孔(8)包括长椭圆孔和方形孔。 10. A high-density integrated circuit packaging structure according to any one of claims 1 to 8, characterized in that the size of the lead frame (7) is 300±0.100mm in length, 100±0.050mm in width and 100±0.050mm in thickness 0.203mm, multiple installation units are arranged on the lead frame (7), the installation units are arranged in 11 rows along the width direction, and 36 rows along the length direction, and a plurality of installation units are arranged in the middle of the lead frame (7) The process hole (8), the process hole (8) includes oblong holes and square holes.
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CN108109977A (en) * 2018-02-12 2018-06-01 王孝裕 It is a kind of to manufacture ic chip package structure with ultrasonic copper wire

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