CN104979007A - Bit line multiplexer and bit line multiplexing system - Google Patents

Abstract

The invention relates to a bit line multiplexer and a bit line multiplexing system. The bit line multiplexer includes: a transistor group, a selection transistor, a third transistor and a fourth transistor. The transistor group comprises a first transistor and a second transistor which are connected in series, and a grid electrode of the first transistor and a grid electrode of the second transistor are connected and connected to a bit line. The selection transistor is connected with the transistor group, and a grid electrode of the selection transistor is connected with a bit selection line. The third transistor is connected to the transistor group. The fourth transistor is connected to the third transistor. By using the bit line multiplexer, the output voltage can be switched to be in a state when the potential of the bit line is higher than the set potential, so that the potential of the bit line with low noise can not influence the output voltage, and the immunity of noise interference is improved.

Description

Bit line multiplexer and bit line multiplexer system

technical field

The present invention relates to a bit line multiplexer and a bit line multiplexer system.

Background technique

Referring to FIG. 1 , it shows a schematic block diagram of a ROM system. The read-only memory (Read Only Memory) 11 is used to store data or programs, etc., which usually uses a row of decoders 12 and a column of decoders and multiplexers 13 to read data or programs. However, due to interference between adjacent bit lines, the read data may be incorrect.

Contents of the invention

The technical problem to be solved by the present invention is to provide a bit line multiplexer and a bit line multiplexer system to solve the problem of only The problem that the data read from the read memory is incorrect.

The present invention relates to a bit line multiplexer, including: a transistor group, a selection transistor, a third transistor and a fourth transistor. The transistor group includes a first transistor and a second transistor, the first transistor and the second transistor are connected in series, a gate of the first transistor is connected with a gate of the second transistor, and is connected to a Wire. The selection transistor is connected to the transistor group, and a gate of the selection transistor is connected to a bit selection line. The third transistor is connected to the transistor group. The fourth transistor is connected to the third transistor.

The present invention relates to a bit line multiplexing system, comprising: multiple switches and multiple bit line multiplexers. Each switch has a first end and a second end, and the first end of each switch is connected to a bit line. Each bit line multiplexer includes: a transistor group, a selection transistor, a third transistor and a fourth transistor. The transistor group includes a first transistor and a second transistor, the first transistor and the second transistor are connected in series, a gate of the first transistor is connected with a gate of the second transistor, and is connected to the first transistor. Two ends. The selection transistor is connected to the transistor group, and a gate of the selection transistor is connected to a bit selection line. The third transistor is connected to the transistor group. The fourth transistor is connected to the third transistor.

With the bit line multiplexer of the present invention, when the potential of the bit line is higher than the set potential, the output voltage will turn, so that the potential of the bit line with low noise will not affect the output voltage, so as to improve the immunity of noise interference.

Description of drawings

FIG. 1 shows a system block schematic diagram of a read-only memory;

2 shows a schematic circuit diagram of an embodiment of the bit line multiplexer of the present invention;

FIG. 3 shows a schematic diagram of the relationship between input and output of an embodiment of the bit line multiplexer in FIG. 2 of the present invention;

4 shows a schematic circuit diagram of an embodiment of the bit line multiplexer of the present invention;

FIG. 5 shows a schematic diagram of the relationship between input and output of an embodiment of the bit line multiplexer in FIG. 4 of the present invention;

FIG. 6 shows a schematic circuit diagram of the application of the bit line multiplexer in FIG. 2 of the present invention to a read-only memory;

7 shows a schematic circuit diagram of an embodiment of the bit line multiplexer of the present invention;

8 shows a schematic circuit diagram of an embodiment of the bit line multiplexer of the present invention; and

FIG. 9 shows a block diagram of an embodiment of the bit line multiplexing system of the present invention.

Explanation of main component symbols

11 ROM 12 row decoder

13 column decoder and multiplexer 20 bit line multiplexer

21 Transistor group 22 Select transistor

23 third transistor 24 fourth transistor

25 fifth transistor 30 bit line multiplexer

31 Transistor group 32 Select transistor

33 third transistor 34 fourth transistor

35 fifth transistor 50 bit line multiplexer

60-bit line multiplexer 41 memory cells

42 Node 43 Precharge Transistor

44 output latches 70 bit line multiplexing system

71 switch 72 bit line multiplexer

81 ROM 82 Output Latch

211 first transistor 212 second transistor

213 Gate of the first transistor 214 Source of the first transistor

215 Drain of the first transistor 216 Gate of the second transistor

217 Source of the second transistor 218 Drain of the second transistor

221 Select the gate of the transistor 222 Select the source of the transistor

223 Drain of select transistor 231 Gate of third transistor

232 Source of the third transistor 233 Drain of the third transistor

241 Gate of the fourth transistor 242 Source of the fourth transistor

243 Drain of the fourth transistor 251 Gate of the fifth transistor

252 Source of the fifth transistor 253 Drain of the fifth transistor

311 first transistor 312 second transistor

313 Gate of the first transistor 314 Source of the first transistor

315 Drain of the first transistor 316 Gate of the second transistor

317 Source of the second transistor 318 Drain of the second transistor

321 Select the gate of the transistor 322 Select the source of the transistor

323 Drain of select transistor 331 Gate of third transistor

332 Source of the third transistor 333 Drain of the third transistor

341 Gate of the fourth transistor 342 Source of the fourth transistor

343 Drain of the fourth transistor 351 Gate of the fifth transistor

352 Source of the fifth transistor 353 Drain of the fifth transistor

711 First end 712 Second end

Detailed ways

FIG. 2 shows a schematic circuit diagram of an embodiment of the bit line multiplexer of the present invention. The bit line multiplexer 20 of the present invention includes: a transistor group 21 , a selection transistor 22 , a third transistor 23 and a fourth transistor 24 . The transistor group 21 includes a first transistor 211 and a second transistor 212, the first transistor 211 and the second transistor 212 are connected in series, a gate 213 of the first transistor 211 and a gate of the second transistor 212 The pole 216 is connected and connected to a bit line (bit line, BL). The bit line BL can be one of the bit lines of the ROM. The selection transistor 22 is connected to the transistor group 21 , and a gate 221 of the selection transistor 22 is connected to a bit selection line (BL_sel). The third transistor 23 is connected to the transistor group 21 . The fourth transistor 24 is connected to the third transistor 23 .

In one embodiment, the first transistor 211, the second transistor 212, the selection transistor 22 and the third transistor 23 are N-type metal oxide semiconductor transistors (NMOS), and the fourth transistor 24 is a P-type metal oxide transistor. material semiconductor transistor (PMOS).

A source 214 of the first transistor 211 is connected to a drain 218 of the second transistor 212 . A source 222 of the selection transistor 22 is connected to a drain 215 of the first transistor 211 , and a drain 223 of the selection transistor 22 is grounded. A gate 231 of the third transistor 23 is connected to a source 217 of the second transistor 212 , and a drain 233 of the third transistor 23 is connected to the drain 218 of the second transistor 212 . A gate 241 of the fourth transistor 24 is grounded, a source 242 of the fourth transistor 24 is connected to a first potential V _S1 , a drain 243 of the fourth transistor 24 is connected to a drain of the third transistor 23 source 232 . The source 217 of the second transistor 212 is an output node.

FIG. 3 is a schematic diagram showing the relationship between input and output of an embodiment of the bit line multiplexer in FIG. 2 of the present invention. With reference to FIG. 2 and FIG. 3 , when the bit selection line (BL_sel) reaches a set potential, the selection transistor 22 is turned on. When the potential V _BL of the bit line BL reaches a first set potential V _{IN_MIN} , the first transistor 211 is turned on, but the second transistor 212 is still not turned on, and the output voltage (the second transistor 212 of the second transistor 212 The voltage of the source 217) V _OUT is still a high potential (V _DD ). When the potential V _BL of the bit line BL reaches a second set potential V _SPH , both the first transistor 211 and the second transistor 212 are turned on, and the output voltage V _OUT turns to a low potential (for example: 0 ).

Therefore, using the bit line multiplexer of the present invention, when the potential V _BL of the bit line BL is higher than the second set potential, the output voltage will transition, and the potential V _BL of the bit line BL is lower than the second set potential , the output voltage does not change. Therefore, the potential of the bit line causing the output voltage transition is increased to the second set potential, so that the potential of the low-noise bit line BL will not affect the output voltage, so as to improve immunity to noise interference. That is, adjacent bit lines do not interfere with each other, so as to improve the accuracy of reading data.

FIG. 4 shows a schematic circuit diagram of an embodiment of the bit line multiplexer of the present invention. The bit line multiplexer 30 of the present invention includes: a transistor group 31 , a selection transistor 32 , a third transistor 33 and a fourth transistor 34 . The transistor group 31 includes a first transistor 311 and a second transistor 312, the first transistor 311 and the second transistor 312 are connected in series, a gate 313 of the first transistor 311 and a gate of the second transistor 312 Pole 316 is connected and is connected to a bit line (BL). The selection transistor 32 is connected to the transistor group 31 , and a gate 321 of the selection transistor 32 is connected to a bit selection line (BL_sel). The third transistor 33 is connected to the transistor group 31 . The fourth transistor 34 is connected to the third transistor 33 .

In one embodiment, the first transistor 311, the second transistor 312, the selection transistor 32 and the third transistor 33 are P-type metal oxide semiconductor transistors (PMOS), and the fourth transistor 34 is a P-type metal oxide transistor. material semiconductor transistor (NMOS).

A drain 315 of the first transistor 311 is connected to a source 317 of the second transistor 312 . A drain 323 of the selection transistor 32 is connected to a source 314 of the first transistor 311 , and a source 322 of the selection transistor 32 is connected to a high potential (V _DD ). A gate 331 of the third transistor 33 is connected to a drain 318 of the second transistor 312 , and a source 332 of the third transistor 33 is connected to the source 317 of the second transistor 312 . A gate 341 of the fourth transistor 34 is connected to a second potential V _S2 , a source 342 of the fourth transistor 34 is connected to a drain 333 of the third transistor 33 , and a drain of the fourth transistor 34 Pole 343 is grounded. The drain 318 of the second transistor 312 is an output node.

FIG. 5 is a schematic diagram showing the relationship between input and output of an embodiment of the bit line multiplexer in FIG. 4 of the present invention. With reference to FIG. 4 and FIG. 5, when the potential V BL of the bit line _BL reaches a third set potential V _SPL , both the first transistor 311 and the second transistor 312 are turned on, and the output voltage (the second transistor The voltage of the drain 318 of 312) V _OUT transitions to a high potential (eg V _DD ).

Therefore, similarly, using the bit line multiplexer shown in FIG. 4 of the present invention, the output voltage will only turn when the potential of the bit line BL reaches the third set potential, which can also improve immunity to noise interference. That is, adjacent bit lines do not interfere with each other, so as to improve the accuracy of reading data.

Referring to FIG. 6 , it shows a schematic circuit diagram of applying the bit line multiplexer in FIG. 2 of the present invention to a read-only memory. The bit line BL of the bit line multiplexer 20 of FIG. 2 of the present invention is connected to a precharge transistor 43, and is connected to a storage unit 41 of the read-only memory through a node 42, and the node 42 indicates that the bit line BL is directly connected to The storage unit 41 or the storage unit 41 are open. The output of the bit line multiplexer 20 is also connected to an output latch (Output Latch) 44 to output the read data.

FIG. 7 shows a schematic circuit diagram of an embodiment of the bit line multiplexer of the present invention. Compared with the bit line multiplexer 20 of FIG. 2 , the same components in the bit line multiplexer 50 of FIG. 7 are given the same component numbers. The difference between the bit line multiplexer 50 in FIG. 7 of the present invention and the bit line multiplexer 20 in FIG. 2 is that the bit line multiplexer 50 of the present invention also includes a fifth transistor 25, which is an N-type metal oxide semiconductor transistor (NMOS), connecting the transistor group 21 and the selection transistor 22, a gate 251 of the fifth transistor 25 is connected to the source 217 of the second transistor 212, a source 252 of the fifth transistor 25 is connected to On the bit line BL, a drain 253 of the fifth transistor 25 is connected to the source 222 of the selection transistor 22 .

When the potential V _BL of the bit line BL is greater than the first set potential V _{IN_MIN} and lower than the second set potential V _SPH , the fifth transistor 25 is turned on, so the first transistor 211 is not turned on, so that Additional power consumption caused by the conduction of the first transistor 211 is avoided. Therefore, the bit line multiplexer 50 of the present invention can also reduce unnecessary power consumption.

FIG. 8 shows a schematic circuit diagram of an embodiment of the bit line multiplexer of the present invention. Compared with the bit line multiplexer 30 of FIG. 4 , the same components in the bit line multiplexer 60 of FIG. 8 are given the same component numbers. The difference between the bit line multiplexer 60 in FIG. 8 of the present invention and the bit line multiplexer 30 in FIG. 4 is that the bit line multiplexer 60 of the present invention also includes a fifth transistor 35, which is a P-type metal oxide semiconductor transistor (PMOS), connecting the transistor group 31 and the selection transistor 32, a gate 351 of the fifth transistor 35 is connected to the drain 318 of the second transistor 212, a drain 353 of the fifth transistor 35 is connected to On the bit line BL, a source 352 of the fifth transistor 35 is connected to the drain 323 of the selection transistor 32 . Likewise, the bit line multiplexer 60 of the present invention can also reduce unnecessary power consumption.

FIG. 9 shows a block diagram of an embodiment of the bit line multiplexing system of the present invention. The bit line multiplexing system 70 of the present invention can be applied to the ROM 81 . The bit line multiplexing system 70 of the present invention includes: a plurality of switches 71 and a plurality of bit line multiplexers 72 . Each switch 71 has a first terminal 711 and a second terminal 712, and the first terminal 711 of each switch 71 is connected to the bit line BL. Each bit line multiplexer 72 can be the bit line multiplexer shown in FIG. 2 , FIG. 4 , FIG. 7 or FIG. 8 , which will not be described here again. However, in the bit line multiplexer 72, the bit line BL contact originally in the bit line multiplexer of FIG. 2, FIG. 4, FIG. 7 or FIG. The line multiplexer 72 is connected to the bit line BL of the ROM 81 via the switch 71 .

The number of these switches 71 in the bit line multiplexing system 70 of the present invention corresponds to the number of bit lines of the read-only memory 81, but the number of bit line multiplexers 72 can be only 8, that is, 8 bit line multiplexers 72 These bit lines can be shared, and the data of the read-only memory 81 to be read is respectively controlled by the switch 71 . Likewise, the output latches 82 can also be shared. The number of these switches is greater than the number of these bit line multiplexers. Therefore, the bit line multiplexing system 70 of the present invention can reduce the number of bit line multiplexers and reduce the hardware cost.

However, the above-mentioned embodiments are only for illustrating the principles and effects of the present invention, rather than limiting the present invention. Therefore, those skilled in the art can modify and change the above embodiments without departing from the spirit of the present invention. The scope of rights of the present invention should be listed in the claims.

Claims (15)

1. A bit line multiplexer, characterized in that, comprising: A transistor group includes a first transistor and a second transistor, the first transistor is connected in series with the second transistor, a gate of the first transistor is connected with a gate of the second transistor, and is connected to a bit line; a selection transistor connected to the transistor group, a gate of the selection transistor connected to a selection line; a third transistor connected to the transistor group; and A fourth transistor connected to the third transistor. 2. The bit line multiplexer according to claim 1, wherein the first transistor, the second transistor, the selection transistor and the third transistor are N-type metal-oxide-semiconductor transistors, and the fourth transistor is a P type metal-oxide-semiconductor transistors. 3. The bit line multiplexer according to claim 2, wherein a source of the first transistor is connected to a drain of the second transistor, a source of the selection transistor is connected to a drain of the first transistor A drain, a gate of the third transistor is connected to a source of the second transistor, a drain of the third transistor is connected to the drain of the second transistor, a gate of the fourth transistor grounded, a drain of the fourth transistor is connected to a source of the third transistor, and a source of the fourth transistor is connected to a first potential. 4. The bit line multiplexer according to claim 3, further comprising a fifth transistor, which is an N-type metal-oxide-semiconductor transistor, connected to the transistor group and the selection transistor, and a gate of the fifth transistor connected to the source of the second transistor, a source of the fifth transistor connected to the bit line, and a drain of the fifth transistor connected to the source of the selection transistor. 5. The bit line multiplexer according to claim 1, wherein the first transistor, the second transistor, the selection transistor and the third transistor are P-type metal-oxide-semiconductor transistors, and the fourth transistor is an N-type transistor. type metal-oxide-semiconductor transistors. 6. The bit line multiplexer as claimed in claim 5, wherein a drain of the first transistor is connected to a source of the second transistor, a drain of the select transistor is connected to a source of the first transistor A source, a gate of the third transistor is connected to a drain of the second transistor, a source of the third transistor is connected to the source of the second transistor, a gate of the fourth transistor connected to a second potential, a source of the fourth transistor is connected to a drain of the third transistor, and a drain of the fourth transistor is grounded. 7. The bit line multiplexer according to claim 6, further comprising a fifth transistor, which is a P-type metal-oxide-semiconductor transistor, connected to the transistor group and the selection transistor, and a gate of the fifth transistor connected to the drain of the second transistor, a drain of the fifth transistor connected to the bit line, and a source of the fifth transistor connected to the drain of the selection transistor. 8. A bit line multiplexing system, comprising: a plurality of switches, each switch having a first end and a second end, the first end of each switch being connected to a bit line; and Multiple bit line multiplexers, each bit line multiplexer comprising: A transistor group includes a first transistor and a second transistor, the first transistor and the second transistor are connected in series, a gate of the first transistor is connected with a gate of the second transistor, and is connected to the second end; a selection transistor connected to the transistor group, a gate of the selection transistor connected to a selection line; a third transistor connected to the transistor group; and A fourth transistor connected to the third transistor. 9. The bit line multiplexing system according to claim 8, wherein the first transistor, the second transistor, the selection transistor and the third transistor are N-type metal-oxide-semiconductor transistors, and the fourth transistor is a P type metal-oxide-semiconductor transistors. 10. The bit line multiplexing system according to claim 9, wherein a source of the first transistor is connected to a drain of the second transistor, a source of the selection transistor is connected to a drain of the first transistor A drain, a gate of the third transistor is connected to a source of the second transistor, a drain of the third transistor is connected to the drain of the second transistor, a gate of the fourth transistor grounded, a drain of the fourth transistor is connected to a source of the third transistor, and a source of the fourth transistor is connected to a first potential. 11. The bit line multiplexing system according to claim 10, further comprising a fifth transistor, which is an N-type metal-oxide-semiconductor transistor, connected to the transistor group and the selection transistor, and a gate of the fifth transistor connected to the source of the second transistor, a source of the fifth transistor connected to the bit line, and a drain of the fifth transistor connected to the source of the selection transistor. 12. The bit line multiplexing system according to claim 8, wherein the first transistor, the second transistor, the selection transistor and the third transistor are P-type metal-oxide-semiconductor transistors, and the fourth transistor is an N-type transistor. type metal-oxide-semiconductor transistors. 13. The bit line multiplexing system according to claim 12, wherein a drain of the first transistor is connected to a source of the second transistor, a drain of the selection transistor is connected to a source of the first transistor A source, a gate of the third transistor is connected to a drain of the second transistor, a source of the third transistor is connected to the source of the second transistor, a gate of the fourth transistor connected to a second potential, a source of the fourth transistor is connected to a drain of the third transistor, and a drain of the fourth transistor is grounded. 14. The bit line multiplexing system according to claim 13, further comprising a fifth transistor, which is a P-type metal oxide semiconductor transistor, connected to the transistor group and the selection transistor, and a gate of the fifth transistor connected to the drain of the second transistor, a drain of the fifth transistor connected to the bit line, and a source of the fifth transistor connected to the drain of the selection transistor. 15. The bit line multiplexing system of claim 8, wherein the number of said switches is greater than the number of said bit line multiplexers.