CN104952803A - Forming method of semiconductor structure - Google Patents
Forming method of semiconductor structure Download PDFInfo
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- CN104952803A CN104952803A CN201410114617.6A CN201410114617A CN104952803A CN 104952803 A CN104952803 A CN 104952803A CN 201410114617 A CN201410114617 A CN 201410114617A CN 104952803 A CN104952803 A CN 104952803A
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- 238000000034 method Methods 0.000 title claims abstract description 93
- 239000004065 semiconductor Substances 0.000 title claims abstract description 68
- 239000000463 material Substances 0.000 claims abstract description 104
- 238000005530 etching Methods 0.000 claims abstract description 47
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 238000003860 storage Methods 0.000 claims abstract description 28
- 125000006850 spacer group Chemical group 0.000 claims description 53
- 230000015572 biosynthetic process Effects 0.000 claims description 49
- 238000007667 floating Methods 0.000 claims description 27
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 239000007789 gas Substances 0.000 claims description 19
- 238000000151 deposition Methods 0.000 claims description 13
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 12
- 230000008021 deposition Effects 0.000 claims description 12
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 238000005137 deposition process Methods 0.000 claims description 6
- 239000001307 helium Substances 0.000 claims description 6
- 229910052734 helium Inorganic materials 0.000 claims description 6
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- VIKNJXKGJWUCNN-XGXHKTLJSA-N norethisterone Chemical compound O=C1CC[C@@H]2[C@H]3CC[C@](C)([C@](CC4)(O)C#C)[C@@H]4[C@@H]3CCC2=C1 VIKNJXKGJWUCNN-XGXHKTLJSA-N 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- 229910021332 silicide Inorganic materials 0.000 claims description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 180
- 239000003989 dielectric material Substances 0.000 description 32
- 150000002500 ions Chemical class 0.000 description 17
- 238000005468 ion implantation Methods 0.000 description 9
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 230000000873 masking effect Effects 0.000 description 6
- 230000002093 peripheral effect Effects 0.000 description 6
- 230000007547 defect Effects 0.000 description 5
- 238000002955 isolation Methods 0.000 description 5
- 238000005304 joining Methods 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000000376 reactant Substances 0.000 description 3
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- -1 phosphonium ion Chemical class 0.000 description 2
- 238000009832 plasma treatment Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
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- 230000005465 channeling Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
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- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
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- 239000011229 interlayer Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
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Abstract
A forming method of a semiconductor structure includes providing a semiconductor substrate including a first zone having a plurality of separated storage grid structures and a second zone having a plurality of gate structures. First grooves are arranged between adjacent storage grid structures and second grooves are arranged between adjacent gate structures. The width of each first groove is smaller than that of the second groove. A liner layer is formed on the semiconductor substrate. The method also includes etching the liner layer for making the width of the top part of each first groove greater than that of the bottom part of each first groove; forming a second wall material layer on the liner layer; etching the second side wall material layer, forming a second side wall on the surface of the side wall of the gate structures and forming a medium layer filling the first grooves at the same time. By adopting the above method, the semiconductor structure forming technology can be simplified.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of formation method of semiconductor structure.
Background technology
In current semiconductor industry, integrated circuit (IC) products mainly can be divided into three major types type: logic, memory and analog circuit, and wherein memory device account for sizable ratio in integrated circuit (IC) products.Wherein, nonvolatile memory is widely used, and comprising: read-only memory, programmable read only memory, Erasable Programmable Read Only Memory EPROM, Electrically Erasable Read Only Memory, flash memory and ferroelectric memory etc.
Along with improving constantly of semiconductor device integrated level, the spacing between the size of the memory cell in memory and neighbor memory cell also constantly reduces, and the reliability of memory is faced with new challenges.
Pitch smaller between consecutive storage unit, the difficulty of filled media material between consecutive storage unit can be improved, be easy to form cavity in the dielectric layer between described consecutive storage unit, the isolation performance of described dielectric layer is caused to be deteriorated, make, between the bit line of consecutive storage unit, the problems such as bridging occur, also can improve the difficulty of the side wall forming memory cell, thus affect the reliability of memory.
Further, on described memory cell peripheral chip, also need to form peripheral circuit device, such as input/output transistors etc., usually need the side wall and the filled media layer that form described memory cell and peripheral circuit device respectively, processing step is comparatively complicated.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of semiconductor structure, simplifies the processing step forming memory.
For solving the problem, the invention provides a kind of formation method of semiconductor structure, comprise: Semiconductor substrate is provided, described Semiconductor substrate comprises first area and second area, described first area is formed with some discrete storage grid structures, described second area is formed with some grid structures, described storage grid structure comprises the floating gate structure being positioned at semiconductor substrate surface, be positioned at the control gate structure on floating gate structure surface, be positioned at first side wall on floating gate structure and control gate structure side wall surface, between adjacent storage grid structure, there is the first groove, there is between neighboring gate structures the second groove, the width of the first groove is less than the width of the second groove, form laying on a semiconductor substrate, described substrate layer covers and stores grid structure and grid structure, etching stores the portions of pads layer of grid structural top and the first groove upper part sidewall surfaces, makes the first groove top width be greater than the bottom width of the first groove, described laying is formed the second spacer material layer, the second spacer material layer on first area is filled full first groove and is covered and stores grid structural top, and the second spacer material layer on second area covers the inwall of the second groove and the top surface of grid structure, adopt without the described second spacer material layer of mask etching technique etching, form the second side wall being positioned at gate structure sidewall surface, form the dielectric layer of filling full described first groove simultaneously.
Optionally, after etched portions laying, the bottom width of the first groove is made to be 50% ~ 90% of the first groove top width.
Optionally, the etching technics that etching laying adopts is dry etch process.
Optionally, described dry etch process is anisotropic etch process.
Optionally, described dry etch process is that remote plasma assists dry etch process.
Optionally, the etching gas that described remote plasma assists dry etch process to adopt is NF
3and NH
3, NF
3with NH
3flow-rate ratio be 1:20 ~ 5:1, etching temperature is 40 degrees Celsius ~ 80 degrees Celsius, pressure be 0.5 holder ~ 50 hold in the palm.
Optionally, the method forming described second spacer material layer is high-aspect-ratio fill process.
Optionally, the deposition gases that described high-aspect-ratio fill process adopts comprises ozone and tetraethoxysilane, the flow of tetraethoxysilane is 500 milli gram/minute ~ 8000 milli gram/minute, the flow of ozone be 5000 standard milliliters/minute ~ 3000 standard milliliters/minute, pressure is that 300 holder ~ 600 are held in the palm, and reaction temperature is 400 degrees Celsius ~ 600 degrees Celsius.
Optionally, the deposition gases of described high-aspect-ratio fill process also comprises nitrogen, oxygen and helium, the flow of nitrogen be 1000 standard milliliters/minute ~ 10000 standard milliliters/minute, the flow of oxygen be 0 standard milliliters/minute ~ 5000 standard milliliters/minute, the flow of helium be 5000 standard milliliters/minute ~ 20000 standard milliliters/minute.
Optionally, the material of described second spacer material layer is silica.
Optionally, the material of described laying is silica.
Optionally, the technique forming described laying is atom layer deposition process, high-density plasma deposition process or plasma enhanced chemical vapor deposition technique.
Optionally, the thickness of described laying is 5nm ~ 25nm.
Optionally, described floating gate structure comprises: be positioned at the floating gate dielectric layer of described semiconductor substrate surface and be positioned at the floating boom pole on described floating gate dielectric layer surface, described control gate structure comprises: be positioned at the control gate dielectric layer of floating gate surface and be positioned at the control gate of control gate dielectric layer surface.
Optionally, described Semiconductor substrate also comprises the first source-drain electrode being positioned at the Semiconductor substrate storing grid structure both sides.
Optionally, also comprise: after described second side wall of formation, in the Semiconductor substrate of described grid structure both sides, form the second source-drain electrode.
Optionally, also comprise: at described second source-drain electrode surface and the surperficial formation metal silicide layer of grid structure.
Compared with prior art, technical scheme of the present invention has the following advantages:
In technical scheme of the present invention, between the adjacent storage grid structure on the first area of Semiconductor substrate, there is the first groove, there is between the neighboring gate structures on second area the second groove, and the width of the first groove is less than the width of the second groove; Form laying on a semiconductor substrate, described laying covers and stores grid structure and grid structure; After the described laying of formation, described laying is etched, remove the portions of pads layer storing grid structural top and the first groove upper part sidewall surfaces, the top width of the first groove is increased further; And then form described second spacer material layer, and described spacer material layer is etched, form the second side wall of grid structure both sides simultaneously and fill the dielectric layer of full first groove.Described laying can improve the inner surface contour of described first groove, makes the inwall of the first groove smoother, and the joining place of the first bottom portion of groove and sidewall is arcuation, can reduce the follow-up difficulty depositing spacer material layer in the first groove.And, curved with the laying storing grid top joining place owing to covering described first groove top sidewall, so, after forming described laying, described first groove top opening is larger, the reactant being conducive to follow-up formation second spacer material enters in described first groove, thus improves the quality of follow-up the second spacer material layer formed in described first groove.After described laying is etched, the top width of further increase by first groove, in the process of deposition second spacer material layer, reacting gas is more easily entered in described first groove, thus the second higher spacer material layer of filling quality can be formed in described first groove; The dielectric layer etching described second spacer material layer formation can directly as the isolation structure between adjacent storage grid structure, and the second side wall on described dielectric layer and second area II is formed simultaneously, compared with prior art, do not need the dielectric layer additionally formed again in the first groove, can processing step be saved.
Further; technical scheme of the present invention can adopt remote plasma to assist dry etch process to etch described laying; because described remote plasma assists the etching gas in dry etch process after the plasma treatment zone away from etch areas is in plasma; enter etch areas again; the energy of plasma is relatively low; less to the plasma damage of etachable material layer; the first side wall can not be damaged in the process of etching laying, thus described first side wall can not be affected to the protective effect storing grid structure.
Further, technical scheme of the present invention can adopt high-aspect-ratio fill process to form described second gate spacer material layer.Because the top width of described first groove is greater than bottom width, and described high-aspect-ratio fill process has higher filling capacity for the first groove that depth-to-width ratio is higher, so the filling quality of the second spacer material layer in described first groove is higher, defect is less, can directly as the isolation structure between adjacent storage grid structure, compared with prior art, do not need again the second spacer material layer in described first groove to be removed the separator being formed in addition and be positioned at the first groove, thus can processing step be saved.
Accompanying drawing explanation
Fig. 1 to Figure 10 is the structural representation of the forming process of the semiconductor structure of embodiments of the invention.
Embodiment
As described in the background art, because the spacing between consecutive storage unit is less, between consecutive storage unit, the difficulty of filled media material is comparatively large, is easy to form the defects such as cavity, affects the reliability of memory.
In the process of the side wall of the transistor of formation peripheral circuit, can chemical vapor deposition method be adopted, after forming spacer material layer on a semiconductor substrate, more described spacer material layer be carried out without mask etching to form described side wall.But because the spacing between memory cell is less, in the process forming described spacer material layer, described spacer material layer can fill the groove between completely described memory cell, but because the spacing between memory cell is less, cause the depth-to-width ratio of described groove higher, cause being filled in the spacer material layer in described groove and can there is the defects such as more cavity.Follow-up needs are after the side wall of transistor forming peripheral circuit, remove the spacer material layer in the groove between described memory cell again, then the technique that other can be filled high-aspect-ratio groove is again adopted, form the interlayer dielectric layer of filling full described groove, processing step is comparatively complicated.
Embodiments of the invention, when the side wall of periphery transistor, form the dielectric layer of the groove of filling between full consecutive storage unit simultaneously, and, there is no defect in described dielectric layer, thus can processing step be saved, and do not affect the performance of memory.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Please refer to Fig. 1, Semiconductor substrate 100 is provided, described Semiconductor substrate 100 comprises first area I and second area II, forms the first grid layer of dielectric material 201 covering first area I and second area I, the first grid material layer 202 being positioned at first grid layer of dielectric material 201 surface successively, covers the second gate layer of dielectric material 301 of the first grid material layer 202 on the II of first area, covers the second grid material layer 302 of the first grid material layer 202 on described second gate layer of dielectric material 301 and second area II on described Semiconductor substrate 100 surface.
In the present embodiment, described first area I and second area II is adjacent area, and in other embodiments of the invention, described first area I and second area II can also be non-conterminous region.Described first area I for the formation of memory, for the formation of the periphery transistor of memory on second area II, such as input and output transistor etc.
First grid layer of dielectric material 201 on described first area I is for the formation of the floating gate dielectric layer of memory cell, and the first grid layer of dielectric material 201 on second area II is for the formation of the gate dielectric layer of transistor.In the present embodiment, the material of described first grid layer of dielectric material 201 is silica.In other embodiments of the invention, the material of described first grid layer of dielectric material 201 can also be hafnium oxide, the contour K dielectric material of zirconia.
First grid material layer 202 on described first area I is for the formation of the floating boom pole of memory cell, and the first grid material layer 202 on second area II is for the formation of a part for the grid of transistor.In the present embodiment, the material of described first grid material layer 202 is polysilicon.
Second gate layer of dielectric material 301 on described first area I is for the formation of the control gate dielectric layer of memory cell.The material of the layer of dielectric material of second gate described in the present embodiment 301 is the laminated construction of oxide-nitride-oxide.In example described in other of the present invention, described second gate layer of dielectric material 301 also can adopt other dielectric materials.
Second grid material layer 302 on described first area I is for the formation of the control gate of memory cell, and the second grid material layer 302 on second area II is for the formation of a part for the grid of transistor.In the present embodiment, the material of described second grid material layer 202 is polysilicon.
First grid material layer 201 on described second area II is for the formation of the gate dielectric layer of peripheral circuit transistor.In example described in other of the present invention, can be different according to the operating voltage of transistor, adjust the thickness of the first grid material layer 201 at the diverse location place on described second area II.
In the present embodiment, chemical vapor deposition method is adopted to form described first grid layer of dielectric material 201, first grid material layer 202, second gate layer of dielectric material 301, second grid material layer 302.
Please refer to Fig. 2, graphical hard mask layer 400 is formed on described second grid material layer 302 surface, described Patterned masking layer 400 has the opening be positioned on the I of first area, expose part second grid material layer 302(and please refer to Fig. 1) surface, and cover the second grid material layer 302 on second area II; With described graphical hard mask layer 400 for mask, the second grid material layer 302(etched on the I of first area please refer to Fig. 1 successively), second gate layer of dielectric material 301(please refer to Fig. 1), first grid material layer 202(please refer to Fig. 1), formation control grid 302a, control gate dielectric layer 301a, floating boom 202a.
Described Patterned masking layer 400 defines position and the size of the storage grid structure of the memory cell formed on the I of first area, and described storage grid structure comprises: control gate 302a, control gate dielectric layer 301a, floating boom 202a, be positioned at the first grid layer of dielectric material 201 as floating gate dielectric layer below floating boom 202a.Between adjacent storage grid structure, there is the first groove 303.
In the present embodiment, first grid layer of dielectric material 201 is not etched, remain the first grid layer of dielectric material 201 of the semiconductor substrate surface between adjacent storage grid structure, described first grid layer of dielectric material 201 can prevent Semiconductor substrate 100 surface from sustaining damage in the process of follow-up formation first light doping section and the first source-drain electrode.
In other embodiments of the invention, also after etching first grid material layer 202, can continue to etch first grid layer of dielectric material 201, form floating gate dielectric layer.
The material of described graphical hard mask layer 400 is silicon nitride.In example described in other of the present invention, described graphical hard mask layer 400 can also adopt other hard mask materials, such as amorphous carbon, carborundum etc.
In the present embodiment, dry etch process is adopted to etch described second grid material layer 302, second gate layer of dielectric material 301, first grid material layer 202.
Please refer to Fig. 3, the first light dope ion implantation technology is carried out to the Semiconductor substrate 100 of described control gate 302a both sides, forms the first light doping section 501.
With described hard mask layer 400 for mask, carry out the first light dope ion implantation technology to described Semiconductor substrate 100, the Doped ions that described first light dope ion implantation technology adopts is N-type ion.In other embodiments of the invention, described Doped ions can also be P type ion.In the present embodiment, the Doped ions in described first light doping section 501 is phosphonium ion.
Semiconductor substrate 100 surface of described first area I also has first grid layer of dielectric material 201, in the process of carrying out the first light dope ion implantation technology, described first grid layer of dielectric material 201 can avoid the surface of Semiconductor substrate 100 to produce implant damage, and the channeling effect can improved in ion implantation process, controls the degree of depth injecting ion preferably.
Please refer to Fig. 4, the sidewall surfaces of the graphical hard mask layer 400 on described first area I and floating gate structure, control gate structure forms the first side wall 410.
In the present embodiment, described first side wall 410 is double-decker, and described first side wall 410 comprises the silicon nitride spacer 401 on monox lateral wall 402 and surface thereof.In example described in other of the present invention, described first side wall can also be single layer structure.
The method forming described first side wall 410 comprises: on the I of first area, form covering first grid layer of dielectric material 201(please refer to Fig. 3), floating boom 202a, control gate dielectric layer 301a, after the sidewall of control gate 302a and graphical hard mask layer 400 and the silicon oxide layer of graphical hard mask layer 400 top surface and silicon nitride layer, adopt without mask etching technique, etch described silicon nitride layer and silicon oxide layer, remove the silicon oxide layer and the silicon nitride layer that are positioned at graphical hard mask layer 400 top surface and first grid layer of dielectric material 201 surface, form monox lateral wall 402 and silicon nitride spacer 401.Further, continue etching first grid layer of dielectric material 201 and form the floating gate dielectric layer 201a be positioned at below floating boom 201a and side wall 410.Described first grid layer of dielectric material 201 can form the etching stop layer of the first side wall 410 as etch nitride silicon layer and silicon oxide layer.In the present embodiment, described first side wall 410 is also as the part storing grid structure.
Described first side wall 410 is as the mask of follow-up formation first source-drain electrode.After forming described first side wall 410, the width of the first groove 303 between adjacent storage grid structure declines further, and the depth-to-width ratio of described first groove 303 improves, and further increases the difficulty of filled media layer in described first groove 303.
Please refer to Fig. 4, the first heavy doping ion injection is carried out to the Semiconductor substrate 100 bottom the first groove 303, forms the first source-drain electrode 502.
It is N-type ion that described first heavy doping ion injects the Doped ions adopted.In other embodiments of the invention, described Doped ions can also be P type ion.In the present embodiment, the Doped ions in described first source-drain electrode area 502 is phosphonium ion.
In the present embodiment, adjacent memory cell shares described first source-drain electrode 502.
Please refer to Fig. 5, the graphical hard mask layer 400(removed on second area II please refer to Fig. 4), then the second grid material layer 302(etched on second area II please refer to Fig. 4), first grid material layer 301(please refer to Fig. 4), form grid 310, then the second light dope ion implantation is carried out to the Semiconductor substrate 100 of described grid 310 both sides, form the second light doping section 503.
In the present embodiment; eliminate the Patterned masking layer 400 on second area II; and the Patterned masking layer 400 being positioned at control gate 302a top remained on the II of first area, the Patterned masking layer 400 at described control gate 302a top can protect described control gate 302a in follow-up processing step.In example described in other of the present invention, can remove according to concrete requirement on devices or retain the Patterned masking layer 400 at described control gate 302a top.
Described grid 310 comprises Part I grid 202b and Part II grid 302b, described Part I grid 202b is remaining part first grid material layer after etching first grid material layer 202, and described Part II grid 302b is remaining part second grid material layer after etching second grid material layer 302.In the present embodiment, described Part I grid 202b is identical with the material of Part II grid 302b, is polysilicon, and described Part I grid 202b and Part II grid 302b is jointly as the grid 310 of the transistor that second area II is formed.
There is the second groove 304, because the device integration on described second area II is less than the integrated level of the memory that first area I will be formed, so the width of described second groove 304 is greater than the width of the first groove 303 between neighboring gates 310.
In the present embodiment, first grid layer of dielectric material 202 is not etched, remain the first grid layer of dielectric material 202 on Semiconductor substrate 100 surface between neighboring gates 310, described first grid layer of dielectric material 202 can prevent Semiconductor substrate 100 surface from sustaining damage in the process of follow-up formation second light doping section and the second source-drain electrode.
In other embodiments of the invention, also after etching second grid material layer 302 and first grid material layer 202, can continue to etch first grid layer of dielectric material 201, form gate dielectric layer.
After the described grid 310 of formation, form mask layer (not shown) at described grid 310 top, carry out the second light dope ion implantation with described mask layer for the Semiconductor substrate of mask to grid 310 both sides, form the second light doping section 503.
In the present embodiment, the Doped ions of described second light dope ion implantation is N-type ion, and the transistor that second area II is formed is nmos pass transistor.
In other embodiments of the invention, according to the dissimilar transistor that second area II is formed, and the transistor of different operating voltage, carry out the second light dope ion implantation respectively, form the second light doping section that each transistor is different separately.
Please refer to Fig. 6, described Semiconductor substrate 100 forms laying 601, described laying 601 covers and stores grid structure and grid structure 310.
Between the material of described laying 601 and the first side wall 410, there is higher selective etching ratio, in the process of laying described in subsequent etching 601, can avoid causing damage to the first side wall 410.In the present embodiment, the material of described laying 601 is silica.
Atom layer deposition process, high-density plasma deposition process or plasma enhanced chemical vapor deposition technique etc. can be adopted to form described laying 601.The deposition quality of the laying 601 adopting above-mentioned technique to be formed is higher, and interface quality is better.
The thickness of described laying 601 is 5nm ~ 25nm.In other embodiments of the invention, according to the width of described first groove 303, the thickness of described laying 601 can be adjusted.
After the inner wall surface of described first groove 303 forms laying 601, described laying 601 can improve the inner surface contour of described first groove 300, make the inwall of the first groove 303 smoother, bottom first groove 303 and the joining place of sidewall be arcuation, the difficulty of follow-up deposition spacer material layer in the first groove 303 can be reduced.And, curved with the laying 601 storing grid top joining place owing to covering described first groove 303 top sidewall, so, after forming described laying 601, described first groove 303 open top is larger, the reactant being conducive to follow-up formation second spacer material enters in described first groove 303, thus improves the quality of the second spacer material layer formed in described first groove 303.
Please refer to Fig. 7, etching stores the portions of pads layer 601 of grid structural top and the first groove 303 upper part sidewall surfaces, and the top width of the first groove 303 is increased.
Dry etch process can be adopted to etch described laying 601.Described dry etch process can be isotropic etching technique.
In the present embodiment, the etching technics of employing is the dry method etch technology that remote plasma is assisted, the dry etch process employing NF that described remote plasma is auxiliary
3, NH
3as etching gas, wherein, NF
3with NH
3flow-rate ratio be 1:20 ~ 5:1, etching temperature is 40 degrees Celsius ~ 80 degrees Celsius, pressure be 0.5 holder ~ 50 hold in the palm.Described NF
3with NH
3flow-rate ratio in the scope of 1:20 ~ 5:1, and control etching temperature and the pressure of described dry etching, the uniformity of described dry etch process can be made higher, the laying after etching can not be made to produce rough surface.And, in the dry etch process that described remote plasma is auxiliary, etching gas is after the plasma treatment zone away from etch areas is in plasma, enter etch areas again, make the energy of the plasma in etch areas relatively low, less to the plasma damage of etachable material layer.Further, described etching technics has higher selectivity to silica.In the process of etching laying 601, the first side wall 410 can not be damaged to, thus described first side wall 410 can not be affected to the protective effect storing grid structure.
In enforcement embodiment of the present invention, described etching gas can also be comprise NF
3, HF, F
2, CHF
3or C
3h
2f
6in one or more fluoro-gas, and CH
4, C
3h
8, CH
2cl
2in one or more hydrogen-containing gas.
After removing the portions of pads layer 601 being positioned at and storing on grid structural top and the first groove 303 upper part sidewall, the A/F at the first groove 303 top is increased, thus make in the process of subsequent deposition second spacer material layer, reacting gas can more easily enter in described first groove 303, thus in described first groove 303, form the second higher spacer material layer of filling quality.
After etching described laying 601, the width at the first groove 303 top of formation is greater than bottom width, concrete, and described first groove 303 bottom width can be 50% ~ 90% of top width.
In etching process, not removing only the laying 601 being positioned at and storing grid structural top and the first groove 303 upper part sidewall surfaces, also eliminate grid 310 top on second area II and the portions of pads layer 601 on sidewall.
Please refer to Fig. 8, described laying 601 is formed the second spacer material layer 602, the second spacer material layer 602 on the I of first area is filled full first groove 303(and be please refer to Fig. 8) and cover storage grid structural top, the second spacer material layer 602 on second area II covers the inwall of the second groove 304 and the top surface of grid structure 310.
The material of described second spacer material layer 602 is silica, and the method forming described second spacer material layer 602 is high-aspect-ratio fill process.In the present embodiment, the deposition gases that described high-aspect-ratio fill process adopts comprises tetraethoxysilance and ozone, wherein, the flow of tetraethoxysilane is 500 milli gram/minute ~ 8000 milli gram/minute, the flow of ozone be 5000 standard milliliters/minute ~ 3000 standard milliliters/minute, pressure is that 300 holder ~ 600 are held in the palm, and reaction temperature is 400 degrees Celsius ~ 600 degrees Celsius.
In example described in other of the present invention, described deposition gases also comprises: nitrogen, oxygen and helium, the flow of nitrogen be 1000 standard milliliters/minute ~ 10000 standard milliliters/minute, the flow of oxygen be 0 standard milliliters/minute ~ 5000 standard milliliters/minute, the flow of helium be 5000 standard milliliters/minute ~ 20000 standard milliliters/minute.
The thickness of described second spacer material layer is greater than 1/2 of the first groove 303 width, so the second spacer material layer 602 on described first area I fills full described first groove 303, and covers the top surface storing grid structure; The width of the second groove 304 between the neighboring gates 310 on second area II is comparatively large, and described second spacer material layer 602 covers the inner wall surface of the second groove 304 and the top surface of grid 310.
Because the top width of described first groove 303 is greater than bottom width, and described high-aspect-ratio fill process has higher filling capacity for the first groove 303 that depth-to-width ratio is higher, so the filling quality of the second spacer material layer 602 in described first groove 303 is higher, defect is less, can directly as the separator between adjacent storage grid structure, compared with prior art, the present embodiment is follow-up does not need to be removed by the second spacer material layer 602 in described first groove 303 separator being formed in addition and be positioned at the first groove 303 again.
Please refer to Fig. 9, adopt and please refer to Fig. 8 without the described second spacer material layer 602(of mask etching technique etching), removing to be positioned at stores bottom grid structural top, the second groove 304 and the part second spacer material layer 602 at grid 310 top, form the second side wall 620 being positioned at grid 310 sidewall surfaces, form the dielectric layer 610 of filling full described first groove simultaneously.
Described is dry etch process without mask etching technique, and the etching gas that described dry etch process adopts comprises CF
4, CHF
3, C
3h
4f
4or C
2h
2f
4in one or more fluoro-gas.
In the present embodiment, while the side wall 620 forming grid 310 both sides on second area II, form the dielectric layer 610 between adjacent storage grid structure on the I of first area, and, the deposition quality of described dielectric layer 610 is higher, can directly as the isolation structure stored between grid structure.
Compared with prior art, the present embodiment, described dielectric layer 610 is removed by follow-up needs, can reduce processing step, and, avoid in removal dielectric layer process, to the damage that Semiconductor substrate 100 and storage grid structure cause.
Please refer to Figure 10, with described second side wall 620 for mask, in the Semiconductor substrate 100 to grid 310 both sides, carry out the second heavy doping ion injection, form the second source-drain electrode 504.
In embodiments of the invention, the second source-drain electrode 504 in the Semiconductor substrate 100 of different grid 310 both sides can be formed simultaneously.
In other embodiments of the invention, according to the dissimilar transistor that second area II is formed, and the transistor of different operating voltage, adjust dosage and the degree of depth of the second heavy doping ion injection respectively, form the second source-drain electrode 504 that each transistor is different separately.
In example described in other of the present invention, follow-uply can also form metal silicide layer, to reduce the contact resistance of grid 310 and the second source-drain electrode 504 surface at described grid 310 and the second source-drain electrode 504 surface.
In sum, in the present embodiment, form laying on a semiconductor substrate, described laying covers and stores grid structure and grid structure; After the described laying of formation, described laying is etched, remove the portions of pads layer storing grid structural top and the first groove upper part sidewall surfaces, the top width of the first groove is increased further; And then form described second spacer material layer, and described spacer material layer is etched, form the second side wall of grid structure both sides simultaneously and fill the dielectric layer of full first groove.Described laying can improve the inner surface contour of described first groove, make the inwall of the first groove smoother, the joining place of the first bottom portion of groove and sidewall is arcuation, and make described first groove top opening larger, the reactant being conducive to follow-up formation second spacer material enters in described first groove, thus improves the quality of follow-up the second spacer material layer formed in described first groove.
After described laying is etched, the top width of the first groove can be increased further, in the process of deposition second spacer material layer, reacting gas is more easily entered in described first groove, thus the second higher spacer material layer of filling quality can be formed in described first groove; The dielectric layer etching described second spacer material layer formation can directly as the isolation structure between adjacent storage grid structure, and the second side wall on described dielectric layer and second area is formed simultaneously, compared with prior art, do not need the dielectric layer additionally formed again in the first groove, can processing step be saved.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (17)
1. a formation method for semiconductor structure, is characterized in that, comprising:
Semiconductor substrate is provided, described Semiconductor substrate comprises first area and second area, described first area is formed with some discrete storage grid structures, described second area is formed with some grid structures, described storage grid structure comprises the floating gate structure being positioned at semiconductor substrate surface, the control gate structure being positioned at floating gate structure surface, is positioned at first side wall on floating gate structure and control gate structure side wall surface, between adjacent storage grid structure, there is the first groove, have the second groove between neighboring gate structures, the width of the first groove is less than the width of the second groove;
Form laying on a semiconductor substrate, described laying covers and stores grid structure and grid structure;
Etching stores the portions of pads layer of grid structural top and the first groove upper part sidewall surfaces, makes the first groove top width be greater than the bottom width of the first groove;
Described laying is formed the second spacer material layer, the second spacer material layer on first area is filled full first groove and is covered and stores grid structural top, and the second spacer material layer on second area covers the inwall of the second groove and the top surface of grid structure;
Adopt without the described second spacer material layer of mask etching technique etching, form the second side wall being positioned at gate structure sidewall surface, form the dielectric layer of filling full described first groove simultaneously.
2. the formation method of semiconductor structure according to claim 1, is characterized in that, after etched portions laying, makes the bottom width of the first groove be 50% ~ 90% of the first groove top width.
3. the formation method of semiconductor structure according to claim 1, is characterized in that, the etching technics that etching laying adopts is dry etch process.
4. the formation method of semiconductor structure according to claim 3, is characterized in that, described dry etch process is anisotropic etch process.
5. the formation method of semiconductor structure according to claim 3, is characterized in that, described dry etch process is that remote plasma assists dry etch process.
6. the formation method of semiconductor structure according to claim 5, is characterized in that, the etching gas that described remote plasma assists dry etch process to adopt is NF
3and NH
3, NF
3with NH
3flow-rate ratio be 1:20 ~ 5:1, etching temperature is 40 degrees Celsius ~ 80 degrees Celsius, pressure be 0.5 holder ~ 50 hold in the palm.
7. the formation method of semiconductor structure according to claim 1, is characterized in that, the method forming described second spacer material layer is high-aspect-ratio fill process.
8. the formation method of semiconductor structure according to claim 7, it is characterized in that, the deposition gases that described high-aspect-ratio fill process adopts comprises ozone and tetraethoxysilane, the flow of tetraethoxysilane is 500 milli gram/minute ~ 8000 milli gram/minute, the flow of ozone be 5000 standard milliliters/minute ~ 3000 standard milliliters/minute, pressure is that 300 holder ~ 600 are held in the palm, and reaction temperature is 400 degrees Celsius ~ 600 degrees Celsius.
9. the formation method of semiconductor structure according to claim 8, it is characterized in that, the deposition gases of described high-aspect-ratio fill process also comprises nitrogen, oxygen and helium, the flow of nitrogen be 1000 standard milliliters/minute ~ 10000 standard milliliters/minute, the flow of oxygen be 0 standard milliliters/minute ~ 5000 standard milliliters/minute, the flow of helium be 5000 standard milliliters/minute ~ 20000 standard milliliters/minute.
10. the formation method of semiconductor structure according to claim 1, is characterized in that, the material of described second spacer material layer is silica.
The formation method of 11. semiconductor structures according to claim 1, is characterized in that, the material of described laying is silica.
The formation method of 12. semiconductor structures according to claim 1, is characterized in that, the technique forming described laying is atom layer deposition process, high-density plasma deposition process or plasma enhanced chemical vapor deposition technique.
The formation method of 13. semiconductor structures according to claim 1, is characterized in that, the thickness of described laying is 5nm ~ 25nm.
The formation method of 14. semiconductor structures according to claim 1, it is characterized in that, described floating gate structure comprises: be positioned at the floating gate dielectric layer of described semiconductor substrate surface and be positioned at the floating boom pole on described floating gate dielectric layer surface, described control gate structure comprises: be positioned at the control gate dielectric layer of floating gate surface and be positioned at the control gate of control gate dielectric layer surface.
The formation method of 15. semiconductor structures according to claim 1, is characterized in that, described Semiconductor substrate also comprises the first source-drain electrode being positioned at the Semiconductor substrate storing grid structure both sides.
The formation method of 16. semiconductor structures according to claim 1, is characterized in that, also comprise: after described second side wall of formation, in the Semiconductor substrate of described grid structure both sides, form the second source-drain electrode.
The formation method of 17. semiconductor structures according to claim 16, is characterized in that, also comprise: at described second source-drain electrode surface and the surperficial formation metal silicide layer of grid structure.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108389831A (en) * | 2018-02-02 | 2018-08-10 | 上海华虹宏力半导体制造有限公司 | The fill method of interlayer dielectric layer |
| CN108630611A (en) * | 2017-03-21 | 2018-10-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN109003978A (en) * | 2017-06-07 | 2018-12-14 | 北京兆易创新科技股份有限公司 | The preparation method and memory of memory |
| CN111261633A (en) * | 2020-01-02 | 2020-06-09 | 合肥晶合集成电路有限公司 | Transistor structure and preparation method thereof |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1855444A (en) * | 2005-03-31 | 2006-11-01 | 英飞凌科技股份公司 | Method of production of charge-trapping memory devices |
| CN101593690A (en) * | 2008-05-30 | 2009-12-02 | 中芯国际集成电路制造(北京)有限公司 | The formation method of stacked dielectric layer and the formation method of before-metal medium layer |
| CN101740471A (en) * | 2008-11-17 | 2010-06-16 | 中芯国际集成电路制造(上海)有限公司 | Methods for filling gap groove and forming semiconductor device |
| CN102412206A (en) * | 2010-09-19 | 2012-04-11 | 中芯国际集成电路制造(上海)有限公司 | Manufacture method of flash memory |
| CN102800689A (en) * | 2011-05-24 | 2012-11-28 | 海力士半导体有限公司 | Nonvolatile memory device and method for fabricating the same |
-
2014
- 2014-03-25 CN CN201410114617.6A patent/CN104952803A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1855444A (en) * | 2005-03-31 | 2006-11-01 | 英飞凌科技股份公司 | Method of production of charge-trapping memory devices |
| CN101593690A (en) * | 2008-05-30 | 2009-12-02 | 中芯国际集成电路制造(北京)有限公司 | The formation method of stacked dielectric layer and the formation method of before-metal medium layer |
| CN101740471A (en) * | 2008-11-17 | 2010-06-16 | 中芯国际集成电路制造(上海)有限公司 | Methods for filling gap groove and forming semiconductor device |
| CN102412206A (en) * | 2010-09-19 | 2012-04-11 | 中芯国际集成电路制造(上海)有限公司 | Manufacture method of flash memory |
| CN102800689A (en) * | 2011-05-24 | 2012-11-28 | 海力士半导体有限公司 | Nonvolatile memory device and method for fabricating the same |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108630611A (en) * | 2017-03-21 | 2018-10-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN109003978A (en) * | 2017-06-07 | 2018-12-14 | 北京兆易创新科技股份有限公司 | The preparation method and memory of memory |
| CN108389831A (en) * | 2018-02-02 | 2018-08-10 | 上海华虹宏力半导体制造有限公司 | The fill method of interlayer dielectric layer |
| CN111261633A (en) * | 2020-01-02 | 2020-06-09 | 合肥晶合集成电路有限公司 | Transistor structure and preparation method thereof |
| CN113380812A (en) * | 2020-02-25 | 2021-09-10 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
| CN113380812B (en) * | 2020-02-25 | 2023-06-09 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
| CN114497048A (en) * | 2020-10-26 | 2022-05-13 | 北方集成电路技术创新中心(北京)有限公司 | Semiconductor structure and method of forming the same |
| CN114220815A (en) * | 2021-12-13 | 2022-03-22 | 华虹半导体(无锡)有限公司 | Method for forming semiconductor structure |
| CN114220815B (en) * | 2021-12-13 | 2025-05-13 | 华虹半导体(无锡)有限公司 | Method for forming semiconductor structure |
| CN115537765A (en) * | 2022-09-27 | 2022-12-30 | 盛吉盛(宁波)半导体科技有限公司 | Plasma chemical vapor deposition device and small-size groove filling method |
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