CN104937569A - Processing device with address translation probing and methods - Google Patents

Abstract

A data processing device is provided that employs multiple translation look-aside buffers (TLBs) associated with respective processors that are configured to store selected address translations of a page table of a memory shared by the processors. The processing device is configured such that when an address translation is requested by a processor and is not found in the TLB associated with that processor, another TLB is probed for the requested address translation. The probe across to the other TLB may occur in advance of a walk of the page table for the requested address or alternatively a walk can be initiated concurrently with the probe. Where the probe successfully finds the requested address translation, the page table walk can be avoided or discontinued.

Description

Processing apparatus and method with address translation detection

Related Application Cross Reference

This application claims the benefit of US Application No. 13/723,379, filed December 21, 2012, the contents of which are incorporated herein by reference.

field

The present disclosure is generally directed to data processing apparatuses that include translation lookaside buffers (TLBs) employing address translations related to memory page tables.

background

The use of virtual addressing is well known in the field of data processing. Typically, page tables are provided to maintain a list of virtual addresses with corresponding physical memory locations of data associated with the virtual addresses, ie: address translations. The process of obtaining the physical memory address where data is stored from the page table list of virtual addresses is called a page table walk.

4Kb and 8Kb virtual pages are commonly used, but larger sizes such as 2Mb or 4Mb or larger can be used. Page table lookups can take a significant amount of time compared to the operating speed of the processor. To avoid doing a page table lookup to fetch every physical address (ie, every translation) of stored data corresponding to a virtual address, a Translation Lookaside Buffer (TLB) is used to store address translations used or likely to be used by the processor.

Typically, the processor will first look for the required address translation in the TLB associated with the memory page table. If the desired address translation is found, then there is no need to consult the page tables. If the desired address translation is not found, then the page table is consulted to find the address translation. In some cases, multi-level TLBs that serve different functions are placed between the processor and the page tables, so that the processor will descend through several levels of the hierarchy looking for the required translation, and only descend through the A page table lookup is performed when the required translation is not found in the TLB hierarchy.

Page tables and TLBs are generally employed in any type of data processor, including but not limited to: central processing units (CPUs), graphics processing units (GPUs), and accelerated processing units (APUs).

Overview of Exemplary Embodiments

A data processing apparatus is provided employing a plurality of translation lookaside buffers (TLBs) associated with respective processors, the TLBs being configured to store selected address translations of memory page tables shared by the processors. The processing means is configured such that when a processor requests an address translation and the address translation is not found in a TLB associated with the processor, another TLB is probed for the requested address translation. The probing for another TLB may occur before the lookup of the page table for the requested address, or the page table lookup may start concurrently with the probing. In the event that the probe successfully finds the requested address translation, page table lookups may be avoided or stopped.

In one embodiment, the data processing arrangement comprises first and second processing units and a page table of a shared memory. A first translation lookaside buffer (TLB) hierarchy is configured to store selected address translations for page tables used by the first processing unit. The second TLB hierarchy is configured to store select address translations for page tables used by the second processing unit. The processing means is configured to probe the second TLB hierarchy for an address translation requested by the first processing unit upon occurrence of a condition that the requested address translation is not found in the first TLB hierarchy.

Such a data processing apparatus may be configured to perform a page table lookup for a requested address translation when the condition arises that the requested address translation is not found in the second TLB hierarchy. Alternatively, the data processing means may be configured to start the lookup of the page table for the requested address translation concurrently with the probing of the second TLB hierarchy.

In some embodiments, the data processing apparatus is also configured to probe the first TLB hierarchy for an address translation requested by the second processing unit when a condition occurs that is not found in the second TLB hierarchy by Address translation requested by the second processing unit. In this case, the data processing means may be configured to perform a lookup of the page table for an address translation requested by the second processing unit upon occurrence of a condition not found in the probe of the first TLB hierarchy Address translation requested by the second processing unit. Alternatively, the data processing means may be configured to start the lookup of the page table for an address translation requested by the second processing unit simultaneously with the probing of the first TLB hierarchy.

For example, the processing units may be of the same or different types, such as a central processing unit (CPU), a graphics processing unit (GPU), or an accelerated processing unit (APU), or some combination thereof. Either, or both, the first or second processing unit may be one of a plurality of first or second processing units respectively associated with a respective TLB hierarchy.

In one example, all of the first processing units are CPUs, and the first TLB hierarchy includes a single level-one TLB associated with each CPU to store page tables used by that CPU Selected address translation; and a second-level TLB associated with the first-level TLB. In this example, the processing means is configured to unsuccessfully search the first-level TLB and the second-level TLB associated with the first processing unit in order to find the address translation requested by the first processing unit, and to use it as an address translation requested by the first processing unit. The address translation requested by the unit probes the status of the second TLB hierarchy.

In another example, all of the first processing units are GPUs, and the first TLB hierarchy includes a single TLB associated with all of the GPUs to store selected address translations for page tables used by the GPUs. In this example, the processing means is configured to unsuccessfully search a single TLB for an address translation requested by the first processing unit as a condition of probing the second TLB hierarchy for the address translation requested by the first processing unit .

The data processing apparatus may have a plurality of second processing units including a second processing unit, wherein the second TLB hierarchy includes a single level of TLB associated with each of the plurality of second processing units associated to store a select address translation of the page table used by this second processing unit; and a second level TLB associated with the first level TLB. In this case, the processing means is configured to probe the second TLB hierarchy for an address translation requested by the first processing unit by searching the first level TLB and the second level TLB associated with the selected second processing unit, In order to find the address translation requested by the first processing unit.

In another embodiment, the data processing apparatus includes a first translation lookaside buffer (TLB) configured to store selected address translations for page tables used by the first processing unit; and a second TLB configured to store Selected address translation of the page table used by the second processing unit. The processing means is configured to probe the second TLB for an address translation requested by the first processing unit when a condition occurs, the requested address translation not being found in the first TLB.

Such a data processing apparatus may include a two-level TLB, wherein the first and second TLBs comprise a first level of a selective address-translated TLB hierarchy configured to store page tables used by the first and second processing units, and the two Level TLBs comprise the second level of the TLB hierarchy. In this case, the data processing apparatus may be configured to perform a page table lookup for the requested address translation when the condition arises that the requested address is not found in a probe of the second TLB or secondary TLB convert. As an alternative embodiment, the data processing apparatus may be configured to start a lookup of the page table for the requested address translation at the same time as the probing of the second TLB when the condition occurs that the request is not found in the secondary TLB address translation.

Methods corresponding to example embodiments and alternative embodiments are also provided.

Additionally, another embodiment provides a non-transitory computer-readable storage medium storing a set of instructions for execution by a general-purpose computer to facilitate fabrication of selectively designed integrated circuits. The non-transitory computer-readable storage medium includes instructions, which are hardware description language (HDL) instructions for manufacture of an apparatus including one or more aspects of the embodiments.

Such an integrated circuit may include a first TLB hierarchy configured to store selected address translations for page tables used by a first processing unit; and a second TLB hierarchy configured to store selected address translations for a page table used by a second processing unit Alternative address translation for page tables. In this case, the integrated circuit is configured to probe the second TLB hierarchy for an address translation requested by the first processing unit when a condition occurs that the requested address is not found in the first TLB hierarchy convert.

As an alternative embodiment, the integrated circuit may include a first translation lookaside buffer (TLB) configured to store selected address translations for page tables used by the first processing unit; and a second TLB configured to store Selected address translation of the page table used by the second processing unit. In this case, the integrated circuit is configured to probe the second TLB for an address translation requested by the first processing unit when a condition occurs that the requested address translation is not found in the first TLB.

Brief description of the drawings

A more detailed understanding can be obtained from the following description, given by way of example in conjunction with the accompanying drawings.

Figure 1 is a block diagram of a processing device in which one or more disclosed embodiments may be implemented.

Figure 2 is a block diagram of another processing device in which one or more disclosed embodiments may be implemented.

Figure 3 is a block diagram of yet another processing device in which one or more disclosed embodiments may be implemented.

detail

Today, data processing devices are ubiquitous and consolidated into a large number of different types of products. Typically, processors are configured to utilize a Translation Lookaside Buffer (TLB), which is configured to store memory page Table selection address translation.

Referring to FIG. 1 , there is shown an example data processing apparatus 100 in which a memory 110 including a page table 120 is shared by a plurality of processors. In the example shown in FIG. 1 , the processing arrangement 100 comprises a first TLB hierarchy 130 configured to store a first set 140 of selected address translations of page tables 120 for a first processing unit 141 , 142 . The processing arrangement 100 also includes a second TLB hierarchy 150 configured to store a second set 160 of selected address translations of the page tables 120 for the second processing units 161 , 162 .

In operation, selected address translations of the page table 120 are stored in the first TLB hierarchy 130 of the first group 140 for the first processing units 141 , 142 . Selected address translations of the page tables 120 are also stored in the second TLB hierarchy 150 of the second set 160 for the second processing units 161 , 162 . In connection with data processing, the processing units 141, 142, 161, 162 will first look for the required address translations in their respective TLB hierarchies 130, 150 associated with memory page tables. Where the TLB hierarchy 130, 150 includes multiple levels of TLBs, the processor will descend through several levels of the hierarchy to find the required address translation.

If the desired address translation is found, then page table 120 need not be consulted. If the desired address translation is not found, then page table 120 may need to be consulted to find the address translation.

In order to avoid as far as possible the need to wait for the result of the query of the page table, the processing device 100 is configured to probe 170 for an address translation requested by one of the first processing units 141, 142 of the first group 140 when a condition occurs The second TLB hierarchy 150 , the condition is that the requested address translation is not found in the first TLB hierarchy 130 . The data processing apparatus 100 is further configured to perform a lookup of the page table 120 for the requested address translation when a condition arises that the requested address translation is not found in the probe 170 of the second TLB hierarchy 150 . As an alternative embodiment, the data processing apparatus 100 may be configured to start the lookup of the page table 120 for the requested address translation concurrently with the probing of the second TLB hierarchy.

In one embodiment, the data processing arrangement 100 is also configured to probe 172 the first TLB hierarchy 130 for an address translation requested by one of the second processing units 161, 162 when a condition occurs, the condition being The address translation requested by the second processing unit 161 , 162 is not found in the second TLB hierarchy 150 . In this case, the data processing arrangement 100 may be configured to perform a lookup of the page table 120 for an address translation requested by the second processing unit 161, 162 when a condition arises that the first TLB hierarchy The address translation requested by the second processing unit 161 , 162 was not found in the probe 172 of 130 . Alternatively, the data processing arrangement 100 may be configured to start the lookup of the page table for the address translation requested by the second processing unit 161 , 162 at the same time as the probing 172 of the first TLB hierarchy 130 .

The processing units 141 , 142 , 161 , 162 may be of any type, like for example: a central processing unit (CPU), a graphics processing unit (GPU) or an accelerated processing unit (APU). In one embodiment, the processing units within each group 140, 160 are of the same type, although different processors may be included in the same group. Although each set 140, 160 is shown as including two processing units, this is for illustration purposes. Handling unit groups of different sizes can be used. Additionally, each group 140, 160 may include more than two processors, or one or both groups 140, 160 may have only a single processor.

The processing device 100 may include more than two groups of processing units sharing memory and respective TLB hierarchies. In this case, any processing unit's translation request that cannot be fulfilled by reference to the TLB hierarchy associated with that processing unit may cause all or a subset of the other TLB hierarchies to be probed for the requested address translation. In one embodiment, page table lookups may be avoided if a hit is encountered in any probed TLB hierarchy. Alternatively, the probe can be issued at the same time the page table lookup is started. In this case, if a translation hit is returned by any query device, the page table query is aborted or its response is ignored.

Although two TLB hierarchies 130, 150 are shown, the processing device 100 may include additional TLB hierarchies configured to store selections of page tables 120 for additional groups of processing units, respectively. address translation. Additionally, the TLB hierarchy is configured to store select address translations for a plurality of page tables associated with memory 110 and/or other memory. The TLB hierarchy can also be configured with a single level or multiple levels.

Referring to Figure 2, another more specific example of an embodiment is shown. In FIG. 2 , an example data processing apparatus 200 has a shared memory 210 including a page table 220 . The processing device 200 comprises a first TLB hierarchy 230 configured to store selected address translations for a page table 220 of a group 240 of central processing units (CPUs) 241 , 242 . The TLB hierarchy 230 for the CPU group 240 is a multi-level hierarchy that includes a first-level TLB 231, 232 associated with each CPU 241, 242 of the CPU group 240, respectively, and a second-level TLB 231, 232 associated with the CPU group 240. Level TLB 280.

Variations in the configuration of TLB hierarchy 230 and/or CPU group 240 will be apparent to those skilled in the art. For example, where additional CPUs are included in CPU group 240, TLB hierarchy 230 may include additional first-level TLBs respectively associated with each additional CPU and second-level TLB 280 indicated in the phantom. Additionally, TLB hierarchy 230 may include more than two levels.

In the example of FIG. 2 , the processing device 200 also includes a second TLB hierarchy 250 configured to store the Select Address Translation. In this example, TLB hierarchy 250 for GPU group 260 is a single level hierarchy with a single TLB associated with all GPUs 261, 262 of GPU group 240, respectively.

Variations in the configuration of TLB hierarchy 250 and/or GPU group 260 will be apparent to those skilled in the art. For example, where additional GPUs are included in GPU group 260, each additional GPU is associated with TLB 250 indicated in the phantom.

In operation, selected address translations for the page table 220 are stored in the first TLB hierarchy 230 for the set 240 of CPUs 241, 242. Selected address translations for the page tables 220 are also stored in the second TLB hierarchy 250 for the set 260 of the GPUs 261, 262. In conjunction with data processing, the CPUs 241, 242 and GPUs 261, 262 will first look in their respective TLB hierarchies 230, 250 for the required address translations. With respect to the CPU TLB hierarchy 230, the CPUs 241, 242 will first look in their respective associated first-level TLBs 231, 232, and then look for the required address translation in the second-level TLBs.

If the required address translation is found, then the page table 220 need not be consulted. If the desired address translation is not found, then the page table 220 needs to be consulted to find the address translation. This page table lookup can take a lot of time. For example, in a non-virtualized x86 system, up to four memory accesses may be required to retrieve the desired translation. In a virtualized system with nested page table lookups, the number of memory accesses can become 24, which is very expensive.

In a heterogeneous processing device 200 where the CPU and GPU share the same page table, it is very likely that the translation needed by the CPU will be found in the GPU hierarchy, or vice versa. In the case of computer programs that share data between two CPUs and GPUs, the likelihood that the hierarchy of one processing unit maintains the transformations required by the other increases.

In order to avoid as much as possible the need to wait for the result of the query of the page table 220, the processing device 200 is configured to probe 270 the GPU TLB 250 for an address translation requested by one of the CPUs 241, 242 of the CPU group 240 when a condition occurs, so The situation described is that the requested address translation was not found in the CPUTLB hierarchy 230 . The data processing apparatus 200 is additionally configured to perform a lookup of the page table 220 for the requested address translation when a condition arises that the requested address translation is not found in the probe 270 of the GPU TLB 250 . As an alternative embodiment, the data processing apparatus 200 may be configured to initiate the lookup of the page table 220 for the requested address translation at the same time as the probing 270 of the GPUTLB 250.

In one embodiment, the data processing apparatus 200 is also configured to probe 272 the CPUTLB hierarchy 230 for an address translation requested by one of the GPUs 261, 262 when a condition occurs that is not present in the GPU TLB 250 Address translation requested by GPU 26I, 262 is found. In this case, the data processing apparatus 200 may be configured to perform a lookup of the page table 220 for an address translation requested by the GPU 261, 262 when a condition occurs, which is a probe 272 at the CPU TLB hierarchy 230 The address translation requested by the GPU 261, 262 was not found in . Alternatively, the data processing apparatus 200 may be configured to start a lookup of the page table for an address translation requested by the GPU 261 , 262 at the same time as the probing 272 of the CPU TLB hierarchy 230 .

In a canonical case, the CPU 241, 242 may perform some work on some area of the memory 210 that brings translation of addresses in this area into the TLB hierarchy 230 of the CPU 241, 242. The CPU 241, 242 may also offload some work on this memory region to one or more of the GPUs 261, 262 for execution. The GPU 261, 262 then requires proper address translation in order to access the memory correctly. If a specific address translation for GPU 261, 262 work is not found in the GPU TLB 250, it is likely to be found in the CPU TLB 230 and specifically by probing the CPU TLB hierarchy 230 in a manner that The same way a CPU seeks an address to assign work to a GPU.

For example, CPU 242 may distribute work to GPU 261. If the GPU 261 requests an address translation for this work but does not find it in the GPU TLB 250, then the GPU 261 will probe 272 the CPU TLB 230 for the requested address translation. In this case, the probe 272 will search the first level TLB 232 associated with the CPU 242 and then the second level TLB 280 to find the address translation. If this probe does not result in an address translation, then the GPU waits for the result of a page table lookup for the requested address translation.

In the example processing device 200 that includes groups of CPUs and GPUs, the CPU TLB hierarchy 230 operates in the context of a memory management unit (MMU), and the GPU TLB 250 operates in the context of an input/output memory management unit (IOMMU) that performs page table lookups. operate in the environment. In this environment, when a GPU's translation request fails within the GPU TLB, the IOMMU can be configured to send a probe message 272 including both the requested virtual address and address space ID (ASID) to the CPU MMU to request the required conversion. In an example apparatus 200 with multiple CPUs, the probe may include the id of the CPU that initiated the task for which the address translation request was made to direct the probe 272 to this specific CPU thereby saving probe bandwidth. If the probe is successful, then the CPU MMU can feed the translation back to the IOMMU (much faster than the IOMMU can perform a full page table lookup), thereby satisfying the GPU's address translation request.

An alternative implementation is to probe the 272CPU MMU directly before making a request to the IOMMU for a page table lookup. If the CPU MMU returns switch, then the GPU does not start IOMMU interaction. In this case, if the CPU MMU also does not include translation, then an IOMMU request is generated.

Referring to Figure 3, an additional embodiment is shown. In FIG. 3 , an example data processing apparatus 300 has a shared memory 310 including a page table 320 . The processing arrangement 300 includes a TLB hierarchy 330 configured to store selected address translations for the page tables 320 of the group 340 of processing units 341 , 342 . TLB hierarchy 330 is a multi-level hierarchy that includes a first-level TLB 231, 232 associated with each processing unit 341, 342 of group 340, and a second-level TLB 280 associated with each of the first-level TLBs 231, 232.

Variations in the configuration of TLB hierarchy 330 and/or group 340 will be apparent to those skilled in the art. For example, where additional processing units are included in group 340, TLB hierarchy 330 may include additional first-level TLBs respectively associated with each additional processing unit and second-level TLB 380 indicated in the phantom. Additionally, TLB hierarchy 330 may include more than two levels.

In operation, selected address translations for page tables 320 are stored in TLB hierarchy 330 for group 340 of processing units 341, 342, with some selected address translations for page tables 320 stored in level one TLB for processing unit 341 331, while some selected address translations for the page table 320 are stored in the level one TLB 332 for the processing unit 342. In connection with data processing, the processing units 341, 342 will first look for the required address translation in their respective first level TLB 331, 332 and then in the second level TLB 380.

If the required address translation is found, then the page table 320 need not be consulted. If the desired address translation is not found, then page table 320 needs to be consulted to find the address translation.

In order to avoid as much as possible the need to wait for the results of page table lookups, the processing device 300 is configured to probe 370 the level 1 TLB 332 for an address translation requested by the processing unit 341 when a condition 341 The requested address translation was not found in the associated first-level TLB 331. The data processing apparatus 300 is additionally configured to perform a lookup of the page table 320 for a requested address translation when a condition arises that the requested address translation is not found in the probe 370 of the level one TLB 331. As an alternative embodiment, the data processing apparatus 300 may be configured to initiate the lookup of the page table 320 for the requested address translation concurrently with the probing 370 of the level one TLB 332.

In one embodiment, the data processing apparatus 300 is also configured to probe 372 the level 1 TLB 331 for an address translation requested by the processing unit 342 when a condition occurs in a The requested address translation was not found in level TLB 332. The data processing apparatus 300 is additionally configured to perform a lookup of the page table 320 for a requested address translation when a condition arises that the requested address translation is not found in the probe 372 of the level one TLB 332. As an alternative embodiment, the data processing apparatus 300 may be configured to start the lookup of the page table 320 for the requested address translation at the same time as the detection 372 of the level one TLB 331.

The processing units 341, 342 may be of any type, like for example: a central processing unit (CPU), a graphics processing unit (GPU) or an accelerated processing unit (APU). The embodiment of FIG. 3 is also applicable within the groups shown with respect to FIG. 1 to provide additional probes before or while starting the page table lookup. The processing device 300 may comprise more than two processing units sharing memory and respective TLB hierarchies. In this case, any processing unit's translation request that cannot be fulfilled with reference to the level 1 TLB associated with that processing unit may cause all or a subset of another level 1 TLB to be probed for the requested address translation. In one embodiment, page table lookups may be avoided if a hit is encountered in any probed level 1 TLB. Alternatively, the probe can be issued at the same time the page table lookup is started. In this case, if a translation hit is returned by any query device, the page table query is aborted or its response is ignored.

It should be understood that the methods described herein may be implemented in any multiprocessor device employing shared memory, and that many variations are possible based on the disclosure herein. Although features and elements have been described above in particular combinations, each feature or element can be used alone without the other features and elements or in various combinations with or without other features and elements. A feature or element.

The provided methods can be implemented in a general purpose computer, processor or processor core. Suitable processors include, by way of example: a general purpose processor, a special purpose processor, a conventional processor, a digital signal processor (DSP), multiple microprocessors, one or more microprocessors associated with a DSP core, a control microcontrollers, application specific integrated circuits (ASICs), field programmable gate array (FPGA) circuits, any other type of integrated circuit (IC) and/or state machine. These processors may be manufactured by configuring a manufacturing process using the results of processing Hardware Description Language (HDL) instructions and other intermediate data including netlists, which instructions can be stored on a computer-readable medium. The result of such processing may be a photomask work that is subsequently used in a semiconductor fabrication process to fabricate a processor implementing one or more aspects of the disclosed embodiments.

The methods or flowcharts provided herein can be implemented in a computer program, software or firmware incorporated into a non-transitory computer-readable storage medium for execution by a general-purpose computer or processor. Examples of non-transitory computer readable storage media include read only memory (ROM), random access memory (RAM), registers, cache memory, semiconductor memory devices, magnetic media such as internal hard disks and removable disks, magneto-optical media , and optical media such as CD-ROM discs and digital versatile discs (DVD).

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Claims (46)

1. A data processing device comprising: first processing unit; second processing unit; a page table of a memory shared by the first and second processing units; a first translation lookaside buffer (TLB) hierarchy configured to store select address translations for the page tables used by the first processing unit; a second TLB hierarchy configured to store select address translations of the page tables used by the second processing unit; and The processing means is configured to probe the second TLB hierarchy for an address translation requested by the first processing unit upon occurrence of a condition that is not found in the first TLB hierarchy The address translation for the request. 2. The data processing apparatus of claim 1 , configured to perform a lookup of the page table for the requested address translation upon occurrence of a condition that is in the second TLB hierarchy The requested address translation was not found in the probe for . 3. The data processing apparatus of claim 1, configured to initiate a lookup of the page table for the requested address translation concurrently with the probing of the second TLB hierarchy. 4. The data processing apparatus of claim 1 , configured to probe the first TLB hierarchy for an address translation requested by the second processing unit when a condition occurs, the condition being The address translation requested by the second processing unit is not found in the second TLB hierarchy. 5. The data processing apparatus according to claim 4, configured to perform a lookup of the page table for the address translation requested by the second processing unit when a condition occurs, the condition being The address translation requested by the second processing unit is not found in the probing of the first TLB hierarchy. 6. The data processing apparatus of claim 4, configured to start said page table for said address translation requested by said second processing unit concurrently with said probing of said first TLB hierarchy query. 7. The data processing apparatus as claimed in claim 1, wherein: The first processing unit is a central processing unit (CPU), a graphics processing unit (GPU), or an accelerated processing unit (APU); and The second processing unit is CPU, GPU or APU. 8. The data processing apparatus of claim 1, wherein the first processing unit is a CPU and the second processing unit is a GPU. 9. The data processing device as claimed in claim 1, further comprising a plurality of first processing units including the first processing unit, wherein: The first TLB hierarchy is configured to store select address translations of the page tables used by the first processing unit. 10. The data processing apparatus according to claim 9, wherein each of the first processing units is a central processing unit (CPU), a graphics processing unit (GPU) or an accelerated processing unit (APU). 11. The data processing apparatus as claimed in claim 10, wherein all of said first processing units are CPUs; and The first TLB hierarchy includes a separate first-level TLB associated with each CPU to store select address translations for the page tables used by that CPU; and with the first-level TLB the associated second-level TLB; and probing the status of the second TLB hierarchy for the address translation requested by the first processing unit is: a search in the first level TLB and the second level TLB associated with the first processing unit The address translation requested by the first processing element was not found in . 12. The data processing apparatus as claimed in claim 10, wherein all of said first processing units are GPUs; and said first TLB hierarchy comprising a single TLB associated with all of said GPUs to store selected address translations of said page tables used by said GPUs; and A condition of probing the second TLB hierarchy for the address translation requested by the first processing unit is that the address translation requested by the first processing unit was not found in a search of the single TLB. 13. The data processing device as claimed in claim 1, further comprising a plurality of second processing units comprising said second processing unit, wherein: The second TLB hierarchy includes a separate first-level TLB associated with each of the plurality of second processing units to store the page tables used by that second processing unit and a second-level TLB associated with said first-level TLB; and The processing means is configured to probe the first processing unit for the address translation requested by the first processing unit by searching the first level TLB and the second level TLB associated with the second processing unit. and two TLB hierarchies to find the address translation requested by the first processing unit. 14. The data processing device as claimed in claim 4, further comprising a plurality of first processing units including the first processing unit and a plurality of second processing units including the second processing unit, wherein: the first TLB hierarchy configured to store select address translations of the page tables used by the first processing unit; and The second TLB hierarchy is configured to store select address translations of the page tables used by the second processing unit. 15. The data processing apparatus as claimed in claim 14, wherein: Each of said first processing units is a central processing unit (CPU), a graphics processing unit (GPU), or an accelerated processing unit (APU); and Each of the second processing units is a CPU, GPU or APU. 16. A data processing apparatus as claimed in claim 15, wherein: all of said first processing units are CPUs; The first TLB hierarchy includes a separate first-level TLB associated with each CPU to store select address translations for the page tables used by that CPU; and with the first-level TLB the associated second-level TLB; probing the status of the second TLB hierarchy for the address translation requested by the first processing unit is: a search in the first level TLB and the second level TLB associated with the first processing unit The address translation requested by the first processing element is not found in ; all of said second processing units are GPUs; said second TLB hierarchy comprising a single TLB associated with all of said GPUs to store select addresses of said page tables used by said GPUs; probing the first TLB hierarchy for the address translation requested by the second processing unit is: the address translation requested by the second processing unit was not found in a search of the single TLB; as well as The processing means is configured to detect the address translation requested by the second processing unit for the address translation requested by the second processing unit by searching the first level TLB and the second level TLB associated with the selected first processing unit. A first TLB hierarchy to find the address translation requested by the second processing unit. 17. The data processing apparatus of claim 16 configured to: The lookup of the page table is made for the address translation requested by the first processing unit upon the condition that the address translation requested by the second TLB hierarchy is not found in the probe of the second TLB hierarchy said address translation requested by the first processing unit; and The lookup of the page table is made for the address translation requested by the second processing unit upon the condition that the address translation requested by the first TLB hierarchy is not found in the probe of the first TLB hierarchy The address translation requested by the second processing unit. 18. The data processing apparatus of claim 16 configured to: initiating a lookup of the page table for the address translation requested by the first processing unit concurrently with the probing of the second TLB hierarchy; and A lookup of the page table is initiated concurrently with the probing of the first TLB hierarchy for the address translation requested by the second processing unit. 19. A data processing device comprising: first processing unit; second processing unit; a page table of a memory shared by the first and second processing units; a first translation lookaside buffer (TLB) configured to store select address translations for the page table used by the first processing unit; a second TLB configured to store select address translations of the page tables used by the second processing unit; and The processing means is configured to probe the second TLB for an address translation requested by the first processing unit when a condition occurs that the requested address is not found in the first TLB convert. 20. The data processing apparatus according to claim 19 , configured to perform a lookup of the page table for the requested address translation when a condition occurs, the condition being all The requested address translation was not found in the probe. 21. The data processing apparatus of claim 19, configured to initiate a lookup of the page table for the requested address translation concurrently with the probing of the second TLB. 22. The data processing device as claimed in claim 19, further comprising a plurality of first processing units including the first processing unit and a plurality of second processing units including the second processing unit, wherein: the first TLB is part of a first TLB hierarchy configured to store select address translations of the page tables used by the first processing unit; and The second TLB is part of a second TLB hierarchy configured to store select address translations of the page tables used by the second processing unit. 23. The data processing apparatus as claimed in claim 19, further comprising a second-level TLB, wherein: the first and second TLBs include a first level of a TLB hierarchy configured to store select address translations of the page tables used by the first and second processing units; the second level TLB comprises a second level of the TLB hierarchy; and The data processing apparatus is configured to perform a lookup of the page table for the requested address translation when a condition occurs, the condition being in the probing of the second TLB or the secondary TLB The requested address translation was not found. 24. The data processing apparatus as claimed in claim 19, further comprising a second-level TLB, wherein: the first and second TLBs include a first level of a TLB hierarchy configured to store select address translations of the page tables used by the first and second processing units; the second level TLB comprises a second level of the TLB hierarchy; and The data processing apparatus is configured to initiate a lookup of the page table for the requested address translation at the same time as the probing of the second TLB when a condition occurs, the condition being that at the second level The requested address translation was not found in the TLB. 25. A data processing method comprising: There is provided a first translation lookaside buffer (TLB) hierarchy configured to store selected address translations for page tables used by the first processing unit; and a second TLB hierarchy configured to store selected address translations for use by the second processing unit Select address translation for said page table; and The second TLB hierarchy is probed for an address translation requested by the first processing unit upon a condition that the requested address translation is not found in the first TLB hierarchy. 26. The data processing method as claimed in claim 25, further comprising performing a lookup of the page table for the requested address translation when a condition occurs, the condition is in the second TLB hierarchy The requested address translation was not found in the probe. 27. The data processing method of claim 25, further comprising starting a lookup of the page table for the requested address translation concurrently with the probing of the second TLB hierarchy. 28. The data processing method according to claim 25, further comprising probing the first TLB hierarchy for an address translation requested by the second processing unit when a condition occurs, the condition being in the The address translation requested by the second processing unit is not found in the second TLB hierarchy. 29. The data processing method as claimed in claim 28, further comprising performing a lookup of the page table for the address translation requested by the second processing unit when a condition occurs, the condition is in the The address translation requested by the second processing unit is not found in the probing of the first TLB hierarchy. 30. The data processing method of claim 28, further comprising starting said page table translation for said address translation requested by said second processing unit concurrently with said probing of said first TLB hierarchy Inquire. 31. The data processing method as claimed in claim 25, wherein said first processing unit is a CPU among a plurality of central processing units (CPUs), and said first TLB hierarchy comprises a separate first-level TLB, said a separate level-1 TLB associated with each CPU to store select address translations for said page tables used by that CPU; and a level-2 TLB associated with said level-1 TLB, wherein when a condition occurs for The address translation requested by the first processing unit probes the second TLB hierarchy, the condition is in a search of the first level TLB and the second level TLB associated with the first processing unit The address translation requested by the first processing unit was not found. 32. The data processing method of claim 25, wherein the first processing unit is a GPU in a plurality of graphics processing units (GPUs), and the first TLB hierarchy includes to store a single TLB of selected address translations of the page tables used by the GPU, wherein probing the condition of the second TLB hierarchy for the address translation requested by the first processing unit is: at The address translation requested by the first processing unit is not found in a search of the single TLB. 33. The data processing method according to claim 25, wherein the second processing unit is one of a plurality of second processing units, and the second TLB hierarchy comprises a single-level TLB, the single-level a TLB associated with each of said plurality of second processing units to store select address translations of said page tables used by that second processing unit; and a second level TLB associated with said first level TLB, which Also includes: probing the second TLB hierarchy for the address translation requested by the first processing unit by searching the first level TLB and the second level TLB associated with the selected second processing unit, so that The address translation requested by the first processing unit is found. 34. The data processing method as claimed in claim 28, wherein said first processing unit is a CPU among a plurality of central processing units (CPUs), and said first TLB hierarchy comprises a separate first-level TLB, said a separate level-1 TLB associated with each CPU to store select address translations of said page tables used by that CPU; and a level-2 TLB associated with said level-1 TLB; and wherein said second processing unit is GPUs in a plurality of graphics processing units (GPUs), and the second TLB hierarchy comprises a single TLB associated with all of the GPUs to store selected address translations of the page tables used by the GPUs, wherein : probing the status of the second TLB hierarchy for the address translation requested by the first processing unit is: a search in the first level TLB and the second level TLB associated with the first processing unit The address translation requested by the first processing element is not found in ; and A condition of probing the first TLB hierarchy for the address translation requested by the second processing unit is that the address translation requested by the second processing unit was not found in a search of the single TLB. 35. The data processing method as claimed in claim 34, further comprising: performing a lookup of the page table for the address translation requested by the first processing unit upon a condition that the address translation requested by the first processing unit is not found in the second TLB hierarchy the address translation requested; and The lookup of the page table is made for the address translation requested by the second processing unit upon the condition that the address translation requested by the first TLB hierarchy is not found in the probe of the first TLB hierarchy The address translation requested by the second processing unit. 36. The data processing method as claimed in claim 34, further comprising: initiating a lookup of the page table for the address translation requested by the first processing unit concurrently with the probing of the second TLB hierarchy; and A lookup of the page table is initiated concurrently with the probing of the first TLB hierarchy for the address translation requested by the second processing unit. 37. A data processing method comprising: providing a first translation lookaside buffer (TLB) configured to store selected address translations for a page table used by the first processing unit; and a second TLB configured to store the page used by the second processing unit the selection address translation of the table; and The second TLB is probed for an address translation requested by the first processing unit upon a condition that the requested address translation is not found in the first TLB. 38. The data processing method according to claim 37, further comprising performing a lookup of the page table for the requested address translation when a situation occurs, the situation being during detection of the second TLB The requested address translation was not found. 39. The data processing method of claim 37, further comprising starting a lookup of the page table for the requested address translation simultaneously with the probing of the second TLB. 40. The data processing method of claim 37, wherein the first TLB is part of a first TLB hierarchy configured to store selected address translations of the page tables used by a plurality of first processing units, and said second TLB is part of a second TLB hierarchy configured to store selected address translations of said page tables used by a plurality of second processing units, wherein: Probing a condition of the second TLB for an address translation requested by the first processing unit is that the requested address translation is not found in the first TLB hierarchy. 41. The data processing method according to claim 37, wherein the first and second TLBs comprise a TLB hierarchy configured to store selected address translations of the page tables used by the first and second processing units The first-level, and second-level TLBs include the second level of the TLB hierarchy, which further includes: Performing the query of the page table for the requested address translation when a condition occurs, the condition is that the requested address translation is not found in the detection of the second TLB or the secondary TLB. . 42. The data processing method according to claim 37, wherein the first and second TLBs comprise a TLB hierarchy configured to store selected address translations of the page tables used by the first and second processing units The first-level, and second-level TLBs include the second level of the TLB hierarchy, which further includes: Initiating the lookup of the page table for the requested address translation concurrently with the probing of the second TLB when a condition occurs that the requested one is not found in the secondary TLB address translation. 43. A non-transitory computer-readable storage medium storing a set of instructions for execution by a general-purpose computer to facilitate the manufacture of integrated circuits, the non-transitory computer-readable storage medium comprising: first processing unit; second processing unit; a page table of a memory shared by the first and second processing units; a first translation lookaside buffer (TLB) hierarchy configured to store select address translations for the page tables used by the first processing unit; a second TLB hierarchy configured to store select address translations of the page tables used by the second processing unit; and The processing means is configured to probe the second TLB hierarchy for an address translation requested by the first processing unit when a condition occurs that all address translation for the above request. 44. The non-transitory computer readable storage medium of claim 43, wherein the instructions are hardware description language (HDL) instructions for device manufacture. 45. A non-transitory computer-readable storage medium storing a set of instructions for execution by a general-purpose computer to facilitate the manufacture of integrated circuits, the non-transitory computer-readable storage medium comprising: first processing unit; second processing unit; a page table of a memory shared by the first and second processing units; a first translation lookaside buffer (TLB) configured to store select address translations for the page table used by the first processing unit; a second TLB configured to store select address translations of the page tables used by the second processing unit; and The processing means is configured to probe the second TLB for an address translation requested by the first processing unit when a condition occurs that the requested address is not found in the first TLB convert. 46. The computer-readable storage medium of claim 45, wherein the instructions are hardware description language (HDL) instructions for manufacturing a device.