CN104934009B - Shift register cell and driving method, shift-register circuit and display device - Google Patents

Abstract

The embodiment of the present invention discloses a shift register unit, a driving method, a shift register circuit and a display device, which relate to the field of display manufacturing and avoid the problem of simultaneous output of multiple rows before the first frame is turned on. The shift register unit includes: an input module, a reset module, a control module, a first output control module, a second output control module and a feedback module. Embodiments of the present invention are used in display manufacturing.

Description

Shift register unit and driving method, shift register circuit and display device

technical field

The invention relates to the field of display manufacturing, in particular to a shift register unit, a driving method, a shift register circuit and a display device.

Background technique

In recent years, the development of liquid crystal displays has shown a trend of high integration and low cost. One of the very important technologies is the mass production of GOA (full name in English: Gate Driver on Array, Chinese: row drive on array substrate). The gate switch circuit is integrated on the array substrate of the liquid crystal display panel by using GOA technology, so that the part of the gate drive integrated circuit can be saved, so as to reduce the product cost in terms of material cost and manufacturing process. The gate switch circuit integrated on the array substrate using the GOA technology is also called a GOA circuit or a shift register circuit.

Wherein, the shift register circuit includes several shift register units, and each shift register unit corresponds to a gate line, and specifically, the output end of each shift register unit is connected to a gate line; and the output end of a shift register unit Connect to the input of the next shift register cell. Each shift register unit in the traditional shift register circuit is a 12TFT (English full name: Thin Film Transistor, Chinese: Thin Film Field Effect Transistor) 1Cap (Chinese: Capacitance) structure. TFT characteristics may change, resulting in the problem of simultaneous output of multiple lines before the first frame is turned on.

Contents of the invention

Embodiments of the present invention provide a shift register unit, a driving method, a shift register circuit, and a display device, which avoid the problem of simultaneous output of multiple lines before the first frame is turned on.

In order to achieve the above object, embodiments of the present invention adopt the following technical solutions:

In one aspect, a shift register unit is provided, including: a first input unit, a second input unit, a pull-up unit, a pull-down unit, a reset unit, an output unit, and a reset unit;

Wherein, the first input unit is connected to the first frame start signal terminal and the second node, and is used to input the signal of the first frame start signal terminal to the second node;

The second input unit is connected to the first input terminal, the second clock signal terminal and the first node, and is used to input the signal of the first input terminal to the the first node;

The pull-up unit is connected to the second clock signal terminal, the third node and the second node, and is used to input the level of the second clock signal terminal to the first clock signal terminal under the control of the second clock signal terminal. Second node or third node;

The pull-down unit is connected to the second clock signal terminal, the first node, the second node, the third node, the first level terminal and the output terminal, and is used for controlling the second clock signal terminal outputting the signal of the first level terminal at the output terminal; outputting the signal of the first level terminal at the first node and the second node under the control of the first node; outputting the signal of the first level end at the first node and the output end under the control of the second node;

The reset unit is connected to the reset signal terminal, the first node, the output terminal and the first level terminal, and is used to transfer the signal of the first level terminal to the first node under the control of the reset signal terminal. and the output output;

The output unit is connected to the first node, the first clock signal terminal and the output terminal; used for storing the level signal of the first node, and under the control of the first node, the first The signal at the clock signal terminal is output at the output terminal;

The reset unit is connected to the second frame start signal terminal, the first level terminal and the output terminal, and is used to reset the signal of the first level terminal under the control of the second frame start signal terminal to The output terminal outputs.

Optionally, the first input unit includes a seventh transistor;

The gate of the seventh transistor is connected to the first frame start signal terminal, the first terminal of the seventh transistor is connected to the gate of the seventh transistor, and the second terminal of the seventh transistor is connected to the second node.

Optionally, the second input unit includes: a first transistor and a thirteenth transistor;

The gate of the first transistor is connected to the first input terminal, the first terminal of the first transistor is connected to the gate of the first transistor, and the second terminal of the first transistor is connected to the first node ;

The gate of the thirteenth transistor is connected to the second clock signal terminal, the first terminal of the thirteenth transistor is connected to the first input terminal, and the second terminal of the thirteenth transistor is connected to the first a node.

Optionally, the pull-up unit includes: a fifth transistor and a ninth transistor;

The gate of the fifth transistor is connected to the third node, the first terminal of the fifth transistor is connected to the second clock signal terminal, and the second terminal of the fifth transistor is connected to the second node;

The gate of the ninth transistor is connected to the second clock signal terminal, the first terminal of the ninth transistor is connected to the second clock signal terminal, and the second terminal of the ninth transistor is connected to the third node .

Optionally, the pull-down unit includes: a sixth transistor, an eighth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor;

The gate of the sixth transistor is connected to the first node, the first terminal of the sixth transistor is connected to the second node, and the second terminal of the sixth transistor is connected to the first level terminal;

The gate of the eighth transistor is connected to the first node, the first end of the eighth transistor is connected to the third node, and the second end of the eighth transistor is connected to the first level end;

The gate of the tenth transistor is connected to the second node, the first terminal of the tenth transistor is connected to the first node, and the second terminal of the tenth transistor is connected to the first level terminal;

The gate of the eleventh transistor is connected to the second node, the first end of the eleventh transistor is connected to the output end, and the second end of the eleventh transistor is connected to the first level end;

The gate of the twelfth transistor is connected to the second clock signal terminal, the first terminal of the twelfth transistor is connected to the output terminal, and the second terminal of the twelfth transistor is connected to the first terminal. flat end.

Optionally, the reset unit includes a second transistor and a fourth transistor;

The gate of the second transistor is connected to the reset signal terminal, the first terminal of the second transistor is connected to the first node, and the second terminal of the second transistor is connected to the first level terminal;

The gate of the fourth transistor is connected to the reset signal terminal, the first terminal of the fourth transistor is connected to the output terminal, and the second terminal of the fourth transistor is connected to the first level terminal.

Optionally, the output unit includes a first capacitor and a third transistor;

The first pole of the first capacitor is connected to the first node, and the second pole of the first capacitor is connected to the output terminal;

A gate of the third transistor is connected to the first node, a first terminal of the third transistor is connected to the first clock signal terminal, and a second terminal of the third transistor is connected to the output terminal.

Optionally, the reset unit includes: a fourteenth transistor;

The gate of the fourteenth transistor is connected to the second frame start signal end, the first end of the fourteenth transistor is connected to the output end, and the second end of the fourteenth transistor is connected to the first One level terminal.

Optionally, each transistor is the same type of transistor.

In one aspect, a shift register circuit is provided, comprising: at least two stages of cascaded shift register units, wherein the shift register unit of the first stage is any one of the above-mentioned shift register units.

In one aspect, a display device is provided, including: the above-mentioned shift register circuit.

On the one hand, a driving method of a shift register unit is provided, including:

In the first stage, the reset unit aligns the level of the output end with the first level end under the control of the second frame start signal end; the pull-down unit aligns the level of the first node with the output end under the control of the second node aligned with the first level terminal;

In the second stage, the first input unit inputs the signal of the first frame start signal terminal into the second node under the control of the first frame start signal terminal; the pull-down unit inputs the signal of the output terminal under the control of the second clock signal terminal The level is aligned with the first level terminal; the second input unit inputs the signal of the first input terminal to the first node under the control of the first input terminal and the second clock signal terminal; in the second stage Under the control of the second frame start signal terminal during the first preset period, the reset unit aligns the level of the output terminal with the first level terminal; the output unit stores the voltage of the first node flat signal;

In the third stage, the output unit outputs the signal of the first clock signal terminal at the output terminal under the control of the first node; the pull-down unit outputs the signal of the first node and the second clock signal terminal under the control of the first node The level of the two nodes is aligned with the first level terminal;

In the fourth stage, the reset unit equalizes the levels of the first node and the output terminal with the first level terminal under the control of the reset signal terminal.

The shift register unit, the driving method, the shift register circuit and the display device provided by the embodiments of the present invention are controlled by the first input unit, the second input unit, the pull-up unit, the pull-down unit, the reset unit, the output unit and the reset unit Outputting the driving signal to the gate line, compared with the prior art, the reset unit in the embodiment of the present invention can output the signal of the first level terminal at the output terminal under the control of the second frame start signal terminal in the initial stage, thereby realizing The gate line output drive signal is reset before the first frame is turned on, which avoids the problem of simultaneous output of multiple lines before the first frame is turned on.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 is a schematic structural diagram of a shift register unit provided by an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a shift register unit provided by another embodiment of the present invention;

FIG. 3 is a schematic flowchart of a driving method for a shift register unit provided by an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of a shift register circuit provided by an embodiment of the present invention;

FIG. 5 is a schematic diagram of timing signal states of each signal terminal of the shift register unit provided by an embodiment of the present invention.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

The transistors used in all the embodiments of the present invention can be thin film transistors or field effect transistors or other devices with the same characteristics, and the transistors used in the embodiments of the present invention are mainly switching transistors according to their functions in circuits. Since the source and drain of the switching transistor used here are symmetrical, the source and drain are interchangeable. In the embodiment of the present invention, in order to distinguish the two poles of the transistor except the gate, the source is called the first terminal, and the drain is called the second terminal. According to the form in the accompanying drawings, it is stipulated that the middle terminal of the transistor is the gate, the signal input terminal is the source terminal, and the signal output terminal is the drain terminal. In addition, the switching transistors used in the embodiments of the present invention include P-type switching transistors and N-type switching transistors, wherein the P-type switching transistors are turned on when the gate is at a low level, and are turned off when the gate is at a high level, and the N-type switching transistors To turn on when the gate is high and off when the gate is low.

Referring to Fig. 1, an embodiment of the present invention provides a shift register unit, including: a first input unit 11, a second input unit 12, a pull-up unit 13, a pull-down unit 14, a reset unit 15, an output unit 16 and reset unit 17;

Wherein, the first input unit 11 is connected to the first frame start signal terminal STV1 and the second node PD, and is used for inputting the signal of the first frame start signal terminal STV1 into the second node PD;

The second input unit 12 is connected to the first input terminal INPUT1, the second clock signal terminal CLKB and the first node PU, and is used to control the first input terminal INPUT1 and the second clock signal terminal CLKB. The signal is input to the first node PU;

The pull-up unit 13 is connected to the second clock signal terminal CLKB, the third node PD_CN and the second node PD, and is used to input the level of the second clock signal terminal CLKB into the second node under the control of the second clock signal terminal CLKB PD or third node PD_CN;

The pull-down unit 14 is connected to the second clock signal terminal CLKB, the first node PU, the second node PD, the third node PD_CN, the first level terminal V1 and the output terminal OUT, and is used to turn the second clock signal terminal CLKB under the control of the second clock signal terminal CLKB. The signal of a level terminal V1 is output at the output terminal OUT; under the control of the first node PU, the signal of the first level terminal V1 is output at the first node PU and the second node PD; The signal of a level terminal V1 is output at the first node PU and the output terminal OUT;

The reset unit 15 is connected to the reset signal terminal RESET, the first node PU, the output terminal OUT and the first level terminal V1, and is used to transfer the signal of the first level terminal V1 to the first node PU and the output terminal V1 under the control of the reset signal terminal RESET. OUT output;

The output unit 16 is connected to the first node PU, the first clock signal terminal CLK and the output terminal OUT; it is used to store the level signal of the first node PU, and convert the signal of the first clock signal terminal CLK under the control of the first node PU to Output at the output terminal OUT;

The reset unit 17 is connected to the second frame start signal terminal STV2, the first level terminal V1 and the output terminal OUT, and is used to transfer the signal of the first level terminal V1 to the output terminal OUT under the control of the second frame start signal terminal STV2. output.

The shift register unit provided by the embodiment of the present invention controls the output of the drive signal to the gate line through the first input unit, the second input unit, the pull-up unit, the pull-down unit, the reset unit, the output unit and the reset unit. In the embodiment of the present invention, the reset unit can output the signal of the first level terminal at the output terminal under the control of the second frame start signal terminal in the initial stage, so as to realize the output drive of the gate line before the first frame is turned on The signal is reset to avoid the problem of simultaneous output of multiple lines before the first frame is turned on.

Referring to FIG. 2, an embodiment of the present invention provides a shift register unit, wherein the first input unit 11 includes a seventh transistor M7;

The gate of the seventh transistor M7 is connected to the first frame start signal terminal STV1 , the first terminal of the seventh transistor M7 is connected to the gate of the seventh transistor M7 , and the second terminal of the seventh transistor M7 is connected to the second node PD.

The second input unit 12 includes: a first transistor M1 and a thirteenth transistor M13;

The gate of the first transistor M1 is connected to the first input terminal INPUT1, the first end of the first transistor M1 is connected to the gate of the first transistor M1, and the second end of the first transistor M1 is connected to the first node PU;

The gate of the thirteenth transistor M13 is connected to the second clock signal terminal CLKB, the first terminal of the thirteenth transistor M13 is connected to the first input terminal INPUT1 , and the second terminal of the thirteenth transistor M13 is connected to the first node PU.

The pull-up unit 13 includes: a fifth transistor M5 and a ninth transistor M9;

The gate of the fifth transistor M5 is connected to the third node PD_CN, the first end of the fifth transistor M5 is connected to the second clock signal terminal CLKB, and the second end of the fifth transistor M5 is connected to the second node PD;

The gate of the ninth transistor M9 is connected to the second clock signal terminal CLKB, the first terminal of the ninth transistor M9 is connected to the second clock signal terminal CLKB, and the second terminal of the ninth transistor M9 is connected to the third node PD_CN.

The pull-down unit 14 includes: a sixth transistor M6, an eighth transistor M8, a tenth transistor M10, an eleventh transistor M11 and a twelfth transistor M12;

The gate of the sixth transistor M6 is connected to the first node PU, the first terminal of the sixth transistor M6 is connected to the second node PD, and the second terminal of the sixth transistor M6 is connected to the first level terminal V1;

The gate of the eighth transistor M8 is connected to the first node PU, the first end of the eighth transistor M8 is connected to the third node PD_CN, and the second end of the eighth transistor M8 is connected to the first level terminal V1;

The gate of the tenth transistor M10 is connected to the second node PD, the first terminal of the tenth transistor M10 is connected to the first node PU, and the second terminal of the tenth transistor M10 is connected to the first level terminal V1;

The gate of the eleventh transistor M11 is connected to the second node PD, the first end of the eleventh transistor M11 is connected to the output terminal OUT, and the second end of the eleventh transistor M11 is connected to the first level terminal V1;

The gate of the twelfth transistor M12 is connected to the second clock signal terminal CLKB, the first terminal of the twelfth transistor M12 is connected to the output terminal OUT, and the second terminal of the twelfth transistor M12 is connected to the first level terminal V1.

The reset unit 15 includes a second transistor M2 and a fourth transistor M4;

The gate of the second transistor M2 is connected to the reset signal terminal RESET, the first terminal of the second transistor M2 is connected to the first node PU, and the second terminal of the second transistor M2 is connected to the first level terminal V1;

The gate of the fourth transistor M4 is connected to the reset signal terminal RESET, the first terminal of the fourth transistor M4 is connected to the output terminal OUT, and the second terminal of the fourth transistor M4 is connected to the first level terminal V1.

The output unit 16 includes a first capacitor C1 and a third transistor M3;

The first pole of the first capacitor C1 is connected to the first node PU, and the second pole of the first capacitor C1 is connected to the output terminal OUT;

The gate of the third transistor M3 is connected to the first node PU, the first terminal of the third transistor M3 is connected to the first clock signal terminal CLK, and the second terminal of the third transistor M3 is connected to the output terminal OUT.

The reset unit 17 includes: a fourteenth transistor M14;

The gate of the fourteenth transistor M14 is connected to the second frame start signal terminal STV2 , the first terminal of the fourteenth transistor M14 is connected to the output terminal OUT, and the second terminal of the fourteenth transistor M14 is connected to the first level terminal V1 .

Optionally, the transistors shown in FIG. 2 are of the same type, so that the complexity of the manufacturing process can be minimized.

The shift register unit provided by the embodiment of the present invention controls the output of the drive signal to the gate line through the first input unit, the second input unit, the pull-up unit, the pull-down unit, the reset unit, the output unit and the reset unit. In the embodiment of the present invention, the reset unit can output the signal of the first level terminal at the output terminal under the control of the second frame start signal terminal in the initial stage, so as to realize the output drive of the gate line before the first frame is turned on The signal is reset to avoid the problem of simultaneous output of multiple lines before the first frame is turned on.

Embodiments of the present invention provide a driving method applied to the above-mentioned shift register unit, as shown in FIG. 3 , including the following steps:

101. In the first stage, the reset unit aligns the level of the output end with the first level end under the control of the second frame start signal end; the pull-down unit adjusts the level of the first node and the output end under the control of the second node Align with the first level terminal.

102. In the second stage, the first input unit inputs the signal of the first frame start signal terminal to the second node under the control of the first frame start signal terminal; the pull-down unit inputs the signal of the output terminal under the control of the second clock signal terminal The level is aligned with the first level terminal; the second input unit inputs the signal of the first input terminal to the first node under the control of the first input terminal and the second clock signal terminal; it is reset in the first preset period of the second stage The unit aligns the level of the output terminal with the first level terminal under the control of the second frame start signal terminal; the output unit stores the level signal of the first node.

103. In the third stage, the output unit outputs the signal of the first clock signal terminal at the output terminal under the control of the first node; the pull-down unit combines the levels of the first node and the second node with the first The level end is aligned.

104. In the fourth stage, the reset unit equalizes the levels of the first node and the output terminal with the first level terminal under the control of the reset signal terminal.

In the driving method of the shift register unit provided in the embodiment of the present invention, the first input unit, the second input unit, the pull-up unit, the pull-down unit, the reset unit, the output unit and the reset unit are used to control the output of the drive signal to the gate line. Compared with the prior art, in the embodiment of the present invention, the reset unit can output the signal of the first level terminal at the output terminal under the control of the second frame start signal terminal in the initial stage, so as to realize the gate control before the first frame is turned on. The line output drive signal is reset, which avoids the problem of simultaneous output of multiple lines before the first frame is turned on.

A shift register circuit provided by an embodiment of the present invention comprises at least two stages of cascaded shift register units. Specifically: it includes a plurality of shift register units in series, except for the first shift register unit and the last shift register unit, the output of each other shift register unit is connected to the next adjacent shift register The first input terminal of the unit, the signal reset terminal of each shift register unit is connected to the output terminal of the next adjacent shift register unit.

Specifically, the shift register circuit shown in FIG. 4 includes several shift register units, wherein the output terminal OUT1 of the shift register unit SR1 is connected to the first input terminal INPUT1 of the shift register unit SR2 and connected to a gate line OG1, The reset signal terminal RESET1 of the shift register unit SR1 is connected to the output terminal OUT2 of the shift register unit SR2; the output terminal OUT2 of the shift register unit SR2 is connected to the first input terminal INPUT3 of the shift register unit SR3 and connected to a gate line OG2, The reset signal terminal RESET2 of the shift register unit SR2 is connected to the output terminal OUT3 of the shift register unit SR3; other shift register units are linked according to this method, and each shift register unit has a first clock signal terminal CLK, A second clock signal terminal and a first level terminal V1 are input, wherein CLK and CLKB are connected to the system clock signal, and the first level terminal V1 is low level vss or grounded vdd. In this embodiment, the first shift register unit is the shift register unit SR1, and the first input terminal INPUT1 of the shift register unit SR1 is idle, wherein the signal of the first frame start signal terminal STV1 is an activation pulse signal , optionally such as the frame start signal STV. SR1 further includes a second frame start signal terminal STV2, and the signal of the second frame start signal terminal is input earlier than the first frame start signal terminal STV1.

It should be noted that the system clock signal CLOCK is a driving clock signal for two or more shift register units. The shift register unit is connected to the corresponding clock signal as required, for example, the first clock signal terminal CLK of the first shift register unit is connected to the first system clock signal, and the second clock signal terminal CLKB of the first shift register unit is connected to The second system clock signal; the first clock signal terminal CLK of the second shift register unit is connected to the second system clock signal, and the second clock signal terminal CLKB of the second shift register unit is connected to the first system clock signal ; The first clock signal terminal CLK of the third shift register unit is connected to the first system clock signal, and the second clock signal terminal CLKB of the third shift register unit is connected to the second system clock signal; The first clock signal terminal CLK of the register unit is connected to the second system clock signal, and the second clock signal terminal CLKB of the fourth shift register unit is connected to the first system clock signal; after this cycle; or other can make the shift register The way the unit is connected for normal operation.

Wherein, with reference to the timing signal state diagram of each signal terminal shown in FIG. 5, the working principle of the shift register unit provided in the above-mentioned FIG. 2 of the present application is described as follows:

In the first stage, STV1=0, STV2=1, INPUT=0, V1=0, CLK=1, CLKB=0, OUT=0, RESET=0; M14 is turned on, other transistors are turned off, PU=0, PD =0, PD_CN=0. It should be noted that, in the following embodiments, "0" indicates a low level; "1" indicates a high level. In this stage, due to the conduction of M14, the levels of OUT and V1 are aligned, which avoids outputting signals to the gate line of the first row before the start of the first frame.

In the second stage, STV1=1, STV2 jumps from 1 to 0 at the preset time point in the second stage, INPUT=0, V1=0, CLK=0, CLKB=1, OUT=0, RESET=0; At this stage, M13 is turned on to charge the PU node; M7 is turned on to charge the PD node; M3, M5, M6, M8, M9, and M12 are turned on; M1, M2, M4, M10, and M11 are turned off; The first time period is turned on, and the second time period is turned off. Among them, it should be noted that as the first stage shift register unit, since the first input terminal is idle, INPUT=0; as the shift register unit after the second stage, since the first input terminal is connected to the adjacent upper stage shift The output terminal of the bit register unit, so its INPUT=1; at this time, M1 is turned on.

In the third stage, STV1=0, STV2=0, INPUT=0, V1=0, CLK=1, CLKB=0, OUT=1, RESET=0; in this stage, M1, M2, M4, M5, M6, M7 , M8, M9, M10, M11, M12, M13, M14 are off, and M3 is on.

In the fourth stage, STV1=0, STV2=0, INPUT=0, V1=0, CLK=0, CLKB=1, OUT=0, RESET=1; in this stage, M1, M3, M6, M8, M14 are cut off, All other transistors are turned on.

An embodiment of the present invention provides a display device, including any shift register circuit in the above embodiments.

In addition, the display device may be any product or component with a display function, such as electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, and navigator.

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. Should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims (12)

1. A kind of 1. shift register cell, it is characterised in that including：First input block, the second input block, pull-up unit, Drop-down unit, reset unit, output unit and reset cell；

   Wherein, first input block connects the first frame start signal end and section point, for first frame to be originated The signal of signal end inputs the section point；

   Second input block connection first input end, second clock signal end and the first node, for defeated described first Under the control for entering end and second clock signal end, the signal of the first input end is inputted into the first node；

   The pull-up unit connects second clock signal end, the 3rd node and the section point, for described second The level of the second clock signal end is inputted into the section point or the 3rd node under the control of clock signal terminal；

   The drop-down unit connects the second clock signal end, first node, the section point, described Section three Point, the first level terminal and output end, under the control of the second clock signal end by the signal of first level terminal Exported in the output end；Under the control of the first node by the signal of first level terminal in the first node and The section point output；Under the control of the section point by the signal of first level terminal in the first node and The output end output；

   Reset unit connection reset signal end, first node, the output end and first level terminal, for described The signal of first level terminal is exported in the first node and the output end under the control at reset signal end；

   The output unit connects first node, the first clock signal terminal and the output end；For storing described first The level signal of node, and under the control of the first node by the signal of first clock signal terminal in the output end Output；

   The reset cell connects the second frame start signal end, first level terminal and the output end, for being opened in the 1st frame The signal of first level terminal is exported in the output end under the control at the second frame start signal end before opening；Its In, when the shift register cell is as first order shift register cell in shift-register circuit, described first is defeated It is idle to enter end；The shift register cell is as the shift register list after the second level in the shift-register circuit When first, the first input end connects the output end of adjacent upper level shift register cell.
2. 2. shift register cell according to claim 1, it is characterised in that it is brilliant that first input block includes the 7th Body pipe；

   The grid of 7th transistor connects the first frame start signal end, the first end connection of the 7th transistor described the The grid of seven transistors, the second end of the 7th transistor connect the section point.
3. 3. shift register cell according to claim 1, it is characterised in that second input block includes：First Transistor and the 13rd transistor；

   The grid of the first transistor connects the first input end, the first end connection described first of the first transistor The grid of transistor, the second end of the first transistor connect the first node；

   The grid of 13rd transistor connects the second clock signal end, the first end connection of the 13rd transistor The first input end, the second end of the 13rd transistor connect the first node.
4. 4. shift register cell according to claim 1, it is characterised in that the pull-up unit includes：5th crystal Pipe and the 9th transistor；

   The grid of 5th transistor connects the 3rd node, when the first end of the 5th transistor connects described second Clock signal end, the second end of the 5th transistor connect the section point；

   The grid of 9th transistor connects the second clock signal end, described in the first end connection of the 9th transistor Second clock signal end, the second end of the 9th transistor connect the 3rd node.
5. 5. shift register cell according to claim 1, it is characterised in that the drop-down unit includes：6th crystal Pipe, the 8th transistor, the tenth transistor, the 11st transistor and the tenth two-transistor；

   The grid of 6th transistor connects the first node, first end connection second section of the 6th transistor Point, the second end of the 6th transistor connect first level terminal；

   The grid of 8th transistor connects the first node, described Section three of the first end connection of the 8th transistor Point, the second end of the 8th transistor connect first level terminal；

   The grid of tenth transistor connects the section point, and the first end of the tenth transistor connects the first segment Point, the second end of the tenth transistor connect first level terminal；

   The grid of 11st transistor connects the section point, and the first end connection of the 11st transistor is described defeated Go out end, the second end of the 11st transistor connects first level terminal；

   The grid of tenth two-transistor connects the second clock signal end, the first end connection of the tenth two-transistor The output end, the second end of the tenth two-transistor connect first level terminal.
6. 6. shift register cell according to claim 1, it is characterised in that the reset unit includes second transistor With the 4th transistor；

   The grid of the second transistor connects the reset signal end, the first end connection described first of the second transistor Node, the second end of the second transistor connect first level terminal；

   The grid of 4th transistor connects the reset signal end, and the first end of the 4th transistor connects the output End, the second end of the 4th transistor connect first level terminal.
7. 7. shift register cell according to claim 1, it is characterised in that the output unit includes, the first electric capacity And third transistor；

   First pole of first electric capacity connects the first node, and the second pole of first electric capacity connects the output end；

   The grid of the third transistor connects the first node, when the first end of the third transistor connects described first Clock signal end, the second end of the third transistor connect the output end.
8. 8. shift register cell according to claim 1, it is characterised in that the reset cell, including：14th is brilliant Body pipe；

   The grid of 14th transistor connects the second frame start signal end, and the first end of the 14th transistor connects The output end is connect, the second end of the 14th transistor connects first level terminal.
9. 9. according to the shift register cell described in claim any one of 2-8, it is characterised in that each transistor is mutually similar The transistor of type.
10. A kind of 10. shift-register circuit, it is characterised in that including：At least shift register cell of two-stage cascade, wherein the One-level shift register cell is the shift register cell described in claim 1-9 any one.
11. A kind of 11. display device, it is characterised in that including：Shift-register circuit described in claim 10.
12. It is 12. a kind of such as the driving method of claim 1-9 any one shift register cells, it is characterised in that including：

    First stage, reset cell draw the level of output end and the first level terminal under the control at the second frame start signal end Together；Drop-down unit draws first node and the level of the output end with first level terminal under the control of section point Together；

    Second stage, the first input block are defeated by the signal at the first frame start signal end under the control at the first frame start signal end Enter the section point；Drop-down unit is under the control of second clock signal end by the level of the output end and the described first electricity Flush end pulls together；Second input block is under the control of first input end and second clock signal end, by the first input end Signal inputs the first node；Reset cell described in the first preset period of time in the second stage originates in second frame The level of the output end and first level terminal are pulled together under the control of signal end；Output unit stores the first node Level signal；

    Phase III, the output unit is under the control of the first node by the signal of the first clock signal terminal in output end Output；Drop-down unit is under the control of the first node by the level of the first node and the section point and described the One level terminal pulls together；

    Fourth stage, reset unit is under the control at reset signal end by the level and institute of the first node and the output end The first level terminal is stated to pull together.