CN104885217A - Multiple die stacking for two or more die - Google Patents

Abstract

A microelectronic package (1310) can include a substrate (1340) having first and second surfaces (1341, 1342), and first and second microelectronic elements (1320, 1330). The substrate (1340) may have a plurality of substrate contacts (1347a, 1347b) at the first surface (1341) and a plurality of terminals (1350) at the second surface (1342). Component contacts (1324, 1334) of microelectronic components (1320, 1330) may be coupled to corresponding substrate contacts (1347a, 1347b). The front surface (1331) of the second microelectronic element (1330) may partially cover and be attached to the rear surface (1322) of the first microelectronic element (1320). The element contacts (1324) of the first microelectronic element (1320) may be arranged in an area array and flip-chip bonded to the substrate contacts (1347a). The element contacts (1334) of the second microelectronic element (1330) can be coupled to the substrate contacts (1347b) through conductive bumps (1375).

Description

Multi-die stacking of two or more die

Cross References to Related Applications

This application is a continuation of U.S. Patent Application No. 13/658,401, filed October 23, 2012, which is a part of U.S. Patent Application No. 13/306,203, filed November 29, 2011 Continuing the application, US Patent Application No. 13/306,203 claims the benefit of US Provisional Patent Application No. 61/477,820, filed April 21, 2011, the disclosure of which is incorporated herein by reference. The following commonly owned applications are incorporated herein by reference, including: US Provisional Patent Applications 61/477,877, 61/477/883, and 61/477,967, all filed April 21, 2011.

Background technique

The present invention relates to stacked microelectronic assemblies, methods of making such assemblies, and components for such assemblies.

Semiconductor chips are usually provided as individual prepackaged units. A standard chip has a flat rectangular body with a large front face that has contacts that connect to the chip's internal circuitry. Each individual chip is typically mounted in a package, which is then mounted on a circuit board, such as a printed circuit board, and the package connects the contacts of the chip to the conductors of the circuit board. In many conventional designs, the chip package occupies a much larger area on the circuit board than the chip itself.

"Area of a chip" as used in this disclosure with reference to a flat chip having a front should be understood to refer to the area of said front. In a "flip-chip" design, the front side of the chip faces the side of the package substrate, ie, the chip carrier is bonded directly to the contacts on the chip carrier via solder balls or other connecting elements. The chip carrier can in turn be bonded to the circuit board by covering the terminals on the front of the chip. The "flip-chip" design provides a relatively compact arrangement; each chip occupies an area of the circuit board equal to or slightly larger than the front face of the chip, such as in certain embodiments of commonly assigned U.S. Patents 5,148,265, 5,148,266, and 5,679,977 disclosed, the entire disclosure of which is incorporated herein by reference.

Certain innovative mounting techniques provide closeness close to or equal to that of conventional flip-chip bonding. A package that can accommodate a single chip in an area of a circuit board that is equal to or slightly larger than the area of the chip itself is commonly referred to as a "chip scale package."

In addition to minimizing the board's planar area occupied by the microelectronic components, there is a need to produce a chip package with a reduced overall height or size perpendicular to the board's plane. Such thin microelectronic packages allow the circuit board in which the package is mounted to be placed in close proximity to adjacent structures, thereby reducing the overall size of the product containing the circuit board.

Various proposals have been made for arranging multiple chips in a single package or module. In conventional "multi-chip modules," chips are mounted side-by-side on a single packaging substrate, which can then be mounted to a circuit board. This approach provides only a limited reduction in the overall area of the circuit board occupied by the chip. The total area is still larger than the total surface area of the individual chips in the module.

It has also been proposed to package multiple chips in a "stacked" arrangement (ie an arrangement in which multiple chips are placed one above the other). In a stacked arrangement, multiple chips can be mounted in an area of the circuit board that is smaller than the total area of the chips. For example, stacked die arrangements are disclosed in certain embodiments in the aforementioned US Patents 5,679,977, 5,148,265, and 5,347,159, the entire disclosures of which are incorporated herein by reference. US Patent 4,941,033, also incorporated herein by reference, discloses an arrangement in which chips are stacked one on top of the other and are interconnected to each other by conductors on a so-called "wiring film" associated with the chips.

Although multi-chip packaging has made some progress, further improvements are still needed in order to minimize its size and improve its performance. The features of the present invention will be realized by the construction of the microelectronic assembly described below.

Contents of the invention

According to aspects of the invention, a microelectronic package may include a substrate having opposing first and second surfaces, and a first microelectronic element and a second microelectronic element having a front surface facing the first surface of the substrate. Electronic component. The substrate can have a plurality of substrate contacts at the first surface and a plurality of terminals at the second surface for connecting the microelectronic package to at least one component external to the package. Each microelectronic element has a plurality of element contacts at its front surface. The element contacts of each microelectronic element can be coupled with corresponding substrate contacts. The front surface of the second microelectronic element can partially cover and be attached to the rear surface of the first microelectronic element. The element contacts of the first microelectronic element can be arranged in an area array and flip-chip bonded to the first set of substrate contacts. The element contacts of the second microelectronic element can be coupled to the second set of substrate contacts through the conductive bumps.

In one particular example, the element contacts of the second microelectronic element can protrude beyond the side edges of the first microelectronic element. In one embodiment, at least one of the first microelectronic element and the second microelectronic element includes a memory element. In an exemplary embodiment, the microelectronic package may also include a plurality of leads extending from at least some of the substrate contacts to the terminals. The leads can be used to carry address signals to address the memory element in at least one of the first microelectronic element and the second microelectronic element. In one example, at least some of the terminals can be used to carry at least one of a signal or a reference potential between the respective terminal and each of the first and second microelectronic elements.

In one embodiment, the microelectronic package may further include a plurality of third microelectronic elements, each third microelectronic element being electrically connected to the substrate. In a specific example, a plurality of third microelectronic elements can be arranged in a stacked structure, each third microelectronic element having a front surface or a front surface or a rear surface facing an adjacent third microelectronic element. back surface. In one embodiment, a plurality of third microelectronic elements may be arranged in a planar configuration, each third microelectronic element having a peripheral surface facing a peripheral surface of an adjacent third microelectronic element.

In one exemplary embodiment, the second microelectronic element can include volatile RAM, each third microelectronic element can include non-volatile flash memory, and the first microelectronic element can include A processor for data transfer between the second microelectronic element and the third microelectronic element. In one example, the second microelectronic element can include a volatile frame buffer memory element, each third microelectronic element can include a non-volatile flash memory, and the first microelectronic element can include a graphics processor.

In a particular embodiment, a system may include a plurality of the above-described microelectronic packages, circuit boards, and processors. The terminals of the microelectronic package are electrically connected to the board contacts of the circuit board. Each microelectronic package can be used to transfer N parallel data bits in a clock cycle, and the processor can be used to transfer M parallel data bits in a clock cycle, and M is greater than or equal to N. In a particular example, a system may include a microelectronic package as described above, and one or more other electronic components electrically connected to the microelectronic package. In one embodiment, the system may also include a housing to which the above-described microelectronic package and other electronic components are mounted.

According to another aspect of the invention, a module may include a module card having a first surface and a second surface, the first microelectronic element and the second microelectronic element having a front surface facing the first surface of the module card. The module card may have a plurality of parallel exposed edge contacts adjacent an edge of at least one of the first and second surfaces for mating with corresponding contacts of the receptacle when the module is inserted into the receptacle. The module card may have a plurality of card contacts on the first surface. Each microelectronic element may have a plurality of element contacts at its front surface. The element contacts of each microelectronic element can be coupled with corresponding card contacts. The front surface of the second microelectronic element can partially cover and be attached to the rear surface of the first microelectronic element. The element contacts of the first microelectronic element may be arranged in an area array and flip-chip bonded to the first set of card contacts. The component contacts of the second microelectronic component are coupled to the second set of card contacts through the conductive bumps.

In one exemplary embodiment, the element contacts of the second microelectronic element may protrude beyond the side edges of the first microelectronic element. In one example, the edge contacts may be exposed at at least one of the first surface or the second surface of the module card. In a particular embodiment, at least one of the first microelectronic element and the second microelectronic element can include a memory element. In one embodiment, a module may include a plurality of leads extending from at least some of the card contacts to the edge contacts. The leads can be used to carry address signals to address the memory element in at least one of the first microelectronic element and the second microelectronic element. In one particular example, at least some of the edge contacts can be used to carry at least one of a signal or a reference potential between the respective edge contact and each of the first and second microelectronic elements.

In one particular example, the module may also include a plurality of third microelectronic elements, each third microelectronic element being electrically connected to the module card. In one example, a plurality of third microelectronic elements may be arranged in a stacked structure, each third microelectronic element having a front surface or a rear surface facing a front surface or a rear surface of an adjacent third microelectronic element. surface. In a particular embodiment, a plurality of third microelectronic elements may be arranged in a planar configuration, each third microelectronic element having a peripheral surface facing a peripheral surface of an adjacent third microelectronic element.

In one embodiment, the second microelectronic element can include volatile RAM, each third microelectronic element can include non-volatile flash memory, and the first microelectronic element can include a A processor for data transfer between the microelectronic element and the third microelectronic element. In one particular example, the second microelectronic element can include a volatile frame buffer memory element, each third microelectronic element can include a non-volatile flash memory, and the first microelectronic element can include a graphics processor.

In an exemplary embodiment, a system may include a plurality of the modules, circuit boards and processors described above. The exposed contacts of the module are plugged into mating sockets that are electrically connected to the circuit board. Each module is used to transmit N parallel data bits in a clock cycle, and the processor is used to transmit M parallel data bits in a clock cycle, and M is greater than or equal to N. In one example, a system may include the module described above, and one or more other electronic components electrically connected to the module. In a particular embodiment, the system may also include a housing to which the aforementioned modules and other electronic components are mounted.

Description of drawings

1A is a schematic cross-sectional view of a stacked microelectronic assembly according to an embodiment of the present invention;

1B is a bottom cross-sectional view of the stack assembly of FIG. 1A along line 1B-1B in FIG. 1A;

1C is a side cross-sectional view of the stacked assembly of FIG. 1B along line 1C-1C in FIG. 1B;

2 is a schematic cross-sectional view of a stacked microelectronic assembly having flip-chip bonded microelectronic elements according to another embodiment;

3 is a schematic cross-sectional view of a stacked microelectronic assembly with upward facing microelectronic elements according to another embodiment;

4 is a schematic cross-sectional view of a stacked microelectronic assembly having a single opening in a module card for wire bonds to extend through attached to two microelectronic elements, according to another embodiment.

5 is a schematic cross-sectional view of a stacked microelectronic assembly with wire bonds according to another embodiment;

6 is a schematic cross-sectional view of a stacked microelectronic assembly with elongated solder contacts according to another embodiment;

7A is a schematic cross-sectional view of a stacked microelectronic assembly having microelectronic elements with contacts located near their edges according to another embodiment;

7B is a bottom cross-sectional view of the stacked package of FIG. 7A along line 7B-7B in FIG. 7A;

Figure 7C is a partial view showing an alternative arrangement of contacts for a portion of Figure 7B;

8 is a variation of the bottom cross-sectional view of the stacked assembly of FIG. 1B in which one microelectronic element has rows of center contacts oriented generally perpendicular to rows of center contacts of another microelectronic element;

9A is a schematic cross-sectional view of a stacked microelectronic assembly with a lead frame according to another embodiment;

9B is a bottom cross-sectional view of the stack assembly of FIG. 9A along line 9B-9B in FIG. 9A;

9C is a side cross-sectional view of the stack assembly of FIG. 9B along line 9C-9C in FIG. 9B;

10A is a schematic top view of a stacked microelectronic assembly having a plurality of stacked microelectronic elements (encapsulant not shown), according to another embodiment;

10B is a side cross-sectional view of the stacked assembly of FIG. 10A along line 10B-10B in FIG. 10A;

10C is a schematic top view of a stacked microelectronic assembly having a plurality of mutually adjacent microelectronic elements according to another embodiment;

Figure 11 is a schematic perspective view of a stacked microelectronic assembly comprising two interbonded module cards according to another embodiment;

Figure 12 is a schematic diagram of a system comprising multiple modules according to one embodiment;

13A is a schematic cross-sectional view of a stacked microelectronic package according to another embodiment;

13B is a bottom cross-sectional view of the stacked package shown in FIG. 13A along line 13A-13A in FIG. 13A;

14A-14E are partial cross-sectional views of variations of a portion of the stacked microelectronic package of FIG. 13A shown by shaded portion 14 in FIG. 13A;

15 is a schematic cross-sectional view of a stacked microelectronic package with elongated solder contacts according to another embodiment;

Figure 16 is a schematic diagram of a system according to an embodiment of the present invention.

Detailed ways

Referring to FIGS. 1A-1C , a module 10 according to an embodiment of the present invention may include a first microelectronic element 20 , a second microelectronic element 30 and a module card 40 having exposed edge contacts 50 . First encapsulant 60 may cover microelectronic elements 20 and 30 , as well as a portion of module card 40 .

In some embodiments, at least one of first microelectronic element 20 and second microelectronic element 30 may be a semiconductor chip, wafer, or the like. For example, one or both of the first microelectronic element 20 and the second microelectronic element 30 may include a memory element, such as a DRAM. As used herein, "memory element" refers to a plurality of memory cells arranged in an array with circuitry for storing and retrieving data therefrom, eg, for transferring data over an electrical interface. In one particular example, module 10 may be included in a single inline memory module (SIMM) or a dual inline memory module (DIMM).

The first microelectronic element 20 may have a front surface 21, a rear surface 22 remote from the front surface 21, and a side edge 23 extending between the front surface and the rear surface. Electrical contacts 24 are exposed at the front surface 21 of the first microelectronic element 20 . As described herein, the electrical contacts 24 of the first microelectronic element 20 may also be referred to as "chip contacts." As used herein, the state that a conductive element is "exposed" at a surface of a structure means that the conductive element is available for contact with a theoretical point moving in a direction perpendicular to the surface of the structure from outside the structure towards the surface of the structure. Accordingly, a terminal or other conductive element exposed at a surface of a structure may protrude from such surface; may be flush with such surface; or may be recessed relative to such surface and exposed through a hole or recess in the structure. The contacts 24 of the first microelectronic element 20 are exposed at the front surface 21 within the central region 25 of the first microelectronic element. For example, the contacts 24 may be arranged in one row adjacent the center of the front surface 21 or in two parallel rows.

The second microelectronic element 30 may have a front surface 31, a rear surface 32 remote from the front surface 31, and a side edge 33 extending between the front surface and the rear surface. Electrical contacts 34 are exposed at the front surface 31 of the first microelectronic element 30 . As described herein, the electrical contacts 34 of the second microelectronic element 30 may also be referred to as "chip contacts." Contacts 34 of the second microelectronic element 30 are exposed at the front surface 31 within the central region 35 of the second microelectronic element. For example, the contacts 34 may be arranged in one row adjacent the center of the front surface 31 or in two parallel rows.

As shown in Figures 1A and 1C, a first microelectronic element 20 and a second microelectronic element 30 are stacked on top of each other. In some embodiments, the front surface 31 of the second microelectronic element 30 and the rear surface 22 of the first microelectronic element 20 face each other. At least a portion of the front surface 31 of the second microelectronic element 30 may cover at least a portion of the rear surface 22 of the first microelectronic element 20 . At least a portion of the central region 35 of the second microelectronic element 30 may protrude beyond the side edge 23 of the first microelectronic element 20 . Correspondingly, the contacts 34 of the second microelectronic element 30 may be placed at positions protruding beyond the side edge 23 of the first microelectronic element 20 .

The microelectronic assembly 10 may further include a module card 40 having oppositely facing first and second surfaces 41 , 42 . One or more conductive contacts 44 may be exposed at the second surface 42 of the module card 40 . The module card 40 may further include one or more holes, such as a first hole 45 and a second hole 46 . As shown in FIGS. 1A and 1C , the respective front surfaces 21 and 31 of the first microelectronic element 20 and the second microelectronic element 30 may face the first surface 41 of the module card 40 .

Module card 40 may be partially or fully fabricated from any suitable dielectric material. For example, module card 40 may comprise a relatively rigid sheet-like material, such as a thick layer of fiber reinforced epoxy, eg, Fr-4 board or Fr-5 board. Regardless of the material used, module card 40 may comprise a single layer or multiple layers of dielectric material. In a particular embodiment, module card 40 may consist essentially of a material having a coefficient of thermal expansion of less than thirty parts per million degrees Celsius ("30 ppm/°C").

As shown in FIG. 1 , the module card 40 may extend beyond the side edge 23 of the first microelectronic element 20 and the side edge 33 of the second microelectronic element 30 . The first surface 41 of the module card 40 can be juxtaposed with the front surface 21 of the first microelectronic element 20 .

In the embodiment depicted in FIGS. 1A-1C , the module card 40 includes a first aperture 45 substantially aligned with the central region 25 of the first microelectronic element 20 and substantially aligned with the central region 35 of the second microelectronic element 30. The second hole 46 of the contact hole 46 thereby contacts the contacts 24 and 34 through the first hole and the second hole, respectively. The first hole 45 and the second hole 46 may extend between the first surface 41 and the second surface 42 of the module card 40 . As shown in FIG. 1B , apertures 45 and 46 may be aligned with respective chip contacts 24 or 34 of respective first 20 and second 30 microelectronic elements.

Module card 40 may also include conductive contacts 44 exposed at its second surface 42 and conductive traces 55 extending between contacts 44 and exposed edge contacts 50 . Conductive traces 55 electrically couple contacts 44 to exposed edge contacts 50 . In a particular embodiment, contacts 44 may be ends of respective traces 55 .

In certain embodiments, the module card 40 may have a plurality of parallel exposed edge contacts 50 adjacent the inset edge 43 of at least one of the first surface 41 and the second surface 42 for use when the module 10 When inserted into the socket (shown in Figure 12), it is butted with the corresponding contact of the socket. As shown in FIG. 1B , inset edge 43 may be positioned such that holes 45 and 46 each have a length L extending in a direction away from inset edge 43 of module card 40 . Some or all of the edge contacts 50 may be exposed at one or both of the first surface 41 or the second surface 42 of the module card 40 .

The exposed edge contacts 50 and the inset edges 43 may be sized to plug into corresponding receptacles (FIG. 12) of other connectors in the system, such as may be provided on a motherboard. Such exposed edge contacts 50 may be adapted to mate with corresponding spring contacts (FIG. 12) within such a receptacle connector. Such spring contacts may be provided on one or more sides of each slot to interface with corresponding exposed edge contacts 50 . In one example, at least some of the edge contacts 50 can be used to carry at least one of a signal or a reference potential between the respective edge contact and each of the first microelectronic element 20 and the second microelectronic element 30 .

As shown in FIGS. 1A-1C , electrical connections or leads 70 may connect the contacts 24 of the first microelectronic element 20 and the contacts 34 of the second microelectronic element 30 to the exposed edge contacts 50 . Leads 70 may include wire bonds 71 and 72 , and conductive trace 55 . In one embodiment, leads 70 are contemplated for electrically connecting both microelectronic elements 20 and 30 to module card 40 . In a particular example, the leads 70 can be used to carry address signals to address memory elements in at least one of the first microelectronic element 20 and the second microelectronic element 30 .

As used herein, a "lead" is part or all of an electrical connection extending between two conductive elements, for example lead 70 including wire bond 71 and conductive trace 55 . The conductive trace 55 extends from a contact 24 of the first microelectronic element 20 through the first aperture 45 to an exposed edge contact 50 .

In one example, module 10 may include a plurality of leads extending within holes 45 and 46 from chip contacts 24 and 34 of at least one of first microelectronic 20 and second microelectronic element 30 to exposed edge contacts 50. 70. In a particular example, leads 70 may include conductive traces 55 on module card 40 and wires extending from the conductive traces to chip contacts 24 and 34 of at least one of first microelectronic 20 and second microelectronic element 30. Bond 71, 72.

As shown in FIG. 1B , the conductive traces 55 of the leads 70 may extend along the second surface 42 of the module card 40 . In particular examples, the conductive traces 55 of the leads 70 may extend along the first surface 41 of the module card 40 , or the conductive traces of the leads may extend along the first surface 41 and the second surface 42 of the module card. Portions of conductive traces 55 may extend from respective contacts 24 and 34 to exposed edge contacts 50 along surface 41 or 42 of module card 40 in a direction generally parallel to length L of holes 45 and 46 . In certain embodiments, the conductive traces 55 can be arranged along the surface 41 or 42 of the module card 40 in such a way that the length of the leads 70 between the respective contacts 24 and 34 and the exposed edge contacts 50 can be minimized. .

Each of the wire bonds 71 and 72 may extend through a respective first hole 45 or second hole 46 and may electrically couple a respective contact 24 or 34 to a corresponding contact 44 of the module card 40 . The forming process of wire bonds 71 and 72 may include inserting a bonding tool through holes 45 , 46 to electrically connect conductive contacts 24 , 34 to corresponding conductive contacts 44 of module card 40 .

In a particular embodiment, each of wire bonds 71 and 72 may be a multi-wire bond including wire bonds in multiple directions substantially parallel to each other. Such a multi-wire bond structure including multiple wire bonds 71 , 72 may provide parallel conductive paths between contacts 24 or 34 and corresponding contacts 44 of module card 40 .

The spacer 12 may be located between the front surface 31 of the second microelectronic element 30 and a portion of the first surface 41 of the module card 40 . Such a spacer 12 may be made of, for example, a dielectric material (such as a silicon diode), a semiconducting material (such as silicon), or one or more layers of adhesive. If the spacer 12 includes an adhesive, the adhesive can connect the second microelectronic element 30 to the module card 40 . In one embodiment, the spacer 12 may have a thickness equal to that of the first microelectronic element 20 between the front surface 21 and the rear surface 22 in a vertical direction V substantially perpendicular to the first surface 41 of the module card 40. T2 is substantially equal to the thickness of T1.

In a particular embodiment, the spacer 12 may be replaced by a buffer chip having a first surface 41 facing the module card 40 . In one example, such a buffer chip may be flip-chip bonded to contacts exposed at the first surface 41 of the module card 40 . Such a buffer chip may be used to help provide impedance isolation of each of the microelectronic elements 20 , 30 from components external to the module 10 .

One or more adhesive layers 14 may be located between the first microelectronic element 20 and the module card 40, between the first microelectronic element 20 and the second microelectronic element 30, between the second microelectronic element 30 and the spacer 12 Between, and between the spacer 12 and the module card 40. Such an adhesive layer 14 may include an adhesive for bonding the above-mentioned components of the module 10 to each other. In particular embodiments, one or more adhesive layers 14 may extend between first surface 41 of module card 40 and first surface 21 of first microelectronic element 20 . In one embodiment, one or more adhesive layers 14 may attach at least a portion of the front surface 31 of the second microelectronic element 30 to at least a portion of the rear surface 22 of the first microelectronic element 20 .

In one example, each adhesive layer 14 may be partially or entirely made of a die attach adhesive and may be composed of a low elastic modulus material such as a silicone elastomer. In one embodiment, the die attach adhesive may be compatible. In another example, if the two microelectronic elements 20 and 30 are conventional semiconductor chips formed of the same material, each adhesive layer 14 may be partially or completely formed by a thin layer of high elastic modulus adhesive or solder because, in response to temperature changes, microelectronic components will tend to expand or contract in unison. Regardless of the material used, each adhesive layer 14 may comprise a single layer or multiple layers therein. In certain embodiments where the spacer sheet 12 is made of adhesive, the adhesive layer 14 between the spacer sheet 12, the second microelectronic element 30 and the module card 40 may be omitted.

The module 10 may also include a first encapsulant 60 and a second encapsulant 65 . The first encapsulant 60 may cover, for example, the respective rear surfaces 22 and 32 of the first and second microelectronic elements 20 and 30 , and portions of the first surface 41 of the module card 40 . In certain embodiments, the first encapsulant 60 may be an overmold. One or more encapsulants 65 may cover the front surfaces 21 and 31 of the first microelectronic element 20 and the second microelectronic element 30 exposed within the respective apertures 45 and 46, portions of the second surface 42 of the module card 40 , contacts 24 , 34 and 44 , and wire bonds 71 and 72 extending between each contact 24 , 34 and the corresponding contact 44 . In particular embodiments, the second encapsulant 65 may cover portions of the leads 70 extending between the chip contacts 24 , 34 and the module card 40 .

In a process according to certain embodiments, a first encapsulant 60 may be injected onto the respective rear surfaces 22 and 32 of the first microelectronic element 20 and the second microelectronic element 30, and the first surface of the module card 40. 41 on. In a process according to one example, the second encapsulant 65 may be injected into the first hole 45 and the second hole 46 such that the portion of the lead 70 between the chip contacts 24 , 34 and the module card 40 is second sealed. Sealant coverage.

Figure 2 is a variation of the embodiment described with respect to Figures 1A-1C. In this variant, the module 210 is identical to the module 10 described above, except that the first microelectronic element 220 is flip chip bonded to the first surface 241 of the module card 240 instead of wire bonded to the second surface of the module card.

Conductive contacts 224 are exposed at the front surface 221 of the first microelectronic element 220 . Conductive contacts or chip contacts 224 may be electrically connected to conductive contacts 247 exposed at first surface 241 of module card 240 through, for example, conductive bumps 273 . The conductive bump 273 may include a fusible metal having a lower melting temperature, for example, solder, tin, or a low-melting mixture including multiple metals. Alternatively, conductive mass 273 may comprise a wettable metal such as copper or other noble or non-noble metal that has a higher melting temperature than solder or other fusible metal. In certain embodiments, the conductive block 273 may include a conductive material dispersed in a medium, such as conductive paste, metal-filled paste, solder-filled paste, isotropic conductive paste, or anisotropic conductive paste.

Conductive traces (not shown in FIG. 2 ) may extend from the conductive contacts 247 along the first surface 241 of the module card 240 to an interposer edge (such as that shown in FIGS. 1B and 1C ) of the module card. 43) at the exposed edge contacts. As in module 10 described above, chip contacts 234 of second microelectronic element 230 may be electrically connected to corresponding conductive contacts 244 of module card 240 by wire bonds 272 extending through holes 246 of the module card. Conductive traces may also extend from conductive contacts 244 along second surface 242 of module card 240 to exposed edge contacts at an insertion edge of the module card (such as insertion edge 43 shown in FIGS. 1B and 1C ). point.

Figure 3 is another variant of the embodiment described with respect to Figures 1A-1C. In this variant, the module 310 is identical to the module 10 described above, except that the first microelectronic element 320 is placed with its rear surface 322 facing the first surface 341 of the module card 340, and at least part of its front surface 321 facing and partially ground covering at least a portion of the front surface 331 of the second microelectronic element 330. The rear surface 322 of the first microelectronic element 320 may be attached to the first surface 341 of the module card 340 by one or more adhesive layers, such as the adhesive layer 14 shown in FIGS. 1A and 1C . Conductive contacts 324 a and 324 b (collectively conductive contacts 324 ) may be exposed at front surface 321 of first microelectronic element 320 . The chip contacts 324 of the first microelectronic element 320 may include any configuration of conductive contacts 324a and/or 324b.

The conductive contacts 324a of the first microelectronic element 320 may be exposed at the first surface 321 within the central region 325 of the first microelectronic element. For example, the contacts 324a may be arranged in one row adjacent to the center of the front surface 321 or in two parallel rows. Conductive contacts 324a may be electrically connected to conductive contacts 347 exposed at first surface 341 of module card 340 by, for example, wire bonds 371a.

The conductive contacts 324b of the first microelectronic element 320 may be exposed at the front surface 321 near the side edges 323 of the first microelectronic element. For example, the contacts 324b may be arranged in one row adjacent the side edge 323 of the first microelectronic element 320 or in two parallel rows. Conductive contacts 324b may be electrically connected (via, eg, wire bonds 371b ) to conductive contacts 347 exposed at first surface 341 of module card 340 .

Similar to FIG. 2 , conductive traces (not shown in FIG. 3 ) may extend from conductive contacts 347 and 344 along the first surface 341 and second surface 342 of the module card 340 to the interposer edge of the module card, respectively. The exposed edge contacts at (eg, interpolation edge 43 shown in FIGS. 1B and 1C ).

Although the embodiment shown in FIG. 3 shows the second microelectronic element 330 electrically connected to the module card 340 by wire bonds 372, in other embodiments, the second microelectronic element may be electrically connected to the module card by various other means. , including, for example, wire bonding (as shown in FIG. 5 ) or flip-chip bonding using solder (as shown in FIGS. 6 and 7 ).

FIG. 4 is another variant of the embodiment described with reference to FIGS. 1A to 1C . In this variation, the module 410 is identical to the module 10 described above, except that the first microelectronic element 410 and the second microelectronic element 420 extend through a common The respective wire bonds 471 and 472 of the holes 446 are electrically connected to the module card 440, rather than having each microelectronic element electrically connected to the module card by wire bonds extending through respective separate holes of the module card.

As shown in FIG. 4, the conductive contacts 424 of the first microelectronic element 420 may be exposed at the front surface 421 near the side edges 423 of the first microelectronic element. For example, the contacts 424 may be arranged in rows adjacent to the side edge 423 of the first microelectronic element 420 . The conductive contacts 424 may be electrically connected to the conductive contacts 444 exposed on the second surface 442 of the module card 440 by, for example, wire bonds 471 .

The conductive contacts 434 of the second microelectronic element 430 may be exposed at the front surface 431 within the central region 435 of the second microelectronic element. For example, contacts 434 may be arranged in rows proximate the center of front surface 431 . The conductive contacts 434 may be electrically connected to the conductive contacts 444 exposed on the second surface 442 of the module card 440 by, for example, wire bonds 472 .

In the embodiment shown in FIG. 4 , module 410 may include a single second encapsulant 465 . For example, the second encapsulant 465 may cover, portions of the respective front surfaces 421 and 431 of the microelectronic elements 420 and 430 exposed within the single common aperture 446, portions of the second surface 442 of the module card 440, the contacts 424, 434 and 444 , and wire bonds 471 and 472 extending between each contact 424 , 434 and the corresponding contact 444 .

FIG. 5 is another variant of the embodiment described with reference to FIGS. 1A to 1C . In this variation, the module 510 is identical to the module 10 described above, except that the first microelectronic element 520 is flip-chip bonded to the first surface 541 of the module card 540 (in the same manner as shown in FIG. 2 ), and the second microelectronic Component 530 is electrically connected to module card 540 by wire bonds 574 a and 574 b (collectively wire bonds 574 ) extending from conductive traces to chip contacts 534 , rather than by wire bonds.

As shown in FIG. 5, conductive contacts 534a and 534b (collectively conductive contacts 534) of second microelectronic element 530 may be exposed at front surface 531 within central region 535 of the second microelectronic element. For example, the contacts 534 may be arranged in one row adjacent the center of the front surface 531 or in two parallel rows. Some of the conductive contacts 534a may be electrically connected to the conductive contacts 544 exposed on the second surface 542 of the module card 540 by, for example, wire bonds 574a. The other conductive contacts 534b may be electrically connected to the conductive contacts 547 exposed on the first surface 541 of the module card 540 by, for example, wire bonds 574b. As shown in FIG. 5, conductive contacts 544 and 547 may be conductive contact portions of respective wire bonds 574a and 574b.

The process for forming wire bonds 574 may be substantially as described in commonly assigned US Patent Nos. 5,915,752 and 5,489,749, the disclosures of which are incorporated herein by reference. During the wire bonding process, each wire 570 may be displaced downwardly by a tool, such as a thermosonic bonding tool, to engage a corresponding conductive contact 534 . Such a bonding tool may be inserted through holes 546 to electrically connect leads 570 to corresponding conductive contacts 534 . The fragile portion of lead 570 may break in the process.

FIG. 6 is another variation of the embodiment described with respect to FIGS. 1A-1C . In this variation, the module 610 is identical to the module 10 described above, except that the first microelectronic element 620 is flip-chip bonded to the first surface 641 of the module card 640 (in the same manner as shown in FIG. 2 ), and the second microelectronic The element 630 is flip-chip bonded to the module by a conductive bump 675 extending between the conductive contact 634 of the second microelectronic element and the conductive contact 647 exposed at the first surface of the module card, rather than by wire bonding. The first face of the card. In certain embodiments, module card 640 may not have leads extending through holes between its first surface 641 and second surface 642 (such as holes 45 and 46 shown in FIG. 1A ).

Similar to the module 10 described above, the conductive contacts 634 of the second microelectronic element 630 may be exposed at the front surface 631 within the central region 635 of the second microelectronic element. For example, the contacts 634 may be arranged in one row adjacent the center of the front surface 631 or in two parallel rows.

Conductive bump 675 may be, for example, an elongated solder connection, a solder ball, or any other material described above with reference to conductive bump 273 . Such conductive bumps 675 may extend across the gap between the spacer 612 and the side edge 623 of the first microelectronic element 620 to electrically connect the second microelectronic element 630 to the module card 640 .

7A and 7B are another variation of the embodiment described with respect to FIG. 6 . In this variation, the module 710 is identical to the module 610 described above, except that the second microelectronic element 730 communicates with the conductive contact 734 located adjacent the side edge 733 of the second microelectronic element to the contact surface exposed at the first surface of the module card. The conductive bumps 775 extending between the conductive contacts 747 are flip-chip bonded to the first surface 741 of the module card 740, rather than having the conductive bumps on the surface of the second microelectronic element exposed in the central region of the second microelectronic element. Extending between the conductive contacts at the front surface.

The first microelectronic element 720 may have a plurality of element contacts 724 at a first surface 721 of the first microelectronic element. The component contacts 724 can be coupled with the first set of substrate contacts 747a such that the component contacts are flip-chip bonded to the substrate contacts. As shown in FIG. 7B, each of the component contacts 724 and the first set of substrate contacts 747a may be arranged in an area array configuration.

In a particular example, the contacts 734 at the front surface 731 of the second microelectronic element 730 can be arranged in columns adjacent to the side edges 733 of the second microelectronic element such that the contacts 734 can protrude beyond the sides of the first microelectronic element 720. side edge 723 . The component contacts 734 may be coupled with a second set of substrate contacts 747b such that the component contacts are flip-chip bonded to the substrate contacts.

Although the contacts 724, 734, and 747 are shown arranged in parallel columns of contacts, other arrangements of the contacts are contemplated by the present invention. For example, although not shown in FIG. 7B, at least one contact may be disposed between adjacent columns of contacts. In another example (eg, as shown in FIG. 7C ), the contacts may comprise a column of contacts, wherein the column axis 719 extends through a majority of the column of contacts 724, ie most of the column of contacts 724 is relative to Column axis 719 is centered. However, in such columns, one or more of the contacts 724 may not be centered relative to the column axis 719, as is the case with contacts 724'. In this case, although the contact (or contacts) may not be centered with respect to the column axis 719, the one or more contacts 724' Can be seen as a section of a specific column. Column axis 719 may extend through one or more of the contacts described above that are not centered relative to the column axis, or in some cases, the uncentered contacts may be farther from the column axis such that column axis 719 may not even pass through the column axis. columns of these uncentered contacts. There may be one, several or many contacts in a column or even multiple columns that are not centered relative to the axes of the respective columns.

In addition, microelectronic elements 720, 730 and substrate 740 are likely to contain contacts 724, 734, 747 in groups rather than columns, such as rings, polygons, or even distributed arrangements of contacts.

In one embodiment, like the module 610 described above, the module card 740 may have no leads extending through the aperture between the first surface 741 and the second surface 742 thereof.

FIG. 8 is another variation of the embodiment described with respect to FIG. 1B . In this variation, the module 810 is identical to the module 10 described above, except that the rows of conductive contacts 824 of the first microelectronic element 820 may be substantially perpendicular to the rows of conductive contacts 834 of the second microelectronic element 830 . In this embodiment, the second hole 846 (similar to the second hole 46 shown in FIG. 1B ) may have a length L extending in a direction away from the insertion edge 843 of the module card 840 . The first hole 845 may have a length L' extending in a direction generally parallel to the insertion edge 843 of the module card 840 and generally perpendicular to the length L of the second hole 846 .

Leads 870 may include the same pattern of conductive traces 855a as the pattern of conductive traces 55 shown in FIG. 1B . Leads 870 may further include an optional pattern of conductive traces 855a extending from conductive contacts 844b exposed at second surface 842 of module card 840 to exposed edge contacts 850 . In a particular embodiment, some of the conductive traces 855b may extend around the side edge 848 of the first hole 845 .

Figure 9 is a variation of the embodiment described with respect to Figures 1A-1C. In this variation, the module 910 is identical to the module 10 described above, except that the first microelectronic element 920 and the second microelectronic element 930 are mounted on a lead frame 980 rather than on a module card (such as the module shown in FIG. 1A ). card 40). In certain embodiments, the respective front surfaces 921 and 931 of the first microelectronic element 920 and the second microelectronic element 930 can face the first surface 981 of the lead frame 980 and each microelectronic element is electrically connected to the lead frame.

Examples of leadframe structures are shown and described in US Patent Nos. 7,176,506 and 6,765,287, the disclosures of which are incorporated herein by reference. Typically, a lead frame, such as lead frame 980 , is a structure formed from a layer of conductive metal, such as copper, and patterned into segments that include a plurality of leads or conductive trace portions 985 . In an exemplary embodiment, at least one of the first microelectronic element 920 and the second microelectronic element 930 may be directly mounted on a lead, which may extend under the microelectronic element. In this embodiment, the contacts 924, 934 on the microelectronic element may be electrically connected to the respective leads by solder balls or the like. The leads can then be used to form electrical connections to various other conductive structures for carrying electrical signal potentials to or from the first microelectronic element 920 and the second microelectronic element 930 . When the structural assembly is complete (including forming encapsulant 960 thereon), a temporary element, such as a frame (not shown), may be removed from the leads of leadframe 980 to form individual leads or conductive trace portions 985 .

The first microelectronic element 920 may be attached to the lead frame 980 by one or more adhesive layers 914 extending between the front surface 921 of the first microelectronic element and the first surface 981 of the lead frame. Such adhesive layer 914 may be similar to adhesive layer 14 described above with reference to FIGS. 1A-1C . A spacer 912 may be attached to the lead frame 980 with one or more adhesive layers 914 extending between the front surface 913 of the spacer and the first surface 981 of the lead frame. At least a portion of the front surface 931 of the second microelectronic element 930 may partially cover the rear surface 922 of the first microelectronic element 920 and the rear surface 915 of the spacer 912 . The front surface 931 of the second microelectronic element 930 may be attached to the rear surface 922 of the first microelectronic element 920 and the rear surface 915 of the spacer 912 by one or more adhesive layers 914 .

As shown in FIGS. 9A through 9C , electrical connections or leads 970 may connect contacts 924 of first microelectronic element 920 and contacts 934 of second microelectronic element 930 to exposed module contacts 950 . Leads 970 may include wire bonds 971 and 972 , and conductive trace portion 985 of lead frame 980 . In a particular example, the leads 970 can be used to carry address signals to address memory elements in at least one of the first microelectronic element 920 and the second microelectronic element 930 .

In one example, the lead frame 980 can define a first gap 945 and a second gap 946 extending between a first surface 981 of the lead frame and a second surface 982 opposite the first surface 981 . The first gap 945 can be aligned with the chip contact 924 of the first microelectronic element 920 such that the wire bond 971 can extend through the first gap between the chip contact 924 and the second surface 982 of the lead frame. The second gap 946 can be aligned with the chip contact 934 of the second microelectronic element 930 such that the wire bond 972 can extend through the second gap between the chip contact 934 and the second surface 982 of the lead frame.

The module 910 may also include an encapsulant 960 covering the first microelectronic element 920, the second microelectronic element 930, and a portion of the lead frame 980 such that the exposed module contacts 950 may be exposed on the lower surface 962 of the interposer portion 961 of the encapsulant. place. Encapsulant 960 may also cover contacts 924 , 934 , as well as wire bonds 971 , 972 extending between each contact 924 , 934 and lead frame 980 . The inset portion 961 of the sealant 960 may have a suitable size and shape to interface with a corresponding socket (shown in FIG. 12 ) when the module 910 is inserted into the socket.

In certain embodiments, the module 910 may have a plurality of parallel exposed module contacts 950 adjacent the inset edge 983 of at least one of the first surface 981 and the second surface 982 for contact with the module when the module 910 is inserted into the receptacle. The corresponding contacts of the socket (shown in Figure 12) are butted. Some or all of the module contacts 950 may be exposed on one or both of the first surface 981 and the second surface 982 of the lead frame 980 .

10A and 10B are a variation on the embodiment described with respect to FIG. 2 . In this variation, module 1010 is identical to module 210 described above, except that module 1010 also includes a stack of third microelectronic elements 1090 mounted on module card 1040 .

Similar to FIG. 2 , the first microelectronic element 1020 is flip-chip bonded to the first surface 1041 of the module card 1040 . Conductive contacts or chip contacts 1024 of first microelectronic element 1020 may be electrically connected to conductive contacts 1047 exposed at first surface 1041 of module card 1040 through, for example, conductive bumps 1073 . The chip contacts 1034 of the second microelectronic element 1030 can be electrically connected to corresponding conductive contacts 1044 of the module card 1040 by wire bonds 1072 extending through the holes 1046 of the module card. Conductive traces (not shown in FIGS. 10A and 10B ) may extend along the first surface 1041 and/or second surface 1042 of the module card 1040 from the conductive contacts 1044 and 1047 to the interposer edges exposed on the module card. Edge contacts 1050 at (eg, edge 1043 or edge 1043a). As shown in FIG. 10B , the edge contacts 1050 may be exposed at the first surface 1041 , or at the second surface 1042 , or at both the first surface and the second surface.

The stack of third microelectronic elements 1090 can be any number including, for example, the two third microelectronic elements 1090a and 1090b shown in FIG. 1OB. The third microelectronic elements 1090 may be connected to each other and/or to the edge contacts 1050 by an interconnect structure. For example, the lower third microelectronic element 1090a may be connected to contacts exposed at the surface of the module card 1040 by flip-chip bonding, wire bonding, wire bonding, or other interconnect structures. One or more upper third microelectronic elements 1090b may be connected to contacts of module card 1040 by conductive vias, wire bonds, wire bonds, or other interconnect structures extending through lower third microelectronic elements 1090a.

In an exemplary embodiment, module 1010 may be configured to function as a solid state storage drive. In such an example, the first microelectronic element 1020 may include a semiconductor chip primarily for performing logic functions, such as a solid-state drive controller, and the second microelectronic element 1030 may include a memory storage element, such as a volatile RAM (such as DRAM). The third microelectronic element 1090 may include a memory storage element, such as non-volatile flash memory. The first microelectronic element 1020 may include a dedicated processor for unlocking the central processing unit of a system (such as the system 1200 of FIG. 12 ) to access memory included in the second microelectronic element 1030 and the third microelectronic element 1090. Management of the transfer of data for storage elements. Such a first microelectronic element 1020 including a solid state drive controller may provide direct memory access to and from a data bus on a motherboard (eg, circuit board 1202 shown in FIG. 12 ) of a system (eg, system 1100 ).

In another embodiment, module 1010 can be configured to function as a graphics module, such as a PCI graphics card slot that can be inserted into a laptop computer. In such an example, the first microelectronic element 1020 may include a semiconductor chip primarily for performing logic functions, such as a graphics processor, and the second microelectronic element 1030 may include a memory storage element, such as a volatile RAM (such as a DRAM ), which can be used as a volatile framebuffer for computational graphics drawing. Each third microelectronic element 1090 may include a memory storage element (eg, non-volatile flash memory).

Figure 10C is a variation on the embodiment described with respect to Figures 10A and 10B. In this variation, the module 1010' is identical to the module 1010 described above, except that the module 1010' includes a plurality of third microelectronic elements 1090' mounted on the module card 1040 adjacent to each other rather than stacked. Similar to the module 1010, the third microelectronic element 1090' can be connected to contacts exposed at the surface of the module card 1040 by any interconnection structure, such as flip-chip bonding, wire bonding, wire bonding, or other interconnection structure. The dots are connected. Module 1010' may be used for the same exemplary functions as module 1010, such as a solid state memory drive or a graphics module.

FIG. 11 depicts a component 1100 comprising a first module 1110a and a second module 1110b according to any of the embodiments described above, such as the module 10 described in FIGS. 1A-1C . The first module 1110a and the second module 1110b may be bonded to each other by at least one layer 1165 such that the second surfaces 1142 of the respective module cards 1140 of the modules face each other. In certain embodiments, the at least one layer 1165 described above may be a single common encapsulant (such as the second encapsulant 65 shown in FIGS. 1A and 1B ). In another example, the at least one layer 1165 may be one or more adhesive layers similar to the adhesive layer 14 described with reference to FIGS. 1A-1C .

Component 1100 may have one or more parallel rows of exposed edge contacts 1150 adjacent an interpolated edge 1143 of the component. Each of the first module 1110a and the second module 1110b can have a row of edge contacts 1150 exposed at the first surface 1141 of the respective module card 1140, so that when the component 1100 is inserted into the socket, such edge contacts can be adapted to Mate with corresponding contacts of a socket (similar to the socket shown in Figure 12).

The modules and components described with reference to FIGS. 1A to 10 can be used to construct various electronic systems, such as the system 1200 shown in FIG. 12 . For example, a system 1200 according to a further embodiment of the present invention includes a number of modules or components 1206 as described above, as well as other electronic components 1208 and 1210 .

System 1200 may include a plurality of sockets 1205, each socket including a plurality of contacts 1207 on one or both sides of the socket, such that each socket 1205 may be adapted to contact a corresponding exposed edge of a corresponding module or component 1206 or exposed module contact mating. In the illustrated exemplary system 1200, the system may include a circuit board or motherboard 1202 (such as a flexible printed circuit board) including a plurality of conductors 1204 interconnecting modules or components 1206 to one another, only shown in FIG. one of the conductors. However, this is exemplary only; any suitable structure for making electrical connections between modules or components 1206 may be used.

In a particular embodiment, system 1200 may also include a processor (such as semiconductor chip 1208), such that each module or component 1206 may be used to transfer N parallel data bits in a clock cycle, and the processor may be used to transfer N parallel data bits in a clock cycle. M parallel data bits, where M is greater than or equal to N.

In one example, system 1200 may include a processor chip 1208 for transferring 32 parallel data bits per clock cycle, and the system may also include four modules 1206 (eg, modules 10 described with reference to FIGS. 1A through 1C ) , each module 1206 is used to transmit 8 parallel data bits in a clock cycle (that is, each module 1206 may include a first microelectronic element and a second microelectronic element, each of the two microelectronic elements is used to transmit 8 parallel data bits during a clock cycle 4 parallel data bits are transferred in one cycle).

In another example, the system 1200 may include a processor chip 1208 for transferring 64 parallel data bits in a clock cycle, and the system may also include four modules 1206 (such as the component 1000 described with reference to FIG. 12 ) , each module 1206 is used to transmit 16 parallel data bits in a clock cycle (that is, each module 1206 may include two sets of first microelectronic elements and second microelectronic elements, and each of the four microelectronic elements is used for 4 parallel data bits are transferred in one clock cycle).

In the example depicted in FIG. 12 , component 1208 is a semiconductor chip and component 1210 is a display screen, but any other components may be used in system 1200 . Of course, although only two additional components 1208 and 1210 are shown in FIG. 12 for clarity of illustration, the system may include any number of such components.

Module or component 1206 and components 1208 and 1210 are mounted in a common housing 1201 (shown schematically in phantom) and are electrically interconnected with each other as necessary to form the desired electrical circuit. Housing 1201 is shown as a portable housing of the type found in, for example, mobile phones or personal digital assistants, and screen 1210 may be exposed at the surface of the housing. In embodiments where structure 1206 includes a photosensitive element (eg, an imaging chip), a lens 1211 or other optical device may also be provided for directing light to the structure. Furthermore, the simplified system shown in FIG. 12 is exemplary only; other systems can be fabricated using the structures described above, including systems that are generally considered to be fixed structures, such as desktop computers, routers, and the like.

Figures 13A and 13B are a variation on the embodiment described with respect to Figures 7A and 7B. In this variation, microelectronic package 1310 is identical to module 710 described above, except that microelectronic package 1310 includes microelectronic elements 1320 and 1330 mounted to substrate 1340 rather than a module card, and microelectronic package 1310 has Terminals 1350 for non-edge contact interconnections. In one embodiment, similar to module 710 described above, substrate 1340 may have no leads extending through holes in the substrate.

The first microelectronic element 1320 may have a front surface 1321 facing a first surface 1341 of the substrate 1340 . The first microelectronic element 1320 can have a plurality of element contacts 1324 at the front surface 1321 of the first microelectronic element. The component contacts 1324 can be coupled with the first set of substrate contacts 1347a such that the component contacts are flip-chip bonded to the substrate contacts. As shown in FIG. 13B, both the component contacts 1324 and the first set of substrate contacts 1347a may be arranged in an area array configuration.

The second microelectronic element 1330 may have a front surface 1331 facing the first surface 1341 of the substrate 1340 . Front surface 1331 of second microelectronic element 1330 may partially cover rear surface 1322 of first microelectronic element 1320 and may be attached to rear surface 1322 , for example, by adhesive layer 1314 .

The second microelectronic element 1330 can have a plurality of element contacts 1334 at its front surface 1331 . Component contacts 1334 may be coupled with a second set of substrate contacts 1347b such that the component contacts are flip-chip bonded to the substrate contacts. As shown in Figure 13B, both the component contacts 1334 and the second set of substrate contacts 1347b may be arranged in a column configuration.

Although contacts 1324, 1334, and 1347 are shown arranged in parallel contact columns, other arrangements of contacts are contemplated by the present invention, as described above with reference to FIGS. 7A-7C.

Substrate 1340 may further include a plurality of terminals 1350 at second surface 1342 for connecting microelectronic package 1310 to a component external to the package. A conductive bump 1351 may be disposed on an exposed surface of the terminal 1350 . Such conductive bumps 1351 may be, for example, solder balls or any other material described above with reference to conductive bumps 273 . In one example, the external component may be a circuit board (eg, circuit board 1602 ) as described below with reference to FIG. 16 .

Contacts 1324 and 1334 may be electrically connected to respective sets of substrate contacts 1347a and 1347b through, for example, respective conductive bumps 1373 and 1375 . Conductive bump 1373 may be, for example, a solder ball or any other material described above with reference to conductive bump 273 . Conductive bump 1375 may be, for example, an elongated solder connection, a solder ball, or any other material described above with reference to conductive bump 273 .

As shown in FIG. 14A , in a variation of the embodiment of FIGS. 13A and 13B , conductive bumps 1375 and/or conductive bumps 1373 may be at least partially replaced by conductive studs 1475 . The conductive posts may include portions deposited (eg, coated or plated) within the openings in which the contacts 1434 of the second microelectronic element are exposed. For example, conductive studs 1475 may be formed by depositing metal or other conductive material, such as a conductive matrix material, in corresponding holes 1476 extending at least partially through encapsulant 1460, and utilizing, for example, U.S. Patent Publication No. 2012/0126389 The process, the disclosure of which is incorporated herein by reference.

In another variation, as shown in FIG. 14B, the posts may include a plurality of frustoconical posts 1477 protruding away from the element contacts 1434 of the second microelectronic element 1430 toward the corresponding substrate contacts 1447b. Each stud 1477 essentially comprises a substantially rigid conductive material, for example, a metal such as copper or aluminum. In one embodiment, post 1477 may be formed by etching a structure such as a continuous or discontinuous sheet of metal attached to a contact. A conductive bump 1473 may be disposed between the post 1477 and the substrate contact 1447b to provide an electrical connection therebetween. As shown in FIG. 14B , studs 1477 may be tapered such that each stud has a first width adjacent component contact 1434 that is greater than a second width adjacent substrate contact 1447b.

Referring to FIG. 14C , in a variation of the embodiment of FIG. 14B , the posts may include a plurality of frustoconical posts 1478 protruding away from the substrate contacts 1447b toward the element contacts 1434 of the corresponding second microelectronic element 1430 . Conductive bumps 1473 may be disposed between terminal posts 1478 and component contacts 1434 to provide electrical connection therebetween. As shown in FIG. 14C , studs 1478 may be tapered such that each stud has a first width adjacent substrate contact 1447b that is greater than a second width adjacent element contact 1434 .

14D, in another variation, at least some of the conductive bumps 1375 may be replaced by conductive posts 1479a and 1479b, the posts 1479a extending from the element contacts 1434 of the second microelectronic element 1430 toward some of the corresponding substrate contacts 1447b. , and stud 1479b extends from the substrate contact toward stud 1479a. Conductive bump 1473 may be disposed between conductive posts 1479a and 1479b to provide electrical connection therebetween. As shown in FIG. 14D , both studs 1479a and 1479b may be tapered such that each stud has a first width adjacent to component contact 1434 or substrate contact 1447b that is greater than a second width adjacent to conductive bump 1473 .

Referring to FIG. 14E , in another variation on the embodiment of FIG. 14B , elongated solder connections 1480 may be provided at post 1477 between substrate contacts 1447b and corresponding element contacts 1434 of second microelectronic element 1430 around to provide an electrical connection between the post and the substrate contacts. The conductive bumps 1473 shown in any of the embodiments of FIGS. 14B, 14C, and 14D may be connected by elongated solder strips extending around respective posts 1477, 1478, and 1479 between component contacts 1434 and substrate contacts 1447b. 1480 instead.

FIG. 15 is a variation of the embodiment described with respect to FIG. 6 . In this variation, microelectronic package 1510 is identical to module 610 described above, except that microelectronic package 1510 includes microelectronic elements 1520 and 1530 mounted to substrate 1540 rather than a module card, and microelectronic package 1510 has a surface exposed on a second surface. Terminals 1550 at 1542 for interconnecting package 1510 with another component are used instead of edge contacts as in the embodiment shown in FIG. 6 . In one embodiment, similar to module 610 described above, substrate 1540 may have no leads extending through holes in the substrate.

Similar to the module 10 described above, the conductive contacts 1534 of the second microelectronic element 1530 may be exposed at the front surface 1531 within the central region 1535 of the second microelectronic element. For example, the contacts 1534 may be arranged in one row adjacent the center of the front surface 1531 or in two parallel rows.

Conductive bump 1575 may be, for example, an elongated solder connection, a solder ball, or any other material described above with reference to conductive bump 273 . Such conductive bumps 1575 can extend across the gap between the spacer 1512 and the side edges 1523 of the first microelectronic element 1520 to electrically connect the second microelectronic element 1530 to the substrate 1540 .

The conductive bump 1575 shown in Figure 15 may be replaced by any alternative connection between the component contact 1534 and the substrate contact 1547b (shown in Figures 14A to 14E).

Any of the microelectronic packages described with reference to FIGS. 13A-15 may include additional microelectronic elements, such as third microelectronic elements 1090 a and 1090 b (collectively third microelectronic element 1090 ) shown in FIGS. 10A and 10B , and the third microelectronic element 1090' shown in FIG. 10C.

In a particular embodiment, microelectronic package 1310 (or 1510) may include, in a configuration similar to the microelectronic element arrangement shown in FIG. 10B , a stack of third microelectronic components mounted on first surface 1341 of substrate 1340 Electronic components 1090. In such an embodiment, the third microelectronic elements 1090a and 1090b each have a surface facing the first surface 1341 of the substrate, which is the same substrate facing the front surfaces 1321 and 1331 of the microelectronic elements 1320 and 1330. of the same surface. Such a substrate 1340 including the third microelectronic element 1090 may also have terminals 1350 at the second surface 1342 for interconnection with another component, rather than the edge contacts shown in FIG. 10B . In such embodiments, there may be any number of third microelectronic elements 1090 in the stack, including, for example, the two third microelectronic elements 1090a and 1090b in the embodiment shown in FIG. 1OB.

In one example, microelectronic package 1310 (or 1510 ) may include, in a configuration similar to the microelectronic element arrangement shown in FIG. 10C , adjacent rather than stacked A plurality of third microelectronic elements 1090'. In such an embodiment, each third microelectronic element 1090' can have a surface facing the first surface 1341 of the substrate that is opposite to the front surfaces 1321 and 1331 of the microelectronic elements 1320 and 1330. The surfaces of the substrates are the same. Such a substrate 1340 including a third microelectronic element 1090' may also have terminals 1350 at the second surface 1342 for interconnection with another component, rather than the edge contacts shown in FIG. 1OC. In such embodiments, there may be any number of third microelectronic elements 1090' in the stack, including, for example, four third microelectronic elements 1090' in the embodiment shown in FIG. 1OC.

The modules and microelectronic packages described with reference to FIGS. 1A-15 can be used to construct a variety of electronic systems, such as the system 1600 shown in FIG. 16 . For example, system 1600 according to further embodiments of the invention includes one or more modules or components 1606 (eg, microelectronic package 1310 described above) and other electronic components 1608 and 1610 .

In the exemplary system 1600 shown, the system may include a circuit board, motherboard, or expander 1602 (such as a flexible printed circuit board) that includes a plurality of conductors 1604 that interconnect modules or components 1606 to one another, in FIG. 16 Only one of the conductors is shown. Such circuit board 1602 may transmit signals to and from microelectronic packages and/or microelectronic assemblies included within system 1600 . However, this is exemplary only; any suitable structure for making electrical connections between modules or components 1606 may be used.

In a particular embodiment, system 1600 may also include a processor (such as semiconductor chip 1608), such that each module or component 1606 may be used to transfer N parallel data bits in a clock cycle, and the processor may be used to transfer N parallel data bits in a clock cycle. M parallel data bits, where M is greater than or equal to N.

In the example depicted in FIG. 16 , component 1608 is a semiconductor chip and component 1610 is a display screen, but any other components may be used in system 1600 . Of course, although only two additional components 1608 and 1610 are shown in FIG. 16 for clarity of illustration, system 1600 may include any number of such components.

Module or component 1606 and components 1608 and 1610 may be mounted in a common housing 1601 (shown schematically in phantom) and electrically interconnected with each other as necessary to form the desired electrical circuit. Housing 1601 is shown as a portable housing of the type found in, for example, mobile phones or personal digital assistants, and screen 1610 may be exposed at the surface of the housing. In embodiments where structure 1606 includes a photosensitive element (eg, an imaging chip), a lens 1611 or other optical device may also be provided for directing light to the structure. Furthermore, the simplified system shown in FIG. 16 is exemplary only; other systems may be fabricated using the structures described above, including systems that are generally considered to be fixed structures, such as desktop computers, routers, and the like.

One potential advantage of modules or components according to the present invention (such as module 10 shown in FIGS. Connecting a particular exposed edge contact (such as exposed edge contact 50) to a particular electrical contact (such as an electrical contact) exposed at the front surface of a particular microelectronic element (such as first microelectronic element 20) Contacts 24) are electrically connected shorter leads. The parasitic capacitance between adjacent leads is considerable, especially in microelectronic assemblies with high contact density and small pitch. In microelectronic assemblies having shorter leads 70, such as module 10, parasitic capacitance, especially between adjacent leads, can be reduced.

Another potential advantage of a module or component according to the invention is that, as described above, it can be used to provide leads of similar length (such as leads 70), for example connecting data input/output signal terminals (such as exposed edge contacts 50) with The electrical contacts 24, 34 at the respective front surfaces of the first microelectronic element 20 and the second microelectronic element 30 are electrically connected. In a system, such as system 1200 including multiple modules or components 1206, having leads 70 of relatively similar lengths can allow for the propagation delay of data input/output signals between each microelectronic element and exposed edge contacts to be Relatively high match.

Another potential advantage of a module or component according to the invention is that, as described above, it can be used to provide leads of similar length (such as lead 70), and then, for example, a shared clock signal terminal and/or a shared data strobe signal can be The terminals (eg, exposed edge contacts 50 ) are electrically connected to the electrical contacts 24 , 34 at the respective front surfaces of the first microelectronic element 20 and the second microelectronic element 30 . The data strobe signal terminals or the clock signal terminals or both may have approximately the same loading and conduction path lengths to each microelectronic element 20 and microelectronic element 30, and the path lengths to each microelectronic element may be relatively short.

In any or all of the foregoing modules or components, the rear surface of one or more of the first microelectronic element or the second microelectronic element may be at least partially exposed at the outer surface of the microelectronic assembly after fabrication is complete. Therefore, in the assembly described with reference to FIGS. within the module 10. While an overmold (eg, first encapsulant 60 ) or other sealing or encapsulating structure may contact or be disposed adjacent to the microelectronic element, rear surfaces 22 and 32 may be partially or fully exposed.

In any of the embodiments described above, the microelectronic assembly may include a heat sink made of metal, graphite, or any other suitable thermally conductive material. In one embodiment, the heat spreader includes a metal layer disposed adjacent to the first microelectronic element. A metal layer can be exposed on the rear surface of the first microelectronic element. Optionally, the heat spreader may include an overmold or encapsulant covering at least the rear surface of the first microelectronic element.

Although the invention has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the invention. It is therefore to be understood that various modifications may be made to the above-described illustrative embodiments, and that other arrangements may be devised, without departing from the spirit and scope of the invention as defined by the appended claims.

It shall be understood that the individual dependent claims and the features recited therein may be combined in different ways with features of the original claims. It should also be understood that features described in connection with various embodiments may be shared with other features of the described embodiments.

Industrial Applicability

The invention has wide industrial applicability, including but not limited to microelectronic packaging and the manufacturing method of microelectronic packaging.

Claims (as amended under Article 19 of the Treaty)

1. A microelectronic package comprising:

a substrate having opposing first and second surfaces, and a plurality of substrate contacts at the first surface and a plurality of terminals at the second surface for connecting the the microelectronic package is connected to at least one component external to the package; and

A first microelectronic element and a second microelectronic element each having a front surface facing the first surface of the substrate, each microelectronic element having a a plurality of element contacts at the front surface, the element contacts of each microelectronic element being coupled to corresponding substrate contacts, the front surface of the second microelectronic element partially covering and attached to connected to the rear surface of the first microelectronic element, the element contacts of the second microelectronic element exposed in a central region of the front surface of the second microelectronic element,

wherein said element contacts of said first microelectronic element are arranged in an area array and are flip-chip bonded to a first set of said substrate contacts, said element contacts of said second microelectronic element are A conductive block is coupled to a second set of said substrate contacts.

2. The microelectronic package of claim 1, wherein the element contacts of the second microelectronic element protrude beyond a side edge of the first microelectronic element.

3. The microelectronic package of claim 1, wherein at least one of the first and second microelectronic elements comprises a memory element.

4. A microelectronic package as claimed in claim 3 , further comprising a plurality of leads extending from at least some of said substrate contacts to said terminals, wherein said leads are operable to carry address signals for use in said first The memory element is addressed in at least one of the microelectronic element and the second microelectronic element.

5. A microelectronic package as claimed in claim 1 , wherein at least some of said terminals are operable to carry signals or signals between said respective terminals and each of said first and second microelectronic elements. at least one of the reference potentials.

6. The microelectronic package of claim 1, further comprising a plurality of third microelectronic elements, each third microelectronic element being electrically connected to the substrate.

7. The microelectronic package according to claim 6, wherein said plurality of third microelectronic elements are arranged in a stacked configuration, each of said third microelectronic elements having an adjacent third microelectronic element The front surface or the rear surface facing the front surface or the rear surface.

8. The microelectronic package according to claim 6 , wherein said plurality of third microelectronic elements are arranged in a planar configuration, each said third microelectronic element having an adjacent third microelectronic element The peripheral surfaces of the facing peripheral surfaces.

9. The microelectronic package of claim 6, wherein said second microelectronic elements comprise volatile RAM, each of said third microelectronic elements comprises non-volatile flash memory, and said first microelectronic The element includes a processor primarily for controlling data transfer between external components and said second and third microelectronic elements.

10. A microelectronic package as claimed in claim 6, wherein said second microelectronic elements comprise volatile frame buffer memory elements, each of said third microelectronic elements comprises non-volatile flash memory, and said first A microelectronic component includes a graphics processor.

11. The microelectronic package of claim 1, wherein the element contacts of a second microelectronic element are arranged in one row or two parallel rows adjacent to the center of the front surface of the second microelectronic element.

12. The microelectronic package of claim 1, wherein the conductive bumps are elongated solder connections.

13. A system comprising a plurality of microelectronic packages, circuit boards and processors according to claim 1, said terminals of said microelectronic packages being electrically connected to board contacts of said circuit board, each microelectronic The electronic package is used to transmit N parallel data bits in a clock cycle, and the processor is used to transmit M parallel data bits in a clock cycle, where M is greater than or equal to N.

14. A system comprising the microelectronic package of claim 1 and one or more other electronic components electrically connected to the microelectronic package.

15. The system of claim 14, further comprising a housing, the microelectronic package and the other electronic components being mounted to the housing.

16. A module comprising:

A module card having a first surface, a second surface and a plurality of parallel exposed edge contacts adjacent an edge of at least one of the first and second surfaces for mating with corresponding contacts of the socket when the module is inserted into the socket, the module card having a plurality of card contacts on the first surface; and

A first microelectronic element and a second microelectronic element each having a front surface facing the first surface of the module card, each microelectronic element having a a plurality of element contacts at said front surface thereof, said element contacts of each microelectronic element being coupled to corresponding said card contacts, said front surface of said second microelectronic element partially covering and attached to the rear surface of the first microelectronic element, the element contacts of the second microelectronic element exposed in a central region of the front surface of the second microelectronic element,

wherein the element contacts of the first microelectronic element are arranged in an area array and are flip-chip bonded to a first set of the card contacts, and the element contacts of the second microelectronic element are electrically conductive A block is coupled to a second set of said card contacts.

17. The module of claim 16, wherein the element contacts of the second microelectronic element protrude beyond a side edge of the first microelectronic element.

18. The module of claim 16, wherein the edge contacts are exposed at at least one of the first or second surfaces of the module card.

19. The module of claim 16, wherein at least one of the first and second microelectronic elements comprises a memory element.

20. The module of claim 19, further comprising a plurality of leads extending from at least some of said card contacts to said edge contacts, wherein said leads are operable to carry address signals for use in said first micro The memory element is addressed in at least one of the electronic component and the second microelectronic component.

21. The module of claim 16, wherein at least some of the edge contacts are operable to carry contact between the respective edge contacts and each of the first and second microelectronic elements. at least one of signal or reference potential.

22. The module of claim 16, further comprising a plurality of third microelectronic elements, each third microelectronic element electrically connected to the module card.

23. The module of claim 22 , the plurality of third microelectronic elements arranged in a stacked configuration, each of the third microelectronic elements having a front surface opposite to an adjacent third microelectronic element. Or the front surface or the back surface facing the back surface.

24. The module of claim 22 , the plurality of third microelectronic elements arranged in a planar configuration, each of the third microelectronic elements having a peripheral surface that is adjacent to an adjacent third microelectronic element. facing peripheral surfaces.

25. The module of claim 22, wherein the second microelectronic elements comprise volatile RAM, each of the third microelectronic elements comprises non-volatile flash memory, and the first microelectronic elements comprise A processor primarily for controlling data transfers between external components and said second and third microelectronic elements.

26. The module of claim 22, wherein said second microelectronic elements comprise volatile frame buffer memory elements, each of said third microelectronic elements comprises non-volatile flash memory, and said first microelectronic elements Electronic components include graphics processors.

27. The module of claim 16, wherein the element contacts of a second microelectronic element are arranged in one row or two parallel rows adjacent to the center of the front surface of the second microelectronic element.

28. The module of claim 16, wherein the conductive bumps are elongated solder connections.

29. A system comprising a plurality of modules, circuit boards and processors according to claim 16, said exposed contacts of said modules being plugged into mating sockets electrically connected to said circuit board, each module For transmitting N parallel data bits in a clock cycle, the processor is used for transmitting M parallel data bits in a clock cycle, and M is greater than or equal to N.

30. A system comprising the module of claim 16, and one or more other electronic components electrically connected to the module.

31. The system of claim 30, further comprising a housing, the module and the other electronic components being mounted to the housing.

Claims (27)

1. a microelectronics Packaging, comprising:

Substrate, described substrate has relative first surface and second surface, and the multiple substrate contact at described first surface place and the multiple terminals at described second surface place, for described microelectronics Packaging being connected at least one parts of described package outside; And

First microelectronic element and the second microelectronic element, described first microelectronic element and the second microelectronic element have the front surface of the first surface in the face of described substrate respectively, each microelectronic element has multiple element contacts at front surface place described in it, described element contacts and the corresponding described substrate contact of each microelectronic element are connected, the described front surface portion of described second microelectronic element covers and is attached to the rear surface of described first microelectronic element

The described element contacts of wherein said first microelectronic element to be arranged in the battle array of face and with substrate contact flip-chip bonding described in first group, the described element contacts of described second microelectronic element is connected by substrate contact described in conducting block and second group.

2. microelectronics Packaging according to claim 1, the described element contacts of wherein said second microelectronic element protrudes from outside the lateral edges of described first microelectronic element.

3. microelectronics Packaging according to claim 1, at least one in wherein said first microelectronic element and the second microelectronic element comprises memory component.

4. microelectronics Packaging according to claim 3, also comprise the multiple lead-in wires extending to described terminal from substrate contact described at least some, wherein said lead-in wire can be used for carrying address signal with at least one in described first microelectronic element and the second microelectronic element to described memory component addressing.

5. microelectronics Packaging according to claim 1, the wherein signal of terminal described at least some between to can be used for carrying in each terminal described and described first microelectronic element and the second microelectronic element each or at least one in reference potential.

6. microelectronics Packaging according to claim 1, also comprises multiple 3rd microelectronic element, and each 3rd microelectronic element is electrically connected to described substrate.

7. microelectronics Packaging according to claim 6, wherein said multiple 3rd microelectronic element is arranged to stacked structure, and each described 3rd microelectronic element has the facing front surface of the front surface of described three microelectronic element adjacent with or rear surface or rear surface.

8. microelectronics Packaging according to claim 6, wherein said multiple 3rd microelectronic element is arranged to planar structure, and each described 3rd microelectronic element has the facing peripheral surface of the peripheral surface of described three microelectronic element adjacent with.

9. microelectronics Packaging according to claim 6, wherein said second microelectronic element comprises volatibility RAM, each described 3rd microelectronic element comprises non-volatile flash memory, and described first microelectronic element comprises the processor being mainly used in controlling external module and the data between described second microelectronic element and the 3rd microelectronic element and transmitting.

10. microelectronics Packaging according to claim 6, wherein said second microelectronic element comprises volatibility frame buffer memory element, and each described 3rd microelectronic element comprises non-volatile flash memory, and described first microelectronic element comprises graphic process unit.

11. 1 kinds of systems, comprise multiple microelectronics Packaging according to claim 1, circuit board and processor, the described terminal of described microelectronics Packaging is electrically connected with the plate contact of described circuit board, each microelectronics Packaging is used within the clock cycle, transmit N number of parallel data bit, described processor is used within the clock cycle, transmit M parallel data bit, and M is more than or equal to N.

12. 1 kinds of systems, comprise microelectronics Packaging according to claim 1, and are electrically connected to other electronic units one or more of described microelectronics Packaging.

13. systems according to claim 12, also comprise housing, and described microelectronics Packaging and other electronic units described are mounted to described housing.

14. 1 kinds of modules, comprising:

Module card, described module card has first surface, the edge contact of second surface and multiple parallel exposure, described edge contact is close to the edge of at least one in described first surface and second surface, for when described module inserts socket, the contact docking corresponding to socket, described module card has multiple card contacts on the first surface; And

First microelectronic element and the second microelectronic element, described first microelectronic element and the second microelectronic element have the front surface of the described first surface in the face of described module card respectively, each microelectronic element has multiple element contacts at front surface place described in it, described element contacts and the corresponding described card contact of each microelectronic element are connected, the described front surface portion of described second microelectronic element covers and is attached to the rear surface of described first microelectronic element

The described element contacts of wherein said first microelectronic element to be arranged in the battle array of face and with card contact flip-chip bonding described in first group, the described element contacts of described second microelectronic element is connected by card contact described in conducting block and second group.

15. modules according to claim 14, the described element contacts of wherein said second microelectronic element protrudes from outside the lateral edges of described first microelectronic element.

16. modules according to claim 14, wherein said edge contact is exposed at least one place in the described first surface of described module card or second surface.

17. modules according to claim 14, at least one in wherein said first microelectronic element and the second microelectronic element comprises memory component.

18. modules according to claim 17, also comprise the multiple lead-in wires extending to described edge contact from card contact described at least some, wherein said lead-in wire can be used for carrying address signal with at least one in described first microelectronic element and the second microelectronic element to described memory component addressing.

19. modules according to claim 14, the wherein signal of edge contact described at least some between to can be used for carrying in each edge contact described and described first microelectronic element and the second microelectronic element each or at least one in reference potential.

20. modules according to claim 14, also comprise multiple 3rd microelectronic element, and each 3rd microelectronic element is electrically connected to described module card.

21. modules according to claim 20, described multiple 3rd microelectronic element is arranged to stacked structure, and each described 3rd microelectronic element has the facing front surface of the front surface of described three microelectronic element adjacent with or rear surface or rear surface.

22. modules according to claim 20, described multiple 3rd microelectronic element is arranged to planar structure, and each described 3rd microelectronic element has the facing peripheral surface of the peripheral surface of described three microelectronic element adjacent with.

23. modules according to claim 20, wherein said second microelectronic element comprises volatibility RAM, each described 3rd microelectronic element comprises non-volatile flash memory, and described first microelectronic element comprises the processor being mainly used in controlling external module and the data between described second microelectronic element and the 3rd microelectronic element and transmitting.

24. modules according to claim 20, wherein said second microelectronic element comprises volatibility frame buffer memory element, and each described 3rd microelectronic element comprises non-volatile flash memory, and described first microelectronic element comprises graphic process unit.

25. 1 kinds of systems, comprise multiple module according to claim 14, circuit board and processor, the contact of the described exposure of described module be inserted into be electrically connected with described circuit board to plug receptacle, each module is used within the clock cycle, transmit N number of parallel data bit, described processor is used within the clock cycle, transmit M parallel data bit, and M is more than or equal to N.

26. 1 kinds of systems, comprise module according to claim 1, and are electrically connected to other electronic units one or more of described module.

27. systems according to claim 26, also comprise housing, and described module and other electronic units described are mounted to described housing.