CN104811164B - Triangular wave generating circuit with clock signal synchronization - Google Patents

Abstract

A triangular wave generating circuit with clock signal synchronization includes a capacitor, first to fourth constant current sources, a first switching unit, a second switching unit, a high and low level limiting unit, a clock signal generator, and a phase detection unit. The first and second constant current sources are used to charge the capacitor. The third and fourth constant current sources are used to discharge the capacitor. The phase detection unit is used to receive an externally supplied clock signal and the internal clock signal, and generate first and second phase signals according to the phase difference between the two. The second switching unit includes third and fourth switches, the third switch is used to respond to the first phase signal to control the coupling state of the second constant current source and the capacitor, and the fourth switch is used to respond to the second phase signal to control the coupling state of the fourth constant current source and the capacitor.

Description

Triangular Wave Generation Circuit with Clock Signal Synchronization

technical field

The invention relates to a triangular wave generating circuit, in particular to a triangular wave generating circuit synchronous with an external clock signal.

Background technique

The triangular wave generating circuit generates a triangular wave signal by charging and discharging a capacitor. The triangular wave generating circuit can be applied in many circuits, one of which is to convert the analog voice signal into a pulse width modulated signal in a D-type (class-D) power amplifier.

FIG. 1 is a known circuit 10 for generating a triangular wave signal VOUT by using a square wave signal VIN. The accuracy of the triangular wave signal will affect the performance of devices using the triangular wave signal, such as the performance of pulse width modulation (PWM) devices. In this figure, the switching frequency fsw of the triangular wave signal VOUT is equal to 1/(TU+TD), where TU is the rising time of the triangular wave signal VOUT from VL to VH, and TD is the falling time of the triangular wave signal VOUT from VH to VL. The rise time TU is equal to C×(VH−VL)/IC, where C is the capacitance of the capacitor C1 across the operational amplifier 12 and IC is the charging current provided by the current source I1. Similarly, the falling time TD is equal to C×(VH-VL)/ID, where ID is the discharge current provided by the current source I2. Assuming that IC and ID are equal, the switching frequency fsw is equal to IC/(2*C*(VH-VL)). From this equation, we know that the triangular wave switching frequency fsw is proportional to IC and ID, and inversely proportional to the triangular wave amplitude (VH-VL).

FIG. 2 is a schematic diagram of potential problems of the triangular wave generating circuit 10 of FIG. 1 . As shown in FIG. 2 , in problem 1, if the current source does not match, that is, the current IC is greater than ID or the current ID is greater than IC, the triangular wave signal VOUT will not switch at the predetermined limit peaks VH and VL. Similarly, problem 2 reveals the triangular wave waveform when the duty cycle of the square wave is not an ideal value. The reason why problem 2 often occurs is that the internal clock signal is not synchronized with the external clock signal. It is very important to synchronize the internal clock signal with the external clock signal, such as the D-type amplifier voice system application for 5.1 or 7.1 channels. If the switching frequencies are not the same, frequency jumps will appear in the sound band.

Accordingly, it is necessary to propose a triangular wave generating circuit to improve the above problems.

Contents of the invention

The invention provides a triangular wave generating circuit with clock signal synchronization. The triangular wave generating circuit includes a capacitor, a first constant current source, a second constant current source, a third constant current source, a fourth constant current source, a first switching unit, a second switching unit, a high /Low level limiting unit, a clock signal generator, and a phase detection unit. The first and second constant current sources are used to charge the capacitor. The third and fourth constant current sources are used to discharge the capacitor. The first switch unit includes a first switch and a second switch, and the first switch unit is used for controlling the coupling states of the first and third constant current sources and the capacitor in response to an internal clock signal. The high/low level limiting unit includes a first and a second comparing unit, the first comparing unit is used for comparing the triangular wave signal with a high level reference voltage, and when the triangular wave signal reaches the high level reference voltage When generating an output signal, the second comparison unit is used for comparing the triangular wave signal with a low-level reference voltage, and generating an output signal when the triangular wave signal reaches the low-level reference voltage. The clock signal generator is used for generating the internal clock signal in response to the output signal of the first comparison unit and the output signal of the second comparison unit. The phase detection unit is used to receive an externally supplied clock signal and the internal clock signal, and generate a first phase signal and a second phase signal according to a phase difference between the externally supplied clock signal and the internal clock signal. The second switch unit includes a third switch and a fourth switch, the third switch is used to control the coupling state of the second constant current source and the capacitor in response to the first phase signal, and the fourth switch The coupling state of the fourth constant current source and the capacitor is controlled in response to the second phase signal.

Description of drawings

FIG. 1 is a known circuit for generating a triangular wave signal from a square wave signal.

FIG. 2 is a schematic diagram of potential problems of the triangular wave generating circuit of FIG. 1 .

FIG. 3 shows a circuit diagram of a triangular wave signal generator according to an embodiment of the present invention.

FIG. 4 shows a possible operation waveform diagram of the phase detection unit shown in FIG. 3 .

FIG. 5 shows another possible operation waveform diagram of the phase detection unit shown in FIG. 3 .

FIG. 6 shows a waveform diagram of the triangular wave signal generator combined with an embodiment of the present invention.

FIG. 7 shows a waveform diagram of the triangular wave signal generator combined with another embodiment of the present invention.

FIG. 8 shows a circuit diagram of a triangular wave signal generator according to an embodiment of the present invention.

FIG. 9 shows a circuit diagram of the switched current arrays incorporating an embodiment of the present invention.

FIG. 10 shows a flowchart of the operation of the triangular wave signal generator according to an embodiment of the present invention.

【Symbol Description】

10 Triangular wave generating circuit

12 operational amplifiers

30, 30' triangle wave signal generator

32 switching unit

33 Second drive circuit

34 High and low level limiting circuit

342 comparators

344 Comparators

36 Internal clock signal generator

38 phase detection unit

82 Switching Current Array

84 switch current array

86 comparison circuit

C1 capacitor

I1-IN constant current source

M1, M2, M3, M4 switches

SW1-SWN switch

S100-S110 steps

detailed description

Certain terms are used throughout the specification and appended claims to refer to particular elements. Those skilled in the art should understand that manufacturers may use different terms to refer to the same component. This description and the appended claims do not use the difference in name as a way to distinguish components, but use the difference in function of components as a criterion for distinguishing. "Includes" mentioned throughout the specification and appended claims is an open-ended term, so it should be interpreted as "including but not limited to". In addition, the term "coupled" herein includes any direct and indirect means of electrical connection. Therefore, if it is described that a first device is coupled to a second device, it means that the first device may be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connection means.

FIG. 3 shows a circuit diagram of a triangular wave signal generator 30 according to an embodiment of the present invention. As shown in FIG. 3 , the triangular wave signal generator 30 includes a capacitor C1 , a pair of matching charging/discharging constant current sources I1 and I2 and a switching unit 32 . The term "matching" here means that the current values of the charging/discharging constant current sources I1 and I2 are substantially the same. The switching unit 32 includes two switches M1 and M2 controlled by an internal clock signal. The two switches M1 and M2 are switched in a complementary manner, so when the switch M1 is turned on, the switch M2 is turned off, and vice versa. In addition, when the switch M1 is turned on, the constant current source I1 is coupled to the capacitor C1. When the switch M2 is turned on, the constant current source I2 is coupled to the capacitor C1.

Referring to FIG. 3 , the triangular wave signal generator 30 further includes a high-low level limiting circuit 34 including two comparators 342 and 344 . The comparator 342 compares a signal VTRI on the capacitor C1 with a high-level reference voltage VH, and the comparator 342 compares the signal VTRI with a low-level reference voltage VL. The output signal CPH of the comparator 342 and the output signal CPL of the comparator 344 are provided to an internal clock signal generator 36 . In this embodiment, the signal generator 36 is an RS latch. The signal generator 36 provides an internal clock signal ICK to control the two switches M1 and M2 in the switching unit 32 according to the comparison result.

Referring to FIG. 3 , the triangular wave signal generator 30 further includes a pair of matching charging/discharging constant current sources I3 and I4 and a switching unit 33 . The switching unit 33 includes two switches M3 and M4. The switch M3 is controlled by an output signal DP of a phase detection unit 38 , and the switch M4 is controlled by an output signal DN of the phase detection unit 38 . When the switch M3 is turned on, the switch M4 is turned off, and vice versa. In addition, when the switch M3 is turned on, the constant current source I3 is coupled to the capacitor C1. When the switch M4 is turned on, the constant current source I4 is coupled to the capacitor C1.

As mentioned above, the operation of the switching unit 33 is controlled by the phase detection unit 38 . The phase detection unit 38 receives an externally supplied clock signal ECK and the internal clock signal ICK, and generates the phase signals DP and DN according to the phase difference between the clock signal ECK and the clock signal ICK. When the signal DP is at logic 0 level, the switch M3 in the switching unit 33 is turned on. When the signal DN is at logic 1 level, the switch M4 in the switching unit 33 is turned on.

FIG. 4 shows a possible operation waveform diagram of the phase detection unit 38 shown in FIG. 3. In FIG. 4, the phase of the external clock signal ECK leads the phase of the internal clock signal ICK, that is, the phase of the external clock signal ECK The rising edge is ahead of the rising edge of the internal clock signal ICK, and the falling edge of the external clock signal ECK is ahead of the falling edge of the internal clock signal ICK. When the rising edge of the external clock signal ECK is ahead of the rising edge of the internal clock signal ICK, the phase detection unit 38 generates the phase signal DP. When the falling edge of the external clock signal ECK is ahead of the falling edge of the internal clock signal ICK, the phase detection unit 38 generates the phase signal DN. Therefore, the width W1 of the phase signal DP and the width W2 of the phase signal DN are determined by the phase difference between the external clock signal ECK and the internal clock signal ICK.

FIG. 5 shows another possible operation waveform diagram of the phase detection unit 38 shown in FIG. 3. In FIG. 5, the phase of the external clock signal ECK lags behind the phase of the internal clock signal ICK, that is, the external clock signal ECK The rising edge of the internal clock signal ICK lags behind the rising edge of the internal clock signal ICK, and the falling edge of the external clock signal ECK lags behind the falling edge of the internal clock signal ICK. When the rising edge of the external clock signal ECK lags behind the rising edge of the internal clock signal ICK, the phase detection unit 38 generates the phase signal DP. When the falling edge of the external clock signal ECK lags behind the falling edge of the internal clock signal ICK, the phase detection unit 38 generates the phase signal DN. Therefore, the width W3 of the phase signal DP and the width W4 of the phase signal DN are determined by the phase difference between the external clock signal ECK and the internal clock signal ICK.

Referring now to FIG. 3 to FIG. 7 , the operation of the triangular wave signal generator 30 of the present invention is described, wherein FIG. 6 shows a waveform diagram of the triangular wave signal generator 30 according to an embodiment of the present invention. In this embodiment, the phase of the external clock signal ECK is ahead of the phase of the internal clock signal ICK.

Referring to FIG. 6, before time t1, when the clock signal ICK is logic 0 level, the capacitor C1 is charged by the current flowing through the constant current source I1, so that the voltage VTRI on the capacitor C1 increases linearly. At time t1, when the phase detection unit 38 detects the phase difference between the external clock signal ECK and the internal clock signal ICK, it will respond to the fact that the phase of the external clock signal ECK is ahead of the phase of the internal clock signal ICK To generate the phase signal DP, which causes the constant current source I3 to charge the capacitor C1. Since the slope of the rising segment of the triangular wave signal is proportional to the DC current flowing through the capacitor, the signal VTRI will quickly reach the high-level reference voltage VH at time t2. When the signal VTRI reaches the reference voltage VH, the output signal CPH of the comparator 342 will output a logic 1 level, so that the RS latch 36 outputs a clock signal ICK with a logic 1 level.

After time t2, the switches M1 and M3 are turned off, the switch M2 is turned on in response to the clock signal ICK, and the capacitor is discharged by the current flowing through the constant current source I2. Therefore, the voltage VTRI on the capacitor C1 will decrease linearly. At time t3, when the phase detection unit 38 detects the phase difference between the external clock signal ECK and the internal clock signal ICK, it will respond to the fact that the phase of the external clock signal ECK is ahead of the phase of the internal clock signal ICK To generate the phase signal DN, the constant current source I4 is added to the constant current source I2 to discharge the capacitor C1. Higher DC current values produce shorter ramp time intervals. Therefore, the signal VTRI will quickly reach the low-level reference voltage VL at time t4. When the signal VTRI reaches the reference voltage VL, the output signal CPL of the comparator 344 will output a logic 1 level, so that the RS latch 36 outputs a clock signal ICK with a logic 0 level.

The above operation will be performed repeatedly, so the voltage VTRI on the capacitor C1 will be generated in a triangular wave form. As mentioned above, the triangular wave signal generator 30 synchronizes the internal clock signal ICK with the externally supplied clock signal ECK by detecting the phase difference between the external clock signal ECK and the internal clock signal ICK. When the phase of the external clock signal ECK leads the phase of the internal clock signal ICK, the slope of the signal VTRI increases according to the detection result, thus shortening the ramp period. In this way, the internal clock signal ICK is synchronized with the externally supplied clock signal ECK after several cycles.

FIG. 7 shows a waveform diagram of the triangular wave signal generator 30 according to another embodiment of the present invention. In this embodiment, the phase of the external clock signal ECK lags behind the phase of the internal clock signal ICK.

Referring to FIG. 7 , before time t1 , the clock signal ICK is at logic 0 level, and the capacitor C1 is charged by the current flowing through the constant current source I1 , so that the voltage VTRI on the capacitor C1 increases linearly. At time t1, the signal VTRI will reach the high-level reference voltage VH, which makes the output signal CPH of the comparator 342 output a logic 1 level, and makes the RS latch 36 output a clock signal with a logic 1 level ICK. Therefore, the switch M1 is turned off and the switch M2 is turned on, so that the current source I2 is coupled to the capacitor C1. After time t1, the phase detection unit 38 detects that there is a phase difference between the external clock signal ECK and the internal clock signal ICK, and generates the phase signal DP according to the detection result, which will make the constant current source I3 coupled to to the capacitor C1. In this embodiment, the current value of the current source I3 is greater than the current value of the current source I2. Therefore, the capacitor C1 will be charged by the net current I3-I2.

The clock signal ECK goes to a logic 1 level at time t2, so the phase signal DP also returns to a logic 1 level. Then, the switch M3 is turned off, and the capacitor C1 is discharged by the current flowing through the constant current source I2, which causes the voltage VTRI on the capacitor C1 to decrease linearly. At time t3, the signal VTRI will reach the low-level reference voltage VL, which makes the output signal CPL of the ground comparator 344 output a logic 1 level, and allows the RS latch 36 to output a clock with a logic 0 level Signal ICK. Therefore, the switch M2 is turned off and the switch M1 is turned on, so that the current source I1 is coupled to the capacitor C1 . After time t3, the phase detection unit 38 detects that there is a phase difference between the external clock signal ECK and the internal clock signal ICK, and generates the phase signal DN according to the detection result, which will make the constant current source I4 start to Capacitor C1 is discharged. In this embodiment, the current value of the current source I4 is greater than the current value of the current source I1 . Therefore, the capacitor C1 will be charged by the net current I4-I1.

The clock signal ECK goes to a logic 0 level at time t4, so the phase signal DN also returns to a logic 0 level. Then, the switch M4 is turned off, and the capacitor is charged by the current flowing through the constant current source I1. The capacitor will be charged and discharged in a similar manner after time t5, so that the voltage VTRI on the capacitor C1 will generate a triangular wave.

As mentioned above, the triangular wave signal generator 30 synchronizes the internal clock signal ICK with the externally supplied clock signal ECK by detecting the phase difference between the external clock signal ECK and the internal clock signal ICK. When the phase of the external clock signal ECK lags behind the phase of the internal clock signal ICK, the capacitor C1 will maintain the previous charging/discharging state during the phase difference interval. Since the overall slope of the signal VTRI becomes gentler, the ramp period increases. In this way, the internal clock signal ICK is synchronized with the externally supplied clock signal ECK after several cycles.

In the above embodiment, the capacitor C1 is additionally charged and discharged by the constant current sources I3 and I4. However, in a different embodiment, this capacitor C1 can also be additionally charged and discharged by a variable current source during the phase difference interval. FIG. 8 shows a circuit diagram of a triangular wave signal generator 30' according to an embodiment of the present invention. Referring to FIG. 8, a comparison circuit 86 compares the pulse width of the phase signal DP with a predetermined time interval TSET to generate a digital code composed of a plurality of bits C0 to CN. At the same time, the comparison circuit 86 compares the pulse width of the phase signal DN with the predetermined time interval TSET to generate a digital code composed of a plurality of bits B0 to BN.

Referring to FIG. 8 , after receiving the digital bits C0 to CN, a switching current array 82 provides charging current according to the digital bits C0 to CN. A switching current array 84 provides discharge current according to the digital bits B0 to BN after receiving the digital bits B0 to BN. FIG. 9 shows a circuit diagram of the switched current arrays 82 and 84 incorporating an embodiment of the present invention. Referring to FIG. 9 , the switched current array 82 includes a plurality of identical current sources I1 to IN, and each current source delivers the same current I. The switched current array 82 further includes a plurality of switches SW1 to SWN corresponding to the plurality of current sources I1 to IN. For example, the switch SW1 is responsible for controlling the coupling state of the current source I1 and the capacitor C1. The circuit configuration of the switched current array 84 is similar to that of the current array 82 . Referring to FIG. 9 , the switched current array 84 includes a plurality of identical current sources I1 to IN, and each current source delivers the same current I. The switched current array 84 further includes a plurality of switches SW1 to SWN corresponding to the plurality of current sources I1 to IN.

FIG. 10 shows a flowchart of the operation of the triangular wave signal generator 30' according to an embodiment of the present invention. The process starts at step S100. Please refer to FIG. 8 to FIG. 10 for the following description. In step S102 , the phase detection unit 38 receives the external clock signal ECK and the internal clock signal ICK, and generates the phase signal DP according to the phase difference between them. In step S104, the comparison circuit 86 compares the pulse width of the phase signal DP with a predetermined time interval TSET to generate a plurality of digital bits C0 to CN. In one embodiment, the digital bits C0 to CN respond to the difference between the pulse width of the phase signal DP and the predetermined time interval TSET. In another embodiment, the comparison circuit 86 compares the pulse width of the phase signal DP with a plurality of predetermined time intervals TSET1 to TSETN to generate a plurality of digital bits C0 to CN.

Next, in step S106, if the pulse width of the phase signal DP is greater than the predetermined time interval TSET, the total current flowing through the current array 82 will increase to charge the capacitor C1. Then, the process returns to step S104. If the pulse width of the phase signal DP is smaller than the predetermined time interval TSET after the charging current is increased, the process ends.

Referring to FIGS. 8 to 10 , in an embodiment of the present invention, the capacitor C1 is initially charged and discharged by only one current source in the current array 82 and one current source in the current array 84 . Next, in step S106, if the pulse width of the phase signal DP is still greater than the predetermined time interval TSET (for example, 100 ns) after several clock cycles, another current source in the current array 82 is coupled to the capacitor C1 to increase the charging current. After several clock cycles, the comparison circuit 86 compares the pulse width of the phase signal DP with the predetermined time interval TSET again. If the pulse width of the phase signal DP is still greater than the predetermined time interval TSET, it means that the total charging current flowing through the current array 82 still cannot reduce the phase difference between the external clock signal ECK and the internal clock signal ICK, so the current Another switch in the array 82 is turned on to couple another current source to the capacitor C1 to increase the charging current. If the pulse width of the phase signal DP is still greater than the predetermined time interval TSET after several cycles, another switch in the current array 82 is turned on to couple another current source to the capacitor C1 to increase the charging current. The switches are continuously turned on to sequentially couple different current sources to the capacitor C1 to increase the charging current until the pulse width of the phase signal DP is less than the predetermined time interval TSET. In this way, the pulse width of the phase signal DP is less than the predetermined time interval TSET.

In the above embodiment, the switches SW1 to SWN in the current array 82 are turned on sequentially to increase the total charging current, while only the switch SW1 in the current array 84 is turned on to increase the discharge current. In another embodiment, the switches SW1 to SWN in the current array 84 are turned on sequentially to increase the total discharge current, while only the switch SW1 in the current array 82 is turned on to increase the charge current. However, in yet another embodiment, the switches SW1 to SWN in the current array 82 and the switches SW1 to SWN in the current array 84 are all turned on sequentially, so that according to the external clock signal ECK and the internal clock signal ICK The phase difference between them increases the total charge and discharge current. In this manner, the pulse width of the phase signal DP is gradually reduced until it is less than the predetermined time interval TSET.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be subject to the scope defined by the appended claims.

The technical content and technical features of the present invention have been disclosed above, but those skilled in the art may still make various substitutions and modifications based on the teaching and disclosure of the present invention without departing from the spirit of the present invention. Therefore, the protection scope of the present invention should not be limited to those disclosed in the embodiments, but should include various replacements and modifications that do not depart from the present invention, and are covered by the following claims.

Claims (9)

1. a kind of circuit for generating triangular wave with clock signal synchronization, including：

One capacitor, with an output end to provide a triangular signal；

First and second constant current sources, to be charged to the capacitor；

Third and fourth constant current source, to the capacitor discharge；

One first switch unit, comprising a first switch and a second switch, first switch unit is used in response to inside one Clock signal with control this first and the 3rd constant current source and the capacitor coupling access status；

One high/low level limiting unit, comprising one first and one second comparing unit, first comparing unit to compare this three Angle ripple signal and a high level reference voltage, and the output of generation one letter when the triangular signal reaches the high level reference voltage Number, second comparing unit is reached to compare the triangular signal and a low level reference voltage, and in the triangular signal An output signal is produced during the low level reference voltage；

One clock signal generator, to this of the output signal in response to first comparing unit and second comparing unit Output signal is to produce the internal clock signal；

One phase detection unit, is supplied to receive an outside supply clock signal and the internal clock signal, and according to the outside The phase difference value of clock signal and the internal clock signal is answered to produce a first phase signal and a second phase signal；And

One second switch unit, comprising one the 3rd switch and one the 4th switch, the 3rd switch is used in response to the first phase Signal is to control the coupling access status of second constant current source and the capacitor, and the 4th switch is used in response to the second phase Signal is to control the coupling access status of the 4th constant current source and the capacitor.

2. circuit for generating triangular wave according to claim 1, wherein when the rising edge of the outside supply clock signal is leading During the rising edge of the internal clock signal, the phase detection unit produces the first phase signal.

3. circuit for generating triangular wave according to claim 1, wherein being somebody's turn to do when the trailing edge of outside supply clock signal is leading During the trailing edge of internal clock signal, the phase detection unit produces the second phase signal.

4. circuit for generating triangular wave according to claim 1, the wherein current value of second constant current source are more than the 3rd The current value of constant current source, and when the rising edge of outside supply clock signal falls behind the rising edge of the internal clock signal, should Phase detection unit produces the first phase signal.

5. circuit for generating triangular wave according to claim 1, the wherein current value of the 4th constant current source be more than this first The current value of constant current source, and when the trailing edge of outside supply clock signal falls behind the trailing edge of the internal clock signal, should Phase detection unit produces the second phase signal.

6. circuit for generating triangular wave according to claim 1, in addition to：

One first comparing unit, pulse width and multiple predetermined time intervals to compare the first phase signal, and at this The pulse width of first phase signal produces one first digital code when being more than the predetermined time interval；And

One first switching electric current array, comprising multiple identical constant current sources and correspondingly to the multiple switch of the constant current source；

The constant current source wherein in the first switching electric current array is in response to first digital code to be sequentially coupled to the electricity Container.

7. circuit for generating triangular wave according to claim 1, in addition to：

One second comparing unit, pulse width and multiple predetermined time intervals to compare the second phase signal, and at this The pulse width of second phase signal produces one second digital code when being more than the predetermined time interval；And

One second switching electric current array, comprising multiple identical constant current sources and correspondingly to the multiple switch of the constant current source；

The constant current source wherein in the second switching electric current array is in response to second digital code to be sequentially coupled to the electricity Container.

8. circuit for generating triangular wave according to claim 1, in addition to：

One first comparing unit, pulse width and a predetermined time interval to compare the first phase signal, and according to this The pulse width of first phase signal and the phase difference value of the predetermined time interval produce one first digital code；And

One first switching electric current array, comprising multiple identical constant current sources and correspondingly to the multiple switch of the constant current source；

The constant current source wherein in the first switching electric current array is in response to first digital code to be sequentially coupled to the electricity Container.

9. circuit for generating triangular wave according to claim 1, in addition to：

One second comparing unit, pulse width and a predetermined time interval to compare the second phase signal, and according to this The pulse width of second phase signal and the phase difference value of the predetermined time interval produce one second digital code；And

One second switching electric current array, comprising multiple identical constant current sources and correspondingly to the multiple switch of the constant current source；

The constant current source wherein in the second switching electric current array is in response to second digital code to be sequentially coupled to the electricity Container.