CN104810371A - Semiconductor memory device and manufacturing method thereof - Google Patents
Semiconductor memory device and manufacturing method thereof Download PDFInfo
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- CN104810371A CN104810371A CN201410042210.7A CN201410042210A CN104810371A CN 104810371 A CN104810371 A CN 104810371A CN 201410042210 A CN201410042210 A CN 201410042210A CN 104810371 A CN104810371 A CN 104810371A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 98
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 229910052751 metal Inorganic materials 0.000 claims abstract description 205
- 239000002184 metal Substances 0.000 claims abstract description 205
- 239000000758 substrate Substances 0.000 claims abstract description 54
- 238000000034 method Methods 0.000 claims abstract description 38
- 239000010410 layer Substances 0.000 claims description 285
- 239000004020 conductor Substances 0.000 claims description 58
- 229910021332 silicide Inorganic materials 0.000 claims description 41
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 41
- 238000003860 storage Methods 0.000 claims description 39
- 238000007667 floating Methods 0.000 claims description 27
- 238000005530 etching Methods 0.000 claims description 20
- 239000011229 interlayer Substances 0.000 claims description 18
- 230000015572 biosynthetic process Effects 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 239000000428 dust Substances 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 230000008569 process Effects 0.000 abstract description 15
- 238000003475 lamination Methods 0.000 abstract 6
- 239000003795 chemical substances by application Substances 0.000 description 16
- 238000001259 photo etching Methods 0.000 description 16
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- 238000005468 ion implantation Methods 0.000 description 3
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- 238000007254 oxidation reaction Methods 0.000 description 3
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- 238000000151 deposition Methods 0.000 description 2
- 230000009931 harmful effect Effects 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
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Abstract
Disclosed are a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes a plurality of double-transistor flash memory units. Each double-transistor flash memory unit includes semiconductor substrate and discrete memory transistor grid electrode lamination structures and selection transistor grid electrode lamination structures, which are on the semiconductor substrate; first doped areas between adjacent selection transistor grid electrode lamination structures and in the semiconductor substrate; second doped areas between adjacent memory transistor grid electrode lamination structures in the semiconductor substrate; first metal plugs on the memory transistor grid electrode lamination structures; second metal plugs on the selection transistor grid electrode lamination structures; first conductive layers and third metal plugs sequentially on the first doped areas; and second conductive layers and fourth metal plugs sequentially on the second doped areas. The semiconductor memory device is capable of reducing manufacturing difficulty of metal plugs and simplifying structural design of a corresponding active source beneath a source electrode so that device miniaturization and process simplification of the device are facilitated.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of semiconductor storage unit and preparation method thereof.
Background technology
Flash memory component due to have can repeatedly carry out data stored in actions such as, reading, erasings, and stored in the data advantage that also can not disappear after a loss of power, so become a kind of nonvolatile memory element that personal computer and electronic equipment extensively adopt.
Wherein, pair transistor flash cell (two-transistor flash memory cell) uses selects transistor (forming two transistor units), make device break away from thus common the crossing of monocrystal stacked gate pole unit wipe and be subject to BTBT(at read-out device can with tunnelling) problem disturbed.
In conjunction with reference to shown in figure 1 and Fig. 2, in prior art, semiconductor storage unit can comprise multiple pair transistor flash cell, and each pair transistor flash cell can comprise:
Include the Semiconductor substrate 10 of source region (not shown);
Memory transistor gate stack structure, comprise successively from bottom to up: be positioned at the floating gate dielectric layer 21 in described Semiconductor substrate 10, floating boom (Floating Gate, FG) 31, control gate dielectric layer 41 and control gate (Control Gate, CG) 51, also comprise the first side wall 61 being simultaneously positioned at floating gate dielectric layer 21 side, floating boom 31 side, control gate dielectric layer 41 side and control gate 51 side;
Select transistor gate stack structure, comprise successively from bottom to up: be positioned at the selection gate dielectric layer 22 in described Semiconductor substrate 10 and select grid (Select Gate, SG) 32, also comprise the second side wall 62 being positioned at simultaneously and selecting gate dielectric layer 22 side and select grid 32 side;
The first doped region 11 in active area between adjacent selection transistor gate stack structure, its drain electrode as pair transistor flash cell (Drain);
The second doped region 13 in active area between adjacent memory transistor gate stack structure, its source electrode as pair transistor flash cell (Source);
The 3rd doped region 15 in active area between adjacent selection transistor gate stack structure and memory transistor gate stack structure, it is as the interpole of pair transistor flash cell;
Be positioned at the first metal silicide 71 and the first metal plug 81 on control gate 51 successively, for drawing control end;
Be positioned at the second metal silicide 72 and the second metal plug 82 selected on grid 32 successively, for drawing selecting side;
Be positioned at the 3rd metal silicide 73 on the first doped region 11 and the 3rd metal plug 83 successively, for drawing drain terminal;
Be positioned at the 4th metal silicide 74 on the second doped region 13 and the 4th metal plug 84 successively, for drawing source;
Interlayer dielectric layer 90, is positioned at Semiconductor substrate 10, memory transistor gate stack structure, selects on transistor gate stack structure and each metal silicide, the upper surface flush of its upper surface and each metal plug.
But along with the continuous reduction of device size, there is following problem in said structure:
First, the depth-to-width ratio of the 3rd metal plug 83 and the 4th metal plug 84 is greater than the depth-to-width ratio of the first metal plug 81 and the second metal plug 82, and along with the continuous reduction of metal plug size, the manufacture difficulty of the 3rd metal plug 83 and the 4th metal plug 84 is increasing.
The second, all need reserved enough distances between the second adjacent metal plug 82 and the 3rd metal plug 83 and between the first adjacent metal plug 81 and the 4th metal plug 84, be finally unfavorable for the miniaturization of device.This is because: on the one hand, when writing flash memory or wiping process, need to apply high voltage, so need to prevent from producing electrical connection between adjacent metal plug, owing to all needing in the forming process of the 3rd metal plug 83 and the 4th metal plug 84 to adopt etching technics, and the depth-to-width ratio of the 3rd metal plug 83 and the 4th metal plug 84 is all larger, need strictly to aim at, therefore manufacture craft requires higher; On the other hand, owing to easily producing deviation in manufacturing process, thus when in interlayer dielectric layer, etching forms the through hole corresponding with the 3rd metal plug 83, remove second side wall 62 adjacent with described 3rd metal plug 83 possibly simultaneously, when in interlayer dielectric layer, etching forms the through hole corresponding with the 4th metal plug 84, remove first side wall 61 adjacent with described 4th metal plug 84 possibly simultaneously, and then cause device failure.
3rd, need the neck portion design (necking design) of carrying out active area, namely the pair transistor flash cell being positioned at same row different lines needs common-source 13, therefore need active area corresponding below source electrode 13 in the multiple pair transistor flash cells by same a line different lines to link together, thus add structure and the process complexity of active area.
Summary of the invention
The problem that the present invention solves is to provide a kind of semiconductor storage unit and preparation method thereof, can reduce the manufacture difficulty of metal plug, simplifies the structural design of active area corresponding below source electrode, is beneficial to the miniaturization of device and the simplification of technique.
For solving the problem, the invention provides a kind of semiconductor storage unit, comprising multiple pair transistor flash cell, each described pair transistor flash cell comprises:
Semiconductor substrate;
Be positioned at memory transistor gate stack structure discrete in described Semiconductor substrate and select transistor gate stack structure;
The first doped region in described Semiconductor substrate between adjacent described selection transistor gate stack structure;
The second doped region in described Semiconductor substrate between adjacent described memory transistor gate stack structure;
Be positioned at structural first metal plug of described memory transistor gate stack;
Be positioned at structural second metal plug of described selection transistor gate stack;
Be positioned at the first conductive layer on described first doped region and the 3rd metal plug successively;
Be positioned at the second conductive layer on described second doped region and the 4th metal plug successively.
For solving the problem, present invention also offers a kind of manufacture method of semiconductor storage unit, comprising:
Semiconductor substrate is provided;
Form discrete memory transistor gate stack structure on the semiconductor substrate and select transistor gate stack structure, adjacent described memory transistor gate stack structure and described selection transistor gate stack structure contact;
Form the first doped region in described Semiconductor substrate between adjacent described selection transistor gate stack structure, in the described Semiconductor substrate between adjacent described memory transistor gate stack structure, form the second doped region;
Described first doped region forms the first conductive layer, and form the second conductive layer on described second doped region;
Described first conductive layer, described second conductive layer, described memory transistor gate stack structure and described selection transistor gate stack structure form interlayer dielectric layer;
The 4th metal plug being positioned at structural first metal plug of described memory transistor gate stack, being positioned at structural second metal plug of described selection transistor gate stack, being positioned at the 3rd metal plug on described first conductive layer and being positioned on described second conductive layer is formed in described interlayer dielectric layer.
Compared with prior art, technical scheme of the present invention has the following advantages:
First, between the first doped region and the 3rd metal plug, increase by the first conductive layer, between the second doped region and the 4th metal plug, increase by the second conductive layer, be equivalent to raise the first doped region and the second doped region, reduce the degree of depth of the 3rd metal plug and the 4th metal plug, thus the difficulty of making the 3rd metal plug and the 4th metal plug can be reduced.
The second, on the one hand, the first conductive layer and groove corresponding to the second conductive layer form self-assembling formation when selecting transistor gate stack structure and memory transistor gate stack structure, and therefore formation process is fairly simple, does not relate to the problem of aligning; On the other hand, because the first conductive layer replaces the 3rd metal plug and the side wall close contact selected in transistor gate stack structure, second conductive layer replaces the side wall close contact in the 4th metal plug and memory transistor gate stack structure, therefore when etching formation the 3rd metal plug and the 4th metal plug, even if there is deviation in technique, also harmful effect can not be produced, so the present invention can reduce the distance between the second adjacent metal plug and the 3rd metal plug and between the first adjacent metal plug and the 4th metal plug to described side wall.
3rd, the second conductive layer being positioned at the multiple pair transistor flash cells in same wordline links together, thus without the need to carrying out the neck portion design of active area, finally greatly reduces structure and the process complexity of active area below source electrode.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of semiconductor storage unit in prior art;
Fig. 2 is the plan structure schematic diagram of semiconductor storage unit in prior art;
Fig. 3 to Figure 10 is the schematic diagram of the manufacture method of the semiconductor storage unit that one embodiment of the invention provides;
Figure 11 to Figure 16 is the schematic diagram of the manufacture method of the semiconductor storage unit that another embodiment of the present invention provides.
Embodiment
As described in background, prior art the 3rd metal plug is located immediately on the first doped region, 4th metal plug is located immediately on the second doped region, thus along with the continuous reduction of device size, the manufacture difficulty of the 3rd metal plug and the 4th metal plug is increasing, 3rd metal plug and the second adjacent metal plug and all need reserved enough distances between the 4th metal plug and the first adjacent metal plug, active area below source electrode needs to carry out neck portion design, finally cause the manufacture craft difficulty of semiconductor storage unit large, the complex structure of the active area below source electrode, and be unfavorable for the miniaturization of device.
For the problems referred to above, the invention provides a kind of semiconductor storage unit and preparation method thereof, it increases by the first conductive layer between the first doped region and the 3rd metal plug, between the second doped region and the 4th metal plug, increase by the second conductive layer, thus the manufacture difficulty of metal plug can be reduced, and be beneficial to the miniaturization of device, no longer can need the physical connection design carrying out active area corresponding below source electrode simultaneously.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
One embodiment of the invention provides a kind of manufacture method of semiconductor storage unit, can comprise the following steps:
Step S11, Semiconductor substrate is provided, form discrete memory transistor gate stack structure on the semiconductor substrate and select transistor gate stack structure, adjacent described memory transistor gate stack structure and described selection transistor gate stack structure contact;
Step S12, forms the first doped region in the described Semiconductor substrate between adjacent described selection transistor gate stack structure, forms the second doped region in the described Semiconductor substrate between adjacent described memory transistor gate stack structure;
Step S13, described Semiconductor substrate, described memory transistor gate stack structure and described selection transistor gate stack structure form conductive material layer, the upper surface of described memory transistor gate stack structure, higher than the upper surface of described selection transistor gate stack structure, is positioned at the upper surface of upper surface higher than described memory transistor gate stack structure of the described conductive material layer of described selection transistor gate stack structure;
Step S14, carries out planarization to described conductive material layer, until make the upper surface flush of the upper surface of remaining described conductive material layer and described memory transistor gate stack structure;
Step S15, etching processing is carried out to remain the conductive material layer be positioned on described first doped region and described second doped region to remaining described conductive material layer, to form the first conductive layer on described first doped region, and form the second conductive layer on described second doped region;
Step S16, described first conductive layer, described second conductive layer, described memory transistor gate stack structure and described selection transistor gate stack structure form interlayer dielectric layer;
Step S17, forms the 4th metal plug being positioned at structural first metal plug of described memory transistor gate stack, being positioned at structural second metal plug of described selection transistor gate stack, being positioned at the 3rd metal plug on described first conductive layer and being positioned on described second conductive layer in described interlayer dielectric layer.
The present embodiment is after formation first doped region and the second doped region, in Semiconductor substrate, memory transistor gate stack structure and selection transistor gate stack structure form the thicker conductive material layer of one deck, and then by carrying out planarization and etching processing to this conductive material layer, remain the conductive material layer be positioned on the first doped region and the second doped region, thus on the first doped region, form the first conductive layer and form the second conductive layer on the second doped region, and then on the first conductive layer, form the 3rd metal plug and form the 4th metal plug on the second conductive layer, namely the first doped region and the second doped region has been raised, reduce the degree of depth of the 3rd metal plug and the 4th metal plug, eventually reduce the difficulty of making the 3rd metal plug and the 4th metal plug, and the distance reduced between the second adjacent metal plug and the 3rd metal plug and between the first adjacent metal plug and the 4th metal plug, and the neck portion design of active area below source electrode can be eliminated by making the second conductive layer of the multiple pair transistor flash cells be positioned in same wordline link together, to reduce structure and the process complexity of active area below source electrode.
Shown in figure 3, the Semiconductor substrate 101 comprising active area is provided, described Semiconductor substrate 101 is formed discrete memory transistor gate stack structure and selects transistor gate stack structure, the upper surface of memory transistor gate stack structure is higher than the upper surface selecting transistor gate stack structure.
Wherein: memory transistor gate stack structure comprises from bottom to up successively: floating gate dielectric layer 211, floating boom 311, control gate dielectric layer 411, control gate 511 and be positioned at the first side wall 611 of floating gate dielectric layer 211 side, floating boom 311 side, control gate dielectric layer 411 side and control gate 511 side simultaneously, transistor gate stack structure is selected to comprise successively from bottom to up: to select gate dielectric layer 221, select grid 321 and be positioned at the second side wall 621 selected gate dielectric layer 221 side and select grid 321 side simultaneously, adjacent described first side wall 611 contacts with described second side wall 621, thus adjacent memory transistor gate stack structure and selection transistor gate stack structure contact, namely gap is not had between the two, only there is gap and formed between adjacent memory transistor gate stack structure there is gap between groove and adjacent selection transistor gate stack structure and form groove.
In the present embodiment, the material of floating boom 311, control gate 511 and selection grid 321 can be all polysilicon, described floating gate dielectric layer 211, control gate dielectric layer 411 and selection gate dielectric layer 221 can be single layer structure, also can be sandwich construction (as: oxide-nitride-oxide).
It should be noted that, before formation first side wall 611, with memory transistor gate stack structure for mask, light dope ion implantation can also be carried out to form light doping section to the Semiconductor substrate 101 of memory transistor gate stack structure periphery; Before formation second side wall 621, to select transistor gate stack structure for mask, light dope ion implantation can also be carried out to form light doping section to the Semiconductor substrate 101 of adjacent selection transistor gate stack structure periphery.Form the 3rd doped region 151 in Semiconductor substrate 101 simultaneously between adjacent described selection transistor gate stack structure and described memory transistor gate stack structure, it is as the interpole of pair transistor flash cell.
Wherein, described selection grid 321 can be formed with described control gate 511 simultaneously, thus can Simplified flowsheet step further.
In order to ensure follow-up carry out planarization and etching processing time, memory transistor gate stack structure can be stopped at better and select in transistor gate stack structure, the present embodiment can form the first hard mask layer 631 at the upper surface of control gate 511, and selecting the upper surface of grid 321 to form the second hard mask layer 641, described first side wall 611 is also positioned at the side of the first hard mask layer 631, and the second side wall 621 is also positioned at the side of the second hard mask layer 641.
The material of described first hard mask layer 631 and described second hard mask layer 641 can be one or more of silicon nitride, silica or silicon oxynitride, and its thickness range can be 200 dust ~ 1000 dusts.
It should be noted that, in other embodiments of the invention, when the conductive material layer of follow-up formation is different with the material of control gate, the first hard mask layer 631 can be omitted; When the conductive material layer of follow-up formation is different from selecting the material of grid 321, the second hard mask layer 641 can be omitted.In addition, even if conductive material layer is identical with selecting the material of grid 321, because etching technics ratio is easier to control, therefore the second hard mask layer 641 can also be omitted.
Continue with reference to shown in figure 3, after formation first side wall 611 and the second side wall 621, by the mode of ion implantation, form the first doped region 111 in the described Semiconductor substrate 101 between adjacent described selection transistor gate stack structure, it is as the drain electrode of pair transistor flash cell; Form the second doped region 131 in described Semiconductor substrate 101 between adjacent described memory transistor gate stack structure, it is as the source electrode of pair transistor flash cell.
The forming process of above-mentioned doped region is known for those skilled in the art, does not repeat them here.
Then with reference to shown in figure 4, the first doped region 131, first, hard mask layer 631, second hard mask layer 641, first doped region 111, second side wall 611 and the second side wall 621 form conductive material layer 651.
The material of described conductive material layer 651 can be any one electric conducting material, as: tungsten, polysilicon etc.
In the present embodiment, the material of conductive material layer 651 is polysilicon, follow-uply conveniently carry out planarization and etching processing, it can adopt furnace process to be formed, thus uniformity is very good, guarantee to be filled in well in the groove on the first doped region 111 and the groove on the second doped region 131.
Because the upper surface of memory transistor gate stack structure is higher than the upper surface selecting transistor gate stack structure, therefore be positioned at the structural conductive material layer of memory transistor gate stack 651 also higher than the structural conductive material layer 651 of selection transistor gate stack, and need guarantee to be positioned at the upper surface of upper surface higher than memory transistor gate stack structure of the structural conductive material layer 651 of selection transistor gate stack.
Carry out planarization for the ease of follow-up, the upper surface of described first mask layer 631 can 1000 dust ~ 2000 dusts lower than the upper surface of the described conductive material layer 651 being positioned at described selection transistor gate stack superstructure.In other embodiments, when omission the first hard mask layer 631, be then upper surface 1000 dust ~ 2000 dusts lower than the upper surface of the conductive material layer 651 being positioned at described selection transistor gate stack superstructure of memory transistor gate stack structure.
Described conductive material layer 651 forms self-assembling formation when selecting transistor gate stack structure and memory transistor gate stack structure, and therefore formation process is fairly simple, does not relate to the problem of aligning.
Then with reference to shown in figure 5, cmp (CMP) is carried out to the conductive material layer 651 shown in Fig. 4, until the upper surface making remaining conductive material layer 731 on the upper surface of remaining conductive material layer 661 on the first doped region 111, the second doped region 131 all with the upper surface flush of the first hard mask layer 631.
Then with reference to shown in figure 6, the conductive material layer 661 shown in Fig. 5 forms first photoetching agent pattern 681 corresponding with the first doped region 111 and second photoetching agent pattern 691 corresponding with the second doped region 131.
The width L1 of described first photoetching agent pattern 681 can be equal to or greater than the width of the first doped region 111, thus the mean breadth of the first conductive layer of follow-up formation can be equal to or greater than the width of the first doped region 111.
It should be noted that, in other embodiments of the invention, described second photoetching agent pattern 691 can be positioned on the second doped region 131, first hard mask layer 631 and the first side wall 611 simultaneously.
Then with reference to shown in figure 7, for mask, described conductive material layer 661 is etched with the first photoetching agent pattern 681 and the second photoetching agent pattern 691 in Fig. 6, to remove the conductive material layer 661 be positioned on described second hard mask layer 641 and the second side wall 621.
Continue with reference to shown in figure 7, remove the first photoetching agent pattern 681, second photoetching agent pattern 691, first hard mask layer 631 and the second hard mask layer 641 in Fig. 6, thus the residual conductive material layer 701 on the first doped region 111 is as the first conductive layer, the residual conductive material layer 731 on the second doped region 131 is as the second conductive layer.
In the present embodiment, the first conductive layer is identical with the height of the second conductive layer, and upper surface is simultaneously higher than the selection upper surface of grid 321 and the upper surface of control gate 511.
It should be noted that, when omission the second hard mask layer, the upper surface of the first conductive layer and the second conductive layer and the upper surface flush of control gate 511.
Described second conductive layer being positioned at the multiple pair transistor flash cells in same wordline in the present embodiment can link together, thus without the need to carrying out the neck portion design of active area, finally greatly reduces structure and the process complexity of active area below source electrode.
Then with reference to shown in figure 8, the control gate 511 of memory transistor gate stack structure is formed the first metal silicide 811, the selection grid 321 selecting transistor gate stack structure form the second metal silicide 821, first conductive layer forms the 3rd metal silicide 801, the second conductive layer forms the 4th metal silicide 831.
Then with reference to shown in figure 9, interlayer dielectric layer 951 is formed to cover the first metal silicide 811, second metal silicide 821, the 3rd metal silicide 801, the 4th metal silicide 831, described first conductive layer, described second conductive layer, described memory transistor gate stack structure and described selection transistor gate stack structure by depositing operation.
Then with reference to shown in Figure 10, by to etch and the technique such as filling forms the first metal plug 911 being positioned at described first metal silicide 811, the second metal plug 921 be positioned on described second metal silicide 821, the 4th metal plug 931 that is positioned at the 3rd metal plug 901 on described 3rd metal silicide 801 and is positioned on described 4th metal silicide 831, described first metal plug 911, second metal plug 921, the 3rd metal plug 901 and the upper surface of the 4th metal plug 931 and the upper surface flush of interlayer dielectric layer 951 in interlayer dielectric layer 951.
Described first metal plug 911 is for drawing control end, and described second metal plug 921 is for drawing selecting side, and described 3rd metal plug 901 is for drawing drain terminal, and described 4th metal plug 931 is for drawing source.
The present embodiment increases by the first conductive layer between the first doped region 111 and the 3rd metal plug 901, between the second doped region 131 and the 4th metal plug 931, increase by the second conductive layer, be equivalent to raise the first doped region 111 and the second doped region 131, reduce the degree of depth of the 3rd metal plug 901 and the 4th metal plug 931, thus the difficulty of making the 3rd metal plug 901 and the 4th metal plug 931 can be reduced.
In addition, due to the first conductive layer and the second side wall 621 close contact, second conductive layer and the first side wall 611 close contact, therefore when etching formation the 3rd metal plug 901 and the 4th metal plug 931, even if there is deviation in technique, also the present embodiment harmful effect can not be produced to the first side wall 611 and the second side wall 621, so can reduce the distance between the second adjacent metal plug 921 and the 3rd metal plug 901 and between the first adjacent metal plug 911 and the 4th metal plug 931.
Another embodiment of the present invention also provides a kind of manufacture method of semiconductor storage unit, comprising:
Step S21, Semiconductor substrate is provided, form discrete memory transistor gate stack structure on the semiconductor substrate and select transistor gate stack structure, adjacent described memory transistor gate stack structure and described selection transistor gate stack structure contact, and the upper surface of described memory transistor gate stack structure is higher than the upper surface of described selection transistor gate stack structure;
Step S22, forms the first doped region in the described Semiconductor substrate between adjacent described selection transistor gate stack structure, forms the second doped region in the described Semiconductor substrate between adjacent described memory transistor gate stack structure;
Step S23, described Semiconductor substrate, described memory transistor gate stack structure and described selection transistor gate stack structure form conductive material layer, bottom anti-reflection layer and low temperature oxide layer, the upper surface flush of described bottom anti-reflection layer successively;
Step S24, successively etching processing is carried out to described low temperature oxide layer, described bottom anti-reflection layer and described conductive material layer until only remain the conductive material layer be positioned on described first doped region and described second doped region, to form the first conductive layer on described first doped region, and form the second conductive layer on described second doped region;
Step S25, described first conductive layer, described second conductive layer, described memory transistor gate stack structure and described selection transistor gate stack structure form interlayer dielectric layer;
Step S26, forms the 4th metal plug being positioned at structural first metal plug of described memory transistor gate stack, being positioned at structural second metal plug of described selection transistor gate stack, being positioned at the 3rd metal plug on described first conductive layer and being positioned on described second conductive layer in described interlayer dielectric layer.
The present embodiment is after formation first doped region and the second doped region, in Semiconductor substrate, memory transistor gate stack structure and selection transistor gate stack structure form layer of conductive material layer successively, the bottom anti-reflection layer of one deck upper surface flush and low temperature oxide layer, and then the conductive material layer be positioned on the first doped region and the second doped region is only remained by etching processing, to form the first conductive layer and form the second conductive layer on the first doped region on the second doped region, and then on the first conductive layer, form the 3rd metal plug and form the 4th metal plug on the second conductive layer, namely the first doped region and the second doped region has been raised, reduce the degree of depth of the 3rd metal plug and the 4th metal plug, eventually reduce the difficulty of making the 3rd metal plug and the 4th metal plug, and the distance reduced between the second adjacent metal plug and the 3rd metal plug and between the first adjacent metal plug and the 4th metal plug, and by making the second conductive layer of the multiple pair transistor flash cells in same wordline link together the structure and process complexity that reduce active area below source electrode.
With reference to shown in Figure 11, the Semiconductor substrate 102 comprising active area is provided, described Semiconductor substrate 102 is formed discrete memory transistor gate stack structure and selects transistor gate stack structure, the upper surface of memory transistor gate stack structure is higher than the upper surface selecting transistor gate stack structure, and forming the first doped region 112 in described Semiconductor substrate 102 between adjacent described selection transistor gate stack structure, it is as the drain electrode of pair transistor flash cell; Form the second doped region 132 in described Semiconductor substrate 102 between adjacent described memory transistor gate stack structure, it is as the source electrode of pair transistor flash cell; Form the 3rd doped region 152 in Semiconductor substrate 102 between adjacent described selection transistor gate stack structure and described memory transistor gate stack structure, it is as the interpole of pair transistor flash cell.
Wherein: memory transistor gate stack structure comprises from bottom to up successively: floating gate dielectric layer 212, floating boom 312, control gate dielectric layer 412, control gate 512 and be positioned at the first side wall 612 of floating gate dielectric layer 212 side, floating boom 312 side, control gate dielectric layer 412 side and control gate 512 side simultaneously; Transistor gate stack structure is selected to comprise successively from bottom to up: select gate dielectric layer 222, select grid 322 and be positioned at the second side wall 622 selected gate dielectric layer 222 side and select grid 322 side simultaneously, adjacent described first side wall 612 contacts with described second side wall 622.
In order to ensure follow-up carry out planarization and etching processing time, memory transistor gate stack structure can be stopped at better and select in transistor gate stack structure, the present embodiment can form the first hard mask layer 632 at the upper surface of control gate 512, and selecting the upper surface of grid 322 to form the second hard mask layer 642, described first side wall 612 is also positioned at the side of the first hard mask layer 632, and the second side wall 622 is also positioned at the side of the second hard mask layer 642.
Concrete steps corresponding to Figure 11 can the step of reference diagram 3 correspondence, does not repeat them here.
Then with reference to shown in Figure 12, the first doped region 132, first, hard mask layer 632, second hard mask layer 642, first doped region 112, second side wall 612 and the second side wall 622 form conductive material layer 672, bottom anti-reflection layer 682 and low temperature oxide layer 692 successively.
The material of described conductive material layer 672 can be any one electric conducting material, as: tungsten, polysilicon etc.
In the present embodiment, the material of conductive material layer 672 is polysilicon, follow-uply conveniently carry out etching processing, it can adopt furnace process to be formed, thus uniformity is very good, guarantees to be filled in well in the groove on the first doped region 112 and the groove on the second doped region 132.
In the present embodiment, the Thickness Ratio of conductive material layer 672 is thinner, be positioned at the upper surface of upper surface lower than memory transistor gate stack structure of the structural conductive material layer 672 of selection transistor gate stack, and the upper surface of described memory transistor gate stack structure can 500 dust ~ 1000 dusts lower than the upper surface of the described conductive material layer 672 above it.
Described bottom anti-reflection layer 682 can adopt spin coating proceeding to be formed, thus its upper surface flush, the thickness being positioned at the described bottom anti-reflection layer 682 of described memory transistor gate stack structure upper surface can be greater than 1000 dusts.
Described low temperature oxide layer 692 is as the hard mask of subsequent etching, and its thickness range can be greater than 300 dusts.
Then, low temperature oxide layer 692 forms the first photoetching agent pattern (not shown) corresponding with the first doped region 112 and the second photoetching agent pattern (not shown) corresponding with the second doped region 132, and with the first photoetching agent pattern and the second photoetching agent pattern for mask, etch described low temperature oxide layer, form low-temperature oxidation layer pattern; Then described first photoetching agent pattern and the second photoetching agent pattern is removed, with described low-temperature oxidation layer pattern for mask, etch described bottom anti-reflection layer 682, form bottom anti-reflective layer pattern, in the process of etching bottom anti-reflecting layer 682, described low-temperature oxidation layer pattern can be removed; Then with described bottom anti-reflective layer pattern for mask, etch described conductive material layer 672, thus only remain the conductive material layer that is positioned on the first doped region 112 as the first conductive layer 702 and the conductive material layer be positioned on the second doped region 132 as the second conductive layer 732, described bottom anti-reflective layer pattern can be removed in the process of etch conductive layer; Then, remove the first hard mask layer 632 and the second hard mask layer 642 in Figure 12, thus obtain the structure shown in Figure 13.
In the present embodiment, the upper surface of the first conductive layer 702 is lower than the upper surface of the second conductive layer 732, but the upper surface of the first conductive layer 702 is higher than the upper surface selecting grid 322, and the upper surface of the second conductive layer 732 is higher than the upper surface of control gate 512.
The width of the first conductive layer 702 described in the present embodiment equals the width of described first doped region 112, and the width of described second conductive layer 732 equals the width of described second doped region 132.
It should be noted that, in other embodiments of the invention, the width of described first photoetching agent pattern can also be greater than the width of described first doped region 112, the width of described second photoetching agent pattern also can be greater than the width of described second doped region 132, thus the mean breadth of described first conductive layer 702 can be greater than the width of described first doped region 112, the mean breadth of described second conductive layer 732 can be greater than the width of described second doped region 132.
Then with reference to shown in Figure 14, the control gate 512 of memory transistor gate stack structure is formed the first metal silicide 812, the selection grid 322 selecting transistor gate stack structure form the second metal silicide 822, first conductive layer 702 forms the 3rd metal silicide 802, the second conductive layer 732 forms the 4th metal silicide 832.
Then with reference to shown in Figure 15, interlayer dielectric layer 952 is formed to cover the first metal silicide 812, second metal silicide 822, the 3rd metal silicide 802, the 4th metal silicide 832, described first conductive layer 702, described second conductive layer 732, described memory transistor gate stack structure and described selection transistor gate stack structure by depositing operation.
Then with reference to shown in Figure 16, etching and the technique such as filling is adopted in interlayer dielectric layer 952, to form the first metal plug 912 being positioned at described first metal silicide 812, the second metal plug 922 be positioned on described second metal silicide 822, the 4th metal plug 932 that is positioned at the 3rd metal plug 902 on described 3rd metal silicide 802 and is positioned on described 4th metal silicide 832, described first metal plug 912, second metal plug 922, the 3rd metal plug 902 and the upper surface of the 4th metal plug 932 and the upper surface flush of interlayer dielectric layer 952.
Described first metal plug 912 is for drawing control end, and described second metal plug 922 is for drawing selecting side, and described 3rd metal plug 902 is for drawing drain terminal, and described 4th metal plug 932 is for drawing source.
The present embodiment can reduce the manufacture difficulty of the 3rd metal plug 902 and the 4th metal plug 932 equally, and the distance that can reduce between the second adjacent metal plug 922 and the 3rd metal plug 902 and between the first adjacent metal plug 912 and the 4th metal plug 932, be namely beneficial to the miniaturization of device.In addition, the second conductive layer 732 of the multiple pair transistor flash cells be positioned in same wordline is linked together, thus without the need to carrying out the neck portion design of active area, to simplify the structure of active area corresponding below source electrode.
Accordingly, the embodiment of the present invention additionally provides a kind of semiconductor storage unit, and it can comprise multiple pair transistor flash cell, and each described pair transistor flash cell can comprise:
Semiconductor substrate;
Be positioned at memory transistor gate stack structure discrete in described Semiconductor substrate and select transistor gate stack structure;
The first doped region in described Semiconductor substrate between adjacent described selection transistor gate stack structure;
The second doped region in described Semiconductor substrate between adjacent described memory transistor gate stack structure;
Be positioned at structural first metal plug of described memory transistor gate stack;
Be positioned at structural second metal plug of described selection transistor gate stack;
Be positioned at the first conductive layer on described first doped region and the 3rd metal plug successively;
Be positioned at the second conductive layer on described second doped region and the 4th metal plug successively.
Wherein, the upper surface of described first conductive layer can flush in or higher than the upper surface of described selection transistor gate stack structure.
Wherein, the upper surface of described second conductive layer can flush in or higher than the upper surface of described memory transistor gate stack structure.
Wherein, the material of described first conductive layer or described second conductive layer can be polysilicon.
Wherein, described second conductive layer being positioned at the multiple pair transistor flash cells in same wordline can link together.
Wherein, described memory transistor gate stack structure can comprise from bottom to up successively: floating gate dielectric layer, floating boom, control gate dielectric layer and control gate and be positioned at the first side wall of the side of described floating gate dielectric layer, the side of described floating boom, the side of described control gate dielectric layer and the side of described control gate simultaneously; Described selection transistor gate stack structure can comprise from bottom to up successively: select gate dielectric layer and select grid and be positioned at the second side wall of the side of described selection gate dielectric layer and the side of described selection grid simultaneously; Adjacent described first side wall contacts with described second side wall.
Wherein, described semiconductor storage unit can also comprise: the first metal silicide between described memory transistor gate stack structure and described first metal plug; The second metal silicide between described selection transistor gate stack structure and described second metal plug; The 3rd metal silicide between described first conductive layer and described 3rd metal plug; The 4th metal silicide between described second conductive layer and described 4th metal plug.
Wherein, the mean breadth of described first conductive layer can be equal to or greater than the width of described first doped region, and the mean breadth of described second conductive layer can be equal to or greater than the width of described second doped region.
The semiconductor storage unit of the present embodiment can adopt any one manufacture method above-mentioned to be formed, and its concrete structure can with reference to shown in Figure 10 or Figure 16.
The semiconductor storage unit that the present embodiment provides increases by the first conductive layer between the first doped region and the 3rd metal plug, between the second doped region and the 4th metal plug, increase by the second conductive layer, be equivalent to raise the first doped region and the second doped region, reduce the degree of depth of the 3rd metal plug and the 4th metal plug, thus the difficulty of making the 3rd metal plug and the 4th metal plug can be reduced; The distance between the second adjacent metal plug and the 3rd metal plug and between the first adjacent metal plug and the 4th metal plug can be reduced; The second conductive layer being positioned at the multiple pair transistor flash cells in same wordline links together, thus without the need to carrying out the neck portion design of active area, finally greatly reduces the structural complexity of active area below source electrode.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (20)
1. a semiconductor storage unit, comprises multiple pair transistor flash cell, it is characterized in that, each described pair transistor flash cell comprises:
Semiconductor substrate;
Be positioned at memory transistor gate stack structure discrete in described Semiconductor substrate and select transistor gate stack structure;
The first doped region in described Semiconductor substrate between adjacent described selection transistor gate stack structure;
The second doped region in described Semiconductor substrate between adjacent described memory transistor gate stack structure;
Be positioned at structural first metal plug of described memory transistor gate stack;
Be positioned at structural second metal plug of described selection transistor gate stack;
Be positioned at the first conductive layer on described first doped region and the 3rd metal plug successively;
Be positioned at the second conductive layer on described second doped region and the 4th metal plug successively.
2. semiconductor storage unit as claimed in claim 1, is characterized in that, the upper surface flush of described first conductive layer in or higher than the upper surface of described selection transistor gate stack structure.
3. semiconductor storage unit as claimed in claim 1, is characterized in that, the upper surface flush of described second conductive layer in or higher than the upper surface of described memory transistor gate stack structure.
4. semiconductor storage unit as claimed in claim 1, it is characterized in that, the material of described first conductive layer or described second conductive layer is polysilicon.
5. semiconductor storage unit as claimed in claim 1, it is characterized in that, described second conductive layer being positioned at the multiple pair transistor flash cells in same wordline links together.
6. semiconductor storage unit as claimed in claim 1, it is characterized in that, described memory transistor gate stack structure comprises from bottom to up successively: floating gate dielectric layer, floating boom, control gate dielectric layer and control gate and be positioned at the first side wall of the side of described floating gate dielectric layer, the side of described floating boom, the side of described control gate dielectric layer and the side of described control gate simultaneously; Described selection transistor gate stack structure comprises from bottom to up successively: select gate dielectric layer and select grid and be positioned at the second side wall of the side of described selection gate dielectric layer and the side of described selection grid simultaneously; Adjacent described first side wall contacts with described second side wall.
7. semiconductor storage unit as claimed in claim 1, is characterized in that, also comprise:
The first metal silicide between described memory transistor gate stack structure and described first metal plug;
The second metal silicide between described selection transistor gate stack structure and described second metal plug;
The 3rd metal silicide between described first conductive layer and described 3rd metal plug;
The 4th metal silicide between described second conductive layer and described 4th metal plug.
8. semiconductor storage unit as claimed in claim 1, it is characterized in that, the mean breadth of described first conductive layer is equal to or greater than the width of described first doped region, and the mean breadth of described second conductive layer is equal to or greater than the width of described second doped region.
9. a manufacture method for semiconductor storage unit, is characterized in that, comprising:
Semiconductor substrate is provided;
Form discrete memory transistor gate stack structure on the semiconductor substrate and select transistor gate stack structure, adjacent described memory transistor gate stack structure and described selection transistor gate stack structure contact;
Form the first doped region in described Semiconductor substrate between adjacent described selection transistor gate stack structure, in the described Semiconductor substrate between adjacent described memory transistor gate stack structure, form the second doped region;
Described first doped region forms the first conductive layer, and form the second conductive layer on described second doped region;
Described first conductive layer, described second conductive layer, described memory transistor gate stack structure and described selection transistor gate stack structure form interlayer dielectric layer;
The 4th metal plug being positioned at structural first metal plug of described memory transistor gate stack, being positioned at structural second metal plug of described selection transistor gate stack, being positioned at the 3rd metal plug on described first conductive layer and being positioned on described second conductive layer is formed in described interlayer dielectric layer.
10. the manufacture method of semiconductor storage unit as claimed in claim 9, is characterized in that, forms described first conductive layer and described second conductive layer comprises:
Described Semiconductor substrate, described memory transistor gate stack structure and described selection transistor gate stack structure form conductive material layer, the upper surface of described memory transistor gate stack structure, higher than the upper surface of described selection transistor gate stack structure, is positioned at the upper surface of upper surface higher than described memory transistor gate stack structure of the structural described conductive material layer of described selection transistor gate stack;
Planarization is carried out to described conductive material layer, until make the upper surface flush of the upper surface of remaining described conductive material layer and described memory transistor gate stack structure;
Etching processing is carried out to remain the conductive material layer be positioned on described first doped region and described second doped region to remaining described conductive material layer.
The manufacture method of 11. semiconductor storage units as claimed in claim 10, it is characterized in that, before carrying out planarization, upper surface 1000 dust ~ 2000 dusts lower than the upper surface of the described conductive material layer being positioned at described selection transistor gate stack superstructure of described memory transistor gate stack structure.
The manufacture method of 12. semiconductor storage units as claimed in claim 9, is characterized in that, forms described first conductive layer and described second conductive layer comprises:
Described Semiconductor substrate, described memory transistor gate stack structure and described selection transistor gate stack structure form conductive material layer, bottom anti-reflection layer and low temperature oxide layer successively, the upper surface of described memory transistor gate stack structure higher than the upper surface of described selection transistor gate stack structure, the upper surface flush of described bottom anti-reflection layer;
Successively etching processing is carried out to described low temperature oxide layer, described bottom anti-reflection layer and described conductive material layer until only remain the conductive material layer be positioned on described first doped region and described second doped region.
The manufacture method of 13. semiconductor storage units as claimed in claim 12, is characterized in that, upper surface 500 dust ~ 1000 dusts lower than the upper surface of the described conductive material layer above it of described memory transistor gate stack structure.
The manufacture method of 14. semiconductor storage units as claimed in claim 12, is characterized in that, the thickness being positioned at the described bottom anti-reflection layer of described memory transistor gate stack structure upper surface is greater than 1000 dusts; The thickness of described low temperature oxide layer is greater than 300 dusts.
The manufacture method of 15. semiconductor storage units as described in claim 10 or 12, it is characterized in that, the material of described conductive material layer is polysilicon, form described first conductive layer and described second conductive layer also comprises: before the described conductive material layer of formation, form hard mask layer at the upper surface of described memory transistor gate stack structure and the upper surface of described selection transistor gate stack structure; After carrying out described etching processing, remove described hard mask layer.
The manufacture method of 16. semiconductor storage units as claimed in claim 15, is characterized in that, the thickness range of described hard mask layer comprises 200 dust ~ 1000 dusts; The material of described hard mask layer is one or more of silicon nitride, silica or silicon oxynitride.
The manufacture method of 17. semiconductor storage units as claimed in claim 9, it is characterized in that, described semiconductor storage unit comprises multiple pair transistor flash cell, and described second conductive layer being positioned at the multiple pair transistor flash cells in same wordline links together.
The manufacture method of 18. semiconductor storage units as claimed in claim 9, it is characterized in that, described memory transistor gate stack structure comprises from bottom to up successively: floating gate dielectric layer, floating boom, control gate dielectric layer and control gate and be positioned at the first side wall of the side of described floating gate dielectric layer, the side of described floating boom, the side of described control gate dielectric layer and the side of described control gate simultaneously; Described selection transistor gate stack structure comprises from bottom to up successively: select gate dielectric layer and select grid and be positioned at the second side wall of the side of described selection gate dielectric layer and the side of described selection grid simultaneously; Adjacent described first side wall contacts with described second side wall.
The manufacture method of 19. semiconductor storage units as claimed in claim 18, it is characterized in that, described selection grid and described control gate are formed simultaneously.
The manufacture method of 20. semiconductor storage units as claimed in claim 9, it is characterized in that, before the described interlayer dielectric layer of formation, form the 4th metal silicide being positioned at structural first metal silicide of described memory transistor gate stack, being positioned at structural second metal silicide of described selection transistor gate stack, being positioned at the 3rd metal silicide on described first conductive layer and being positioned on described second conductive layer.
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| CN118475124A (en) * | 2024-07-11 | 2024-08-09 | 武汉新芯集成电路股份有限公司 | Transistor device and manufacturing method thereof |
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