CN104810297A - Method for manufacturing a flip chip circuit device and the flip chip circuit device - Google Patents
Method for manufacturing a flip chip circuit device and the flip chip circuit device Download PDFInfo
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- CN104810297A CN104810297A CN201510028691.0A CN201510028691A CN104810297A CN 104810297 A CN104810297 A CN 104810297A CN 201510028691 A CN201510028691 A CN 201510028691A CN 104810297 A CN104810297 A CN 104810297A
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Abstract
本发明涉及一种用于制造倒装芯片电路装置的方法,方法具有至少以下步骤:制造或者提供具有第一表面和施加到第一表面上的接通面的电路载体以及具有第二表面和施加到第二表面上的接触位置的半导体构件,施加第一接触单元到接通面上,施加与第一接触单元对应的第二接触单元到接触位置上,如此使第一接触单元平坦化,使得第一接触单元的接触表面在第一公差之内限定共同的第一接触平面,施加粘接剂到第一接触单元和/或第二接触单元上,按压半导体构件和电路载体以便构成第一和第二接触单元之间的电连接,以及使粘接剂硬化以便建立半导体构件和电路载体之间的机械连接。
The invention relates to a method for producing a flip-chip circuit arrangement, the method having at least the following steps: producing or providing a circuit carrier having a first surface and contact areas applied to the first surface and having a second surface and applying To the semiconductor component at the contact location on the second surface, applying a first contact element to the connection surface, applying a second contact element corresponding to the first contact element to the contact location, such that the first contact element is planarized such that The contact surfaces of the first contact unit define a common first contact plane within a first tolerance, the adhesive is applied to the first contact unit and/or the second contact unit, the semiconductor component and the circuit carrier are pressed to form the first and The electrical connection between the second contact units and the hardening of the adhesive in order to produce a mechanical connection between the semiconductor component and the circuit carrier.
Description
技术领域technical field
本发明涉及一种用于制造倒装芯片电路装置的方法和一种相应的倒装芯片电路装置。The invention relates to a method for producing a flip-chip circuit arrangement and a corresponding flip-chip circuit arrangement.
背景技术Background technique
在倒装芯片装配技术中将例如单片半导体元件(芯片、裸芯片(Die))以其有效的接通侧直接装配和接通到电路载体——例如衬底或电路板——上。半导体元件的接触位置在此在无连接引线(引线键合)的情况下与电路载体上的接通面——例如印制导线接通。由此可实现小的面积需求。In flip-chip assembly technology, for example, monolithic semiconductor components (chips, dies) are mounted and connected with their active contact sides directly onto a circuit carrier, for example a substrate or a circuit board. In this case, the contact points of the semiconductor components are connected to contact areas on the circuit carrier, for example conductor tracks, without connecting wires (wire bonding). A small area requirement can thus be achieved.
为此,例如由金制成的钉头凸点(Stud-Bump)施加到半导体构件的接触位置上并且随后铺设到电路载体的印制导线上,其中,所述钉头凸点相当于由常规的球楔键合(Ball-Wedge-Bonden)方法形成的球形键合。然后,按压半导体构件到电路载体上,从而在印制导线和钉头凸点部分地变形的情况下构造电连接。在借助非导电胶粘剂(NCA,非导电胶粘剂)的倒装芯片方法中,在按压之前或者之后将粘合剂置于芯片和电路载体之间,所述粘合剂然后硬化。For this purpose, stud bumps, for example made of gold, are applied to the contact points of the semiconductor components and subsequently laid down on the conductor tracks of the circuit carrier, wherein the stud bumps correspond to those produced by conventional The spherical bond formed by the Ball-Wedge-Bonden method. Then, the semiconductor component is pressed onto the circuit carrier, so that the electrical connection is formed with the conductor tracks and stud bumps partially deformed. In the flip-chip method by means of a non-conductive adhesive (NCA, non-conductive adhesive), an adhesive is placed between the chip and the circuit carrier before or after pressing, which then hardens.
尤其在电路载体的不平整的表面——该表面过渡到印制导线的表面——的情况下,可能在按压钉头凸点的情况下发生不可靠的电接触,因为基于不平整性,局部不同的按压力发生作用。由此,印制导线可能由于其小的高度容易被破坏或者说机械变形,并且位于其下方的电路载体也可能塑性变形。此外,各个凸出的区域可能导致损坏或机械紧固。Especially in the case of an uneven surface of the circuit carrier, which transitions into the surface of the conductor tracks, unreliable electrical contacting can occur when the stud bumps are pressed, because due to the unevenness, local Different pressing forces take effect. As a result, the conductor track can be easily damaged or mechanically deformed due to its small height, and the circuit carrier lying beneath it can also be plastically deformed. Furthermore, each protruding area can lead to damage or mechanical fastening.
为此,在WO 02/056345 A2中提出一种倒装芯片连接,在所述倒装芯片连接中,钉头凸点不仅仅施加在半导体构件的接触位置上,而且也施加在印制导线上或者电路载体的接触盘上。为了构造均质的接触表面,通过压印使钉头凸点平坦化,从而补偿在电路载体和半导体构件上的、也传递到接触表面上的不平整性,并且因此,钉头凸点的接触表面大致位于电路载体或者说半导体构件之上的大约相等的高度上。接着,半导体构件的和电路载体的钉头凸点相对于彼此对齐地叠置并且在键合方法中接合在一起,其方式是,加热、彼此相对地按压和附加地以超声处理所述钉头凸点,以便实现接触材料在两个钉头凸点的接触表面上的扩散。由此构造电连接和机械连接。For this purpose, a flip-chip connection is proposed in WO 02/056345 A2, in which the stud bumps are applied not only to the contact points of the semiconductor components but also to the conductor tracks Or on the contact pads of the circuit carrier. In order to form a homogeneous contact surface, the stud bumps are flattened by embossing, so that unevennesses on the circuit carrier and semiconductor component that are also transferred to the contact surface are compensated, and thus the contact of the stud bumps The surfaces lie approximately at approximately the same height above the circuit carrier or the semiconductor component. Next, the stud bumps of the semiconductor component and of the circuit carrier are placed on top of each other in alignment and bonded together in a bonding method by heating, pressing against each other and additionally ultrasonically treating the stud heads bumps so that the contact material spreads over the contact surface of the two stud bumps. An electrical connection and a mechanical connection are thus formed.
发明内容Contents of the invention
根据本发明设置,电路载体、尤其注塑的电路载体(模塑互联器件,MID,molded interconnect device)和优选单片的半导体构件(芯片,裸芯片)在倒装芯片方法中相互连接和接通,其中,对着施加在半导体构件上的第二接触单元按压与电路载体连接的和经平坦化的第一接触单元,并且附加地使至少部分地包围两个接触单元的粘接剂硬化,以便持久地连接两个彼此相对地按压的接触单元。由此构造倒装芯片电路装置。It is provided according to the invention that the circuit carrier, in particular an injection-molded circuit carrier (molded interconnect device, MID, molded interconnect device), and preferably monolithic semiconductor components (chip, bare chip) are connected and connected to each other in a flip-chip method, In this case, the first contact unit connected to the circuit carrier and planarized is pressed against the second contact unit applied to the semiconductor component, and the adhesive which at least partially surrounds the two contact units is additionally cured in order to permanently Ground connects two contact units pressed against each other. A flip-chip circuit arrangement is thus constructed.
在此,第一和第二接触单元优选实施为金块或者金球,即所谓的钉头凸点,所述第一和第二接触单元与在球楔键合方法中的球形键合部类似地施加到半导体构件上的接触位置上并且施加到电路载体上的接通面——例如由电镀结构例如铜、镍/磷和金电镀的印制导线——上。Here, the first and second contact elements are preferably embodied as gold nuggets or gold balls, so-called stud bumps, which are similar to ball bonds in the ball-wedge bonding method. The ground is applied to the contact points on the semiconductor component and to contact areas on the circuit carrier, for example conductor tracks plated with galvanic structures such as copper, nickel/phosphorus and gold.
由此已经能够实现一些优点。Some advantages can already be achieved by this.
因此,通过在两个待接通的元件上使用钉头凸点来实现,在按压时在电路载体和钉头凸点之间布置的、例如作为印制导线使用的接通面较不强烈地受压。因此通过在印制导线上施加的钉头凸点,“变形平面”在按压时从印制导线优选向上移动到钉头凸点中,并且因此发生作用的表面负荷从电路载体和印制导线向上迁移,从而在按压时力主要作用到钉头凸点的接触表面上并且仅仅小的通过钉头凸点所传递的力作用到印制导线上。由此能够例如强烈地降低在表面负荷中的、可能导致电路载体和印制导线的损坏的峰值,并且因此能够避免印制导线和由塑料制造的电路载体的变形;改善接触的可靠性。The use of stud bumps on the two components to be connected thus achieves that the connection surfaces arranged between the circuit carrier and the stud bumps, which are used, for example, as conductor tracks, are less strongly pressed when pressed. under pressure. Thus, due to the stud bumps applied to the conductor tracks, the "deformation plane" is moved from the conductor tracks, preferably upwards into the stud bumps when pressed, and thus the acting surface load is directed upwards from the circuit carrier and the conductor tracks. Migration, so that when pressing, the force mainly acts on the contact surface of the stud bump and only a small amount of force transmitted through the stud bump acts on the conductor track. As a result, for example, peaks in the surface load that can lead to damage to the circuit carrier and the conductor tracks can be greatly reduced, and deformation of the conductor tracks and the circuit carrier produced from plastic can thus be avoided; the reliability of the contacting is improved.
此外,能够通过第一接触单元的平坦化补偿电路载体的表面上的不平整性,所述不平整性可能位于10μm-20μm的数量级中。这在倒装芯片制造过程中具有以下优点:能够防止接触单元由于各个突出的接触单元在按压时的损坏。Furthermore, irregularities on the surface of the circuit carrier, which may be in the order of 10 μm-20 μm, can be compensated for by the planarization of the first contact unit. This has the advantage during flip-chip manufacturing that damage to the contact elements during pressing due to the individual protruding contact elements can be prevented.
在此,在本发明的范畴内,平坦化或者平整化理解为,使接触表面与第一接触单元至少部分地相适应,即在一个公差内位于第一接触平面中。这可以例如机械地、例如通过置于接触表面上的凸模或者通过材料侵蚀——例如通过激光烧蚀来确保。但也可以考虑其他的使接触表面移动到平面或者接触平面中的方法。在平整化时,优选也略微增大接触表面的面积,因为在平整化时,接触材料也部分地被推开至侧面。在此,公差尤其为由制造决定的公差,例如由于凸模的粗糙度或另外的在平坦化过程中出现的处理精度,所述公差可以位于几百纳米的范围内。Within the scope of the present invention, flattening or flattening is understood here to mean that the contact surface is at least partially adapted to the first contact unit, ie lies within a tolerance in the first contact plane. This can be ensured, for example, mechanically, for example by a stamp placed on the contact surface or by material erosion, for example by laser ablation. However, other methods of moving the contact surface into the plane or into the contact plane are also conceivable. During planarization, the area of the contact surface is preferably also slightly increased, since during planarization the contact material is also partly pushed away to the side. In this case, tolerances are in particular production-dependent tolerances, for example due to the roughness of the punch or other processing precision occurring during the planarization process, which tolerances may lie in the range of several hundred nanometers.
与在WO 02/056345A2中所设置的键合过程——其中接触单元相对彼此被按压、加热和借助超声处理——中不同地,根据本发明优选不发生接触材料——例如金的扩散;因此,所述接触单元不像尤其在键合时那样被焊接,而是根据本发明优选相叠地按压并且仅仅通过经硬化的粘合剂保持相互靠近。Unlike in the bonding process provided in WO 02/056345A2 in which the contact elements are pressed against each other, heated and treated with ultrasound, according to the invention preferably no diffusion of the contact material, such as gold, takes place; therefore , the contact elements are not welded, in particular during bonding, but according to the invention are preferably pressed one above the other and held close together only by the hardened adhesive.
由此可以以有利的方式使制造费用保持小,因为在所述制造中不需要附加的方法步骤,如例如借助超声的处理。此外,可以通过省去超声处理来避免接触单元和整个倒装芯片电路装置的附加要求。As a result, the manufacturing outlay can advantageously be kept low, since no additional method steps are required during the manufacturing, such as, for example, treatment by means of ultrasound. Furthermore, additional requirements for contacting the unit and the entire flip-chip circuit arrangement can be avoided by omitting the ultrasonic treatment.
优选在按压之前如此施加粘接剂到电路载体上,使得所述粘接剂优选完全覆盖第一接触单元和接触表面,其中,粘接剂也可以分布在直接邻近的接通面(印制导线)上。在此,例如如此选择粘接剂的量,使得粘接剂在两个接触单元的按压之后完全填充电路载体和半导体构件之间的间隙,即基本上完全地贴靠电路载体的和半导体构件的表面,以便在硬化之后提高两个元件的机械连接的稳定性。在此,优选仅仅通过以下方式实现机械接合:粘接剂将半导体构件与电路载体连接或者粘接并且因此接触单元保持相互靠近。原则上,也可能的是,粘接剂附加地或者取而代之地施加到半导体构件的表面上。The adhesive is preferably applied to the circuit carrier prior to pressing in such a way that it preferably completely covers the first contact element and the contact surface, wherein the adhesive can also be distributed on the directly adjacent connection areas (conductor tracks). )superior. In this case, for example, the amount of adhesive is selected such that the adhesive completely fills the gap between the circuit carrier and the semiconductor component after the two contact units have been pressed, ie lies essentially completely against the circuit carrier and the semiconductor component. surface in order to increase the stability of the mechanical connection of the two elements after hardening. In this case, the mechanical bonding is preferably achieved only by the adhesive connecting or bonding the semiconductor component to the circuit carrier and thus holding the contact units close to one another. In principle, it is also possible for an adhesive to be applied additionally or instead to the surface of the semiconductor component.
接着,半导体构件的、在由制造决定的公差之内形成第二接触平面的第二接触单元相对于第一接触单元对准并且相互靠近,直到它们碰触到,其中,第一和第二接触平面平行于彼此平放。随后,按压第二接触单元到第一接触单元上,从而粘接剂被挤出到侧面并且在侧面在接触单元周围、也在接触表面的区域中铺设。因此,两个接触单元的接触表面相对于彼此处于电接触中,即粘接剂几乎完全从接触表面之间的间隙中挤出。Next, the second contact elements of the semiconductor component, which form the second contact plane within manufacturing-determined tolerances, are aligned relative to the first contact elements and approach each other until they touch, wherein the first and second contact The planes lie parallel to each other. Subsequently, the second contact unit is pressed onto the first contact unit, so that the adhesive is extruded to the side and spreads on the side around the contact unit, also in the region of the contact surface. The contact surfaces of the two contact units are thus in electrical contact with respect to each other, ie the adhesive is almost completely squeezed out of the gap between the contact surfaces.
在此,粘接剂例如为非导电胶(NCA,non conductive adhesive),以便以有利的方式防止,通过粘接剂将相互邻近的接通面和钉头凸点相互电连接。也可以考虑,附加地使用导电粘接剂、例如银导电胶,其例如仅仅局部地施加在接触表面的区域中,优选在施加非导电粘接剂之前。在按压时,首先将非导电粘接剂挤出直到两个接触单元碰触到导电粘接剂并且同样将所述导电粘接剂挤出,其中,所述导电粘接剂然后至少部分地也可以残留在接触表面之间的间隙中,以便补偿例如小的公差。此外,可以改善电过渡,因为能够减少或者说避免接触表面之间的非导电粘接剂的夹杂物。In this case, the adhesive is, for example, a non-conductive adhesive (NCA, non-conductive adhesive), in order to advantageously prevent an electrical connection of contact surfaces and stud bumps adjacent to one another to one another via the adhesive. It is also conceivable to additionally use a conductive adhesive, for example a silver conductive glue, which is applied, for example, only locally in the region of the contact surface, preferably before applying the non-conductive adhesive. When pressing, the non-conductive adhesive is first extruded until the two contact elements touch the conductive adhesive and the electrically conductive adhesive is also extruded, wherein the electrically conductive adhesive is then also at least partially It may remain in the gap between the contact surfaces in order to compensate eg small tolerances. Furthermore, the electrical transition can be improved, since inclusions of non-conductive adhesive between the contact surfaces can be reduced or avoided.
为了使粘接剂硬化,优选加热所述粘接剂。为此,视粘接剂而定地设置大约250°的温度。有帮助地,通过温度提高也加热接触单元,由此所述接触单元变得更软并且因此可以更容易变形。由此,优选不实现接触材料的扩散、即接触单元的焊接在一起。In order to harden the adhesive, the adhesive is preferably heated. For this purpose, depending on the adhesive, a temperature of approximately 250° is set. Helpfully, the temperature increase also heats the contact unit, whereby it becomes softer and can thus be deformed more easily. Diffusion of the contact material, ie welding of the contact elements together, is thus preferably not achieved.
通过加热接触单元也可以以有利的方式实现不同地成形的接触表面的相互匹配。在此,在按压时,例如使所述一个接触表面的各个突出的区域如此机械变形,使得它们与相对置的接触表面相适应并且因此改善电过渡。An adaptation of differently shaped contact surfaces to one another can also be advantageously achieved by heating the contact unit. In this case, during pressing, for example, the respective protruding regions of the one contact surface are mechanically deformed in such a way that they are adapted to the opposite contact surface and thus improve the electrical transfer.
在此,制造步骤可以改变。因此,第二接触单元的施加例如与第一接触单元的施加和平坦化无关,即在时间上可以在其之前或者之后发生。Here, the manufacturing steps may vary. Thus, for example, the application of the second contacting unit is independent of the application and planarization of the first contacting unit, ie can take place before or after it in time.
附图说明Description of drawings
附图示出:The accompanying drawings show:
图1示出电路载体和半导体构件在接通之前的示意性视图,FIG. 1 shows a schematic view of the circuit carrier and the semiconductor components before switching them on,
图2示出根据图1的、具有所施加的接通面的电路载体,FIG. 2 shows the circuit carrier according to FIG. 1 with applied contact areas,
图3示出根据图2的、具有施加到接通面上的第一接触单元的电路载体,FIG. 3 shows the circuit carrier according to FIG. 2 with a first contact unit applied to the contact surface,
图4示出使第一接触单元平坦化的步骤,Figure 4 shows the step of planarizing the first contact unit,
图5示出在接通之前的倒装芯片电路装置,Figure 5 shows the flip-chip circuit arrangement before switching on,
图6示出接通的倒装芯片电路装置,以及Figure 6 shows a turned-on flip-chip circuit arrangement, and
图7示出根据本发明的方法的流程图。Fig. 7 shows a flow chart of the method according to the invention.
具体实施方式Detailed ways
为了构造在图6中所示出的倒装芯片电路装置3,首先根据图1提供电路载体1——例如电路板、尤其注塑的电路载体(模塑互联器件,MID,molded interconnect device)和单片的半导体构件2或者说芯片或者裸芯片。电路载体1由非导电材料、优选塑料制造并且具有不平整的表面4,其中,在制造时和通过附加的表面处理(激光处理)可能出现不平整性。芯片2具有表面5,在该表面上布置有多个相互隔离的接触位置6——例如接触盘,所述接触位置与集成的开关电路在芯片2中连接。In order to construct the flip-chip circuit arrangement 3 shown in FIG. 6, a circuit carrier 1 is first provided according to FIG. A wafer of semiconductor components 2 or a chip or a bare chip. The circuit carrier 1 is produced from a non-conductive material, preferably plastic, and has an uneven surface 4 , wherein irregularities can occur during production and by additional surface treatment (laser treatment). The chip 2 has a surface 5 on which a plurality of mutually isolated contact points 6 , for example contact pads, which are connected to an integrated switching circuit in the chip 2 , are arranged.
为了将电路载体1与芯片2连接,首先设置,在电路载体1上施加接通面7——例如印制导线和/或接触盘——或者提供具有已经处理的接通面7的电路载体1。为此,根据图2,例如在电镀过程中施加导电层——例如由相应的由铜、镍/磷和金制成的电镀结构——到经表面处理的表面4上,从而构造尽可能无缺陷的接通面7。在此,接通面7形成电路图,该电路图在表面4上基本上沿x方向和y方向延伸,其中,y方向在图中垂直于图平面地定向。分布在表面4上的接通面7的高度、即在z方向上的延展是大致相等的并且为大约10μm至20μm。To connect the circuit carrier 1 to the chip 2 it is first provided that contact areas 7 are applied to the circuit carrier 1 - for example conductor tracks and/or contact pads - or the circuit carrier 1 is provided with already processed contact areas 7 . For this purpose, according to FIG. 2 , for example, an electrically conductive layer is applied in an electroplating process—for example, corresponding electroplating structures made of copper, nickel/phosphorus and gold—onto the surface-treated surface 4 , so that as far as possible no Defective contact surface 7. In this case, contact surface 7 forms a circuit pattern which extends over surface 4 substantially in x-direction and y-direction, wherein in the drawing the y-direction is oriented perpendicular to the drawing plane. The height, ie, the extent in the z-direction, of contact areas 7 distributed over surface 4 is approximately equal and is approximately 10 μm to 20 μm.
由于电路载体1的不平整性,这些接通面7在z方向上相对于彼此移位,即在z方向上的相对定位改变;因此,在表面4上的不平整性也传递到接通面7上。Due to the unevenness of the circuit carrier 1, the connection surfaces 7 are displaced relative to each other in the z direction, ie the relative positioning in the z direction changes; therefore, unevennesses on the surface 4 are also transferred to the connection surfaces 7 on.
为了补偿所述移位,在根据本发明的方法中尤其设置,施加第一接触单元8.1、8.2到接通面7上(St1)。在此,第一接触单元8.1、8.2实施为所谓的钉头凸点。这些钉头凸点在键合方法中施加到接通面7上,所述键合方法例如为常规的球楔键合的一部分。In order to compensate for this displacement, it is provided in particular in the method according to the invention that a first contact unit 8 . 1 , 8 . 2 is applied to contact surface 7 ( St1 ). In this case, the first contact units 8.1, 8.2 are embodied as so-called stud bumps. These stud bumps are applied to contact surface 7 in a bonding method, for example as part of conventional ball-and-wedge bonding.
为此,球楔键合部的尖端被引至接通面7之上,并且接着加热由所述尖端突出的金引线,从而金熔化并且通过表面张力形成球(Ball)。该球借助短的超声脉冲压紧或者键合到接通面7上,从而在接通面7和球之间产生电连接。接着,在球的紧上方剪断金引线。球和被剪断的金引线形成钉头凸点,所述第一接触单元8.1、8.2。在此,钉头凸点的高度9.1、9.2为大约50μm并且可以具有大约1μm-2μm的由制造决定的公差。For this purpose, the tip of the ball wedge bond is brought over contact surface 7 and the gold wire protruding from the tip is then heated so that the gold melts and forms a ball due to surface tension. The ball is pressed or bonded to the contact surface 7 by means of short ultrasonic pulses, so that an electrical connection is produced between the contact surface 7 and the ball. Next, cut the gold wire just above the ball. The balls and the snipped gold wires form stud bumps, the first contact units 8.1, 8.2. In this case, the height 9.1, 9.2 of the stud bumps is approximately 50 μm and can have a production-dependent tolerance of approximately 1 μm-2 μm.
此外,在施加第一接触单元8.1、8.2之后,所述第一接触单元在z方向上相对于彼此移位,因为表面4的不平整性通过接通面7也传递到钉头凸点8.1、8.2上,如尤其在图3中可以看出的那样。钉头凸点的由制造决定的公差可以在最大程度上保持不被考虑,因为该公差相对于表面4的可能位于10μm-20μm范围内的不平整性是可忽略的。Furthermore, after application of the first contacting units 8.1, 8.2, the first contacting units are displaced relative to one another in the z-direction, since unevennesses of the surface 4 are also transferred via the contact surface 7 to the stud bumps 8.1, 8.2, as can be seen especially in FIG. 3 . The production-specific tolerances of the stud bumps can largely be kept out of consideration, since they are negligible with respect to irregularities of the surface 4 which may lie in the range of 10 μm-20 μm.
为了补偿所述不平整性,在以下的步骤St2中使第一接触单元8.1、8.2平坦化,即如此匹配其高度9.1、9.2,使得所有第一接触单元8.1、8.2的接触表面10.1、10.2以第一公差20位于共同的第一接触平面11中,根据图4,所述第一接触平面在x-y方向上延展。In order to compensate for said unevenness, in the following step St2 the first contact elements 8.1, 8.2 are planarized, ie their heights 9.1, 9.2 are adapted in such a way that the contact surfaces 10.1, 10.2 of all first contact elements 8.1, 8.2 are The first tolerance 20 lies in a common first contact plane 11 , which according to FIG. 4 extends in the x-y direction.
为了进行平坦化,在此根据该实施,使用具有平整的下侧13的凸模12,所述凸模在整个电路载体1上延展或者在铺设到所述电路载体上时覆盖至少一个区域,待平坦化的第一接触单元8.1、8.2在电路载体1上布置在所述至少一个区域中。可以在所有三个空间方向上例如由通过控制装置12.1控制的伺服电动机12.2调节凸模12的或者说下侧13的位置。For planarization, according to this implementation, a punch 12 with a flat underside 13 is used which extends over the entire circuit carrier 1 or covers at least one region when laid on said circuit carrier, to be The planarized first contact unit 8 . 1 , 8 . 2 is arranged on the circuit carrier 1 in the at least one region. The position of the punch 12 or the underside 13 can be adjusted in all three spatial directions, for example by a servomotor 12.2 controlled by the control device 12.1.
为此,由伺服电动机12.2使凸模12从上方靠近第一接触单元8.1、8.2并且如此定向,使得下侧13平行于之前所确定的第一接触平面11。接着,下侧13以如此程度向下行进,直到该下侧碰触到各个突出的第一接触单元8.1、8.2或者它们的接触表面10.1、10.2。随后,以均匀的力沿按压方向R按压凸模12到接触表面10.1、10.2上,从而第一接触单元8.1、8.2机械变形,由此减小所述第一接触单元的高度9.1、9.2并且使每一个接触单元8.1、8.2的接触表面10.1、10.2平整并且因此略微增大接触表面的面积。大约以如此程度按压凸模12,直到下侧13靠触所有接触单元8.1、8.2,并且因此也碰触到最邻近地位于表面4上的接触单元8.1、8.2。整体上,如此强烈地在按压方向R上调节凸模12,直到所有接触表面10.1、10.2在由制造决定的第一公差20之内位于第一接触平面11中,并且此外使得每一个接触表面10.1、10.2平整。For this purpose, the punch 12 is brought close to the first contact unit 8 . 1 , 8 . 2 from above by the servomotor 12 . 2 and is oriented such that the underside 13 is parallel to the previously determined first contact plane 11 . The underside 13 then travels downwards to such an extent that it touches the respective protruding first contact unit 8.1, 8.2 or their contact surface 10.1, 10.2. Subsequently, the punch 12 is pressed with a uniform force in the pressing direction R onto the contact surfaces 10.1, 10.2, so that the first contact elements 8.1, 8.2 are mechanically deformed, thereby reducing the height 9.1, 9.2 of said first contact elements and making The contact surface 10.1, 10.2 of each contact unit 8.1, 8.2 is flat and thus slightly increases the area of the contact surface. The punch 12 is pressed approximately until the underside 13 touches all contact elements 8 . 1 , 8 . 2 and thus also the contact elements 8 . 1 , 8 . Overall, the punch 12 is adjusted so strongly in the pressing direction R that all contact surfaces 10 . 1 , 10 . , 10.2 smooth.
因此,通过平坦化实现第一接触平面11,可以施加布置在半导体构件2上的第二接触单元15.1、15.2到该第一接触平面上。在此,第二接触单元15.1、15.2根据图5同样实施为钉头凸点,所述钉头凸点施加到接触位置6上,例如在步骤St1.1中与钉头凸点施加到接通面7上一起。第二接触单元15.1、15.2以其接触表面16.1、16.2限定第二接触平面17,所述第二接触平面由制造决定地可以具有1μm-2μm的第二公差21。The first contact plane 11 , to which the second contact units 15 . 1 , 15 . 2 arranged on the semiconductor component 2 can be applied, is thus achieved by planarization. Here, the second contact units 15.1, 15.2 are likewise designed according to FIG. Face 7 together. The second contact unit 15.1, 15.2 delimits with its contact surfaces 16.1, 16.2 a second contact plane 17 which, depending on production, may have a second tolerance 21 of 1 μm-2 μm.
在第二接触单元15.1、15.2施加到第一接触单元8.1、8.2上之前,在步骤St3中,将粘接剂18——例如非导电环氧树脂胶(NCA,non-conductiveadhesive:非导电粘结剂)如此施加到电路载体1的表面4上,使得完全覆盖第一接触单元8.1、8.2并且也完全覆盖周围的区域,如尤其在图5中所示出的那样。附加地,可以在施加非导电粘接剂18之前将导电粘接剂18.1局部地施加到接触表面10.1、10.2上,而两个邻近的第一接触单元8.1、8.2不因此相互接通。接着,相对于电路载体1如此定向半导体构件2,使得对应于第一接触单元8.1、8.2的第二接触单元15.1、15.2上下相叠地定位并且平面11和17平行于彼此。随后,在步骤St4中,使半导体构件2靠近电路载体1,直到第二接触单元15.1、15.2碰触到第一接触单元8.1、8.2,并且如此彼此相对按压,使得粘接剂18被挤到侧面并且在两个接触单元8.1、8.2、10.1、10.2周围铺设并且优选完全包围它们。在此,优选完全以粘接剂18填充电路载体1和半导体构件2之间的间隙,如在图6中所示出的那样。导电粘接剂18.1也被挤到侧面,但是至少部分地残留在接触表面10.1、10.2、16.1、16.2之间的间隙中。Before the second contact unit 15.1, 15.2 is applied to the first contact unit 8.1, 8.2, in step St3, an adhesive 18—such as a non-conductive epoxy glue (NCA, non-conductive adhesive: non-conductive adhesive) Agent) is applied to the surface 4 of the circuit carrier 1 in such a way that the first contact units 8.1, 8.2 and also the surrounding area are completely covered, as shown in particular in FIG. 5 . In addition, the electrically conductive adhesive 18.1 can be locally applied to the contact surfaces 10.1, 10.2 before the non-conductive adhesive 18 is applied, without two adjacent first contact units 8.1, 8.2 thus not being brought into contact with each other. The semiconductor component 2 is then aligned relative to the circuit carrier 1 in such a way that the second contact units 15 . 1 , 15 . 2 corresponding to the first contact units 8 . 1 , 8 . 2 are positioned one above the other and the planes 11 and 17 are parallel to each other. Subsequently, in step St4, the semiconductor component 2 is brought closer to the circuit carrier 1 until the second contact elements 15.1, 15.2 touch the first contact elements 8.1, 8.2 and are thus pressed against each other such that the adhesive 18 is forced to the sides And it is laid around the two contact units 8.1, 8.2, 10.1, 10.2 and preferably completely surrounds them. In this case, the gap between circuit carrier 1 and semiconductor component 2 is preferably completely filled with adhesive 18 , as shown in FIG. 6 . The electrically conductive adhesive 18.1 is also squeezed out to the sides, but remains at least partially in the gaps between the contact surfaces 10.1, 10.2, 16.1, 16.2.
为了使两个接触单元8.1、8.2、15.1、15.2持久地相互连接,在接着的步骤St5中使粘接剂18硬化;在此,可以略微收缩(zusamenziehen)粘接剂18,以致于半导体构件2绷紧到电路载体1上。因此,粘接剂18负责使两个接触单元8.1、8.2、15.1、15.2粘牢。因此,优选首先通过粘接剂18实现机械粘牢,所述粘接剂将半导体构件2保持在电路载体1上。为了进行硬化,至少加热在接触表面8.1、8.2、15.1、15.2周围的区域,其中,视粘接剂18而定地将温度调节到250°以内。In order to permanently connect the two contact units 8.1, 8.2, 15.1, 15.2 to each other, the adhesive 18 is hardened in the following step St5; Stretched onto the circuit carrier 1. The adhesive 18 is therefore responsible for the fastening of the two contact units 8.1, 8.2, 15.1, 15.2. The mechanical fastening is therefore preferably firstly achieved by means of an adhesive 18 which holds the semiconductor component 2 on the circuit carrier 1 . For hardening, at least the area around the contact surfaces 8.1, 8.2, 15.1, 15.2 is heated, the temperature being adjusted to within 250° depending on the adhesive 18.
通过加热有帮助地,接触表面10.1、10.2、16.1、16.2也变得较软,从而所述接触表面在按压时由于机械变形能够相互匹配,即可以附加地补偿接触表面10.1、10.2、16.1、16.2中的小的不平整性和由制造决定的公差。在粘接剂18的硬化之后,完成根据图6的倒装芯片电路装置3。Helpfully by heating, the contact surfaces 10.1, 10.2, 16.1, 16.2 also become softer, so that they can be adapted to one another when pressed due to mechanical deformation, ie the contact surfaces 10.1, 10.2, 16.1, 16.2 can be additionally compensated Small irregularities and tolerances determined by manufacturing. After hardening of the adhesive 18 , the flip-chip circuit arrangement 3 according to FIG. 6 is completed.
Claims (16)
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| DE102014201166.3A DE102014201166A1 (en) | 2014-01-23 | 2014-01-23 | Method for producing a flip-chip circuit arrangement and flip-chip circuit arrangement |
| DE102014201166.3 | 2014-01-23 |
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| CN119133134A (en) * | 2024-08-08 | 2024-12-13 | 中国电子科技集团公司第二十九研究所 | A radio frequency chip flip-chip interconnection structure and preparation method |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1130306A (en) * | 1994-12-26 | 1996-09-04 | 松下电器产业株式会社 | Semiconductor device and method for manufacturing the same |
| CN1392024A (en) * | 2002-06-28 | 2003-01-22 | 威盛电子股份有限公司 | High Resolution Solder Bump Formation Method |
| CN1519892A (en) * | 2003-01-21 | 2004-08-11 | 颀邦科技股份有限公司 | Method for eliminating height difference of metal bumps on wafer and crystal grain |
| CN1619807A (en) * | 2004-12-06 | 2005-05-25 | 友达光电股份有限公司 | Substrates including integrated circuit chips and integrated circuits thereon |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020093108A1 (en) | 2001-01-15 | 2002-07-18 | Grigorov Ilya L. | Flip chip packaged semiconductor device having double stud bumps and method of forming same |
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2014
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1130306A (en) * | 1994-12-26 | 1996-09-04 | 松下电器产业株式会社 | Semiconductor device and method for manufacturing the same |
| CN1392024A (en) * | 2002-06-28 | 2003-01-22 | 威盛电子股份有限公司 | High Resolution Solder Bump Formation Method |
| CN1519892A (en) * | 2003-01-21 | 2004-08-11 | 颀邦科技股份有限公司 | Method for eliminating height difference of metal bumps on wafer and crystal grain |
| CN1619807A (en) * | 2004-12-06 | 2005-05-25 | 友达光电股份有限公司 | Substrates including integrated circuit chips and integrated circuits thereon |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN119133134A (en) * | 2024-08-08 | 2024-12-13 | 中国电子科技集团公司第二十九研究所 | A radio frequency chip flip-chip interconnection structure and preparation method |
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