CN104810288A - Manufacturing method of double-diffusion metal-oxide-semiconductor (DMOS) device - Google Patents

Abstract

The invention provides a method for manufacturing a DMOS device, comprising the following steps: forming an initial oxide layer on the surface of an epitaxial layer of a silicon substrate; using a mask plate to perform photolithography and etching on the silicon substrate formed with the initial oxide layer , forming an active region pattern and a source injection blocking layer located in the region of the active region pattern on the initial oxide layer; forming a gate in the region of the active region pattern of the initial oxide layer; using the The source injection blocking layer and the gate are used as a mask to form a source diffusion region and a drain diffusion region inside the epitaxial layer. The manufacturing method of the DMOS device of the present invention reduces the number of mask plates used in the traditional technology, thus simplifying the product processing technology, shortening the product processing flow, and improving the production efficiency and economic benefits of the product.

Description

A kind of manufacturing method of DMOS device

technical field

The invention belongs to the technical field of semiconductors, and in particular relates to a manufacturing method of a DMOS device.

Background technique

A circuit based on a double-diffused metal-oxide-semiconductor (MOS) field-effect transistor, referred to as DMOS (double-diffused MOSFET), has a structure similar to that of a CMOS device, and also has electrodes such as source, drain, and gate. DMOS devices mainly include two types: vertical double-diffused metal oxide semiconductor field effect transistor VDMOSFET (vertical double-diffused MOSFET) and lateral double-diffused metal oxide semiconductor field effect transistor LDMOSFET (lateral double-dif fused MOSFET). In power applications, since DMOS adopts a vertical device structure (such as a vertical NPN bipolar transistor), it has high current drive capability, low Rds on-resistance, and high breakdown voltage.

At present, the manufacturing process of DMOS devices includes Planar DMOS and Trench DMOS. Among them, the traditional process of PlanarDMOS usually requires six masks to realize the process design of the product, which are guard ring (ie field limiting ring, Ring) mask, active Area (AA) mask, polycrystalline (Poly) mask, source region (SRC) mask, contact hole (Contact) mask and metal (Metal) mask, and some have higher requirements The products may also add a passivation layer mask. For example, as shown in Figure 1, when making the source and drain, it is usually necessary to use a source region mask for photolithography and etching to form the source and drain region patterns and between the source and drain region patterns The remaining photoresist 9 becomes a blocking layer for the implantation of the source and drain regions when implanting ions (such as N+), thereby ensuring the smooth formation of the source and drain regions (such as N+).

As we all know, in the chip manufacturing industry, the price of a product is often determined by the number of layers of the mask. The more layers of the mask, the more complex the product process, the longer the processing process, and the higher the cost. Therefore, in similar products Reducing the number of mask layers in the manufacturing process means reducing product processing costs and improving production efficiency, which is of great significance.

Contents of the invention

The invention provides a manufacturing method of a DMOS device, which reduces the number of mask plates used in the device manufacturing process, simplifies the product processing technology, and shortens the product processing flow.

A kind of manufacturing method of DMOS device provided by the invention, comprises the steps:

forming an initial oxide layer on the surface of the epitaxial layer of the silicon substrate;

Perform photolithography and etching on the silicon substrate formed with the initial oxide layer by using a mask, and form an active region pattern and a source implant stopper located in the region of the active region pattern on the initial oxide layer layer;

forming a gate in the active area pattern area of the initial oxide layer;

A source diffusion region and a drain diffusion region are formed inside the epitaxial layer by using the source injection blocking layer and the gate as a mask.

According to the manufacturing method of the DMOS device provided by the present invention, the mask plate has an active area pattern and a source injection blocking pattern, and the source injection blocking pattern is located in the area of the active area pattern.

The method of the present invention improves the traditional active region mask so that it has the function of the traditional source region mask, so that the source region mask can be omitted and the DMOS device can be manufactured. Reduce one photolithography process.

Further, forming a gate in the active region pattern area of the initial oxide layer specifically includes:

forming a gate oxide layer on the silicon substrate formed with the source pattern and the source injection blocking layer;

forming a polysilicon layer on the gate oxide layer;

Photolithography and etching are performed on the silicon substrate formed with the polysilicon layer, and a gate is formed in the active area pattern area of the initial oxide layer.

According to the manufacturing method of the DMOS device provided by the present invention, after forming the initial oxide layer, it further includes: forming a protection ring inside the epitaxial layer. Specifically, the guard ring is formed after forming the initial oxide layer and before forming the active region pattern and the source injection blocking layer.

Further, forming a guard ring inside the epitaxial layer specifically includes:

performing photolithography and etching on the silicon substrate formed with the initial oxide layer, and forming a guard ring pattern on the initial oxide layer;

Ions are implanted into the silicon substrate formed with the guard ring pattern, and annealed at 1100-1200° C. for 160-200 minutes to form a guard ring inside the epitaxial layer.

According to the manufacturing method of the DMOS device provided by the present invention, the source diffusion region and the drain diffusion region are N+ regions.

Further, before forming the source diffusion region and the drain diffusion region, it also includes:

Implanting P-type ions into the silicon substrate formed with the source implantation blocking layer and the gate, and annealing at 1100-1200° C. for 100-200 minutes to form a P- region inside the epitaxial layer.

Furthermore, the P-region is formed after forming the source injection blocking layer and the gate and before forming the source diffusion region and the drain diffusion region.

According to the manufacturing method of the DMOS device provided by the present invention, the source diffusion region and the drain diffusion region are N+ regions, and the source injection blocking layer and the gate are used as a mask to form the inside of the epitaxial layer. The source diffusion region and the drain diffusion region specifically include:

Implanting N-type ions into the silicon substrate formed with the source injection blocking layer and the gate, and annealing at 800-900°C for 30-40 minutes, forming a source diffusion region and a drain in the epitaxial layer Extremely diffuse area.

Further, after forming the source diffusion region and the drain diffusion region, it also includes:

forming a dielectric layer on the silicon substrate formed with the source diffusion region and the drain diffusion region;

Perform photolithography on the silicon substrate formed with the dielectric layer, and etch the dielectric layer and its the lower source injection blocking layer, and form a contact hole at the position of the source injection blocking layer above the epitaxial layer.

Further, after forming the contact hole, it also includes:

P-type ions are implanted into the silicon substrate formed with the contact hole, and annealed at 800-900° C. for 30-40 minutes to form a P+ region inside the epitaxial layer.

Further, after forming the P+ region, it also includes:

forming a metal layer on the silicon substrate formed with the P+ region; and

Photolithography and etching are performed on the silicon substrate formed with the metal layer, and a metal wiring structure is formed on the silicon substrate.

More specifically, the manufacturing method of the DMOS device provided by the present invention includes the steps carried out in the following order:

forming the initial oxide layer on the surface of the epitaxial layer of the silicon substrate;

forming the guard ring inside the epitaxial layer;

Photolithography and etching are performed on the silicon substrate formed with the initial oxide layer by using a mask, and the active region pattern and the active region pattern are formed on the initial oxide layer. source injection blocking layer;

forming the gate in the active pattern area of the initial oxide layer;

forming the P-region inside the epitaxial layer;

forming the source diffusion region and the drain diffusion region inside the epitaxial layer by using the source injection blocking layer and the gate as a mask;

forming the dielectric layer on the silicon substrate formed with the source diffusion region and the drain diffusion region, and forming the contact hole at the position of the source injection barrier layer above the epitaxial layer;

The P+ region is formed inside the epitaxial layer.

Wherein, the source diffusion region and the drain diffusion region are N+ regions.

The manufacturing method of the DMOS device described in the present invention reduces the number of layers of the mask used in the traditional DMOS device manufacturing process and saves a photolithography process, so the product processing technology is simplified, the product processing process is shortened, and the production process is improved. Product production efficiency and economic benefits.

Description of drawings

Fig. 1 is the schematic diagram of the DMOS device manufacturing method of prior art;

2 to 8 are schematic diagrams of the manufacturing process of a DMOS device manufacturing method according to an embodiment of the present invention;

Reference signs:

1. Epitaxial layer; 2. Initial oxide layer; 3. Guard ring; 4. Source injection barrier layer; 5. Gate oxide layer; 6. Polysilicon layer; 7. Dielectric layer; 8. Contact hole; 9. Photoresist .

Detailed ways

In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings and embodiments of the present invention. Obviously, the described embodiments are the Some, but not all, embodiments are invented. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

Example

The manufacturing method of the DMOS device of the present invention includes: forming an initial oxide layer on the surface of the epitaxial layer of the silicon substrate; using a mask plate to carry out photolithography and etching on the silicon substrate formed with the initial oxide layer, in the Forming an active region pattern and a source injection blocking layer located in the region of the active region pattern on the initial oxide layer; forming a gate in the region of the active region pattern of the initial oxide layer; using the source injection blocking layer layer and the gate as a mask to form a source diffusion region and a drain diffusion region inside the epitaxial layer. Specifically, the mask plate has an active area pattern and a source injection blocking pattern, and the source injection blocking pattern is located in the active area pattern area.

The manufacturing method of the DMOS device provided by the present invention, by improving the traditional mask plate in the active region, makes it have the function of the mask plate in the traditional source region at the same time, so that the source electrode can be omitted when the DMOS device is manufactured Mask plate and reduce a photolithography process, thereby simplifying the product processing technology, shortening the product processing process, and improving the production efficiency and economic benefits of the product.

It can be understood that the manufacturing method of the DMOS device of the present invention also includes other processes necessary in the manufacturing process of the DMOS device, such as forming a body region and a guard ring inside the epitaxial layer, and forming a source, a drain, and a metal wiring structure, etc., which can adopt conventional techniques in the art.

As an embodiment of the present invention, the following will take an N-channel DMOS device as an example to describe in detail, that is, the source diffusion region and the drain diffusion region are N+ regions with a high doping concentration. It can be understood that, The method of the present invention is also applicable to the manufacture of P-channel DMOS devices.

In the manufacturing method of the DMOS device of the present invention, firstly, a specific mask plate having an active region pattern and a source injection blocking pattern is obtained, and the source injection blocking pattern is located in the region of the active region pattern. More specifically, the source injection blocking pattern is the pattern of the traditional source region mask, that is, the present invention makes the pattern of the traditional source region mask on the active region pattern of the traditional active region mask In the region, thereby form the above-mentioned reticle with active region pattern and source implantation blocking pattern of the present invention; The positions of the source diffusion region and the drain diffusion region are preset in advance, and the source injection blocking pattern is designed between the source diffusion region and the drain diffusion region (two N+ regions), so that when N+ implantation The area between the two N+ regions is blocked; the shape and size of the active region pattern and the source injection blocking pattern according to the present invention can be reasonably designed according to the requirements of the DMOS device structure, such as the source injection blocking The width of the pattern (that is, the distance between two N+ regions) can be designed to be 1.5-2.5um.

Further, the manufacturing method of DMOS device of the present invention comprises the following steps:

Step 1, forming an initial oxide layer on the surface of the epitaxial layer of the silicon substrate;

Specifically, as shown in FIG. 2, the silicon substrate with the epitaxial layer 1 can be a conventional epitaxial wafer in the field, and the epitaxial layer 1 can also be grown on the silicon substrate by a conventional method in the field; the initial The oxide layer 2 can be formed on the surface of the epitaxial layer 1 by wet oxidation, and the thickness of the initial oxide layer 2 can be For example

Step 2, forming a guard ring inside the epitaxial layer;

Specifically, first spin-coat photoresist on the initial oxide layer 2, and use a guard ring mask to expose, and after developing a guard ring pattern, use the guard ring pattern as a mask to wet etch the An initial oxide layer 2, so as to form a protective ring pattern on the initial oxide layer 2; then, implant P- ions with conventional energy and dose, for example, the implantation energy of P- ions can be 60-80kev, and the implant dose can be 3×10 ^13-3 ×10 ¹⁴ /cm ² , annealed at 1100-1200°C for 160-200 minutes, for example, after annealing at 1150°C for 180 minutes, a protective ring 3 is formed inside the epitaxial layer 1; in addition, after annealing After that, the thickness of the initial oxide layer 2 grows as

Step 3, using the mask plate to perform photolithography and etching on the silicon substrate formed with the initial oxide layer, forming the active area pattern and the active area pattern on the initial oxide layer said source injection blocking layer within the region;

Specifically, as shown in FIG. 3, spin-coat photoresist on the silicon substrate on which the guard ring is formed (that is, on the initial oxide layer 2 and the guard ring pattern), and use the above-mentioned mask for exposure, After developing and forming the active area pattern, using the active area pattern on the photoresist layer as a mask to wet etch the initial oxide layer 2, thereby forming an active area pattern on the initial oxide layer 2, and A source injection blocking layer 4 is formed between the two N+ regions in the pattern area of the active region.

Step 4, forming a gate in the active area pattern area of the initial oxide layer;

Specifically, as shown in FIG. 4, the silicon substrate formed with the source region pattern and the source injection blocking layer 4 is oxidized to form a gate oxide layer 5 (ie, a silicon oxide layer), the thickness of which can be for For example Subsequently, polysilicon can be deposited on the surface of gate oxide layer 5 and doped simultaneously, thereby forming polysilicon layer 6, and its thickness can be For example Spin-coat photoresist on the polysilicon layer 6, and use a polysilicon mask to expose, after developing to form a grid pattern, dry etching, so that the active area pattern area of the initial oxide layer 2 A gate is formed inside (that is, outside the preset source diffusion region and drain diffusion region), which includes a gate oxide layer 5 and a polysilicon layer 6 on the gate oxide layer 5 .

Step 5, forming a P-region inside the epitaxial layer;

Specifically, as shown in FIG. 5, P-type ions are implanted into the silicon substrate on which the source implantation blocking layer 4 and the gate are formed. The implantation energy may be 60-80 keV, and the implantation dose may be 3×10 ¹³ ~ 3.5×10 ¹³ /cm ² , the implanted P-type ions enter the epitaxial layer 1 through the region between the gate and source implantation barrier layer 4 (that is, the preset N+ region); as shown in Figure 6, then After annealing at 1100-1200° C. for 100-200 minutes, for example, at 1150° C. for 180 minutes, a P- region is formed inside the epitaxial layer 1 .

Step 6, using the source injection blocking layer and the gate as a mask to form a source diffusion region and a drain diffusion region inside the epitaxial layer;

Specifically, as shown in FIG. 7, N-type ions are implanted into the silicon substrate formed with the source implantation barrier layer 4 and the gate. The implantation energy may be 80-120 keV, and the implantation dose may be 5×10 ¹⁵ -1×10 ¹⁶ /cm ² , anneal at 800-900°C for 30-40 minutes, for example, after annealing at 850°C for 30 minutes, a source diffusion region is formed in the preset N+ region inside the epitaxial layer 1 N+ and drain diffusion region N+ (that is, N+ region).

Step 7, forming the dielectric layer on the silicon substrate formed with the source diffusion region and the drain diffusion region, and forming the contact hole at the position of the source injection barrier layer above the epitaxial layer;

Specifically, as shown in FIG. 8 , it is possible to first form a layer with a thickness of, for example, Undoped silica glass (USG), and then form a thickness on the undoped silica glass, for example, borophosphosilicate glass (BSPG), thereby forming a dielectric layer 7; using a contact hole mask to perform photolithography, and controlling the ratio of the etching rate of the dielectric layer to the etching rate of the epitaxial layer to 15-20:1, such as 15:1, dry etching the dielectric layer 7 and the source injection blocking layer 4 below, so that the source injection blocking layer 4 above the epitaxial layer 1 Contact holes 8 are formed thereon.

Step 8, forming a P+ region inside the epitaxial layer;

Specifically, to implant P-type ions into the silicon substrate formed with the contact hole 8, the implantation energy may be 60-80 keV, and the implantation dose may be 1×10 ¹⁵ -1.5×10 ¹⁵ /cm ² , at 800-900 After annealing at 900° C. for 30 to 40 minutes, for example, 30 minutes at 900° C., a P+ region is formed inside the epitaxial layer 1 .

After the P+ region is formed, the rest of the DMOS device manufacturing process can be completed according to the conventional process until the DMOS device is manufactured. For example, conventional methods can be used to form a metal layer on the silicon substrate formed with the P+ region, and a metal mask is used to perform photolithography and etching, so as to form metal wiring structures and the like on the silicon substrate.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present invention. scope.

Claims (10)

1. a manufacture method for DMOS device, is characterized in that, comprises the steps:

Initial oxide layer is formed in the epi-layer surface of silicon substrate;

Utilize mask plate to carry out photoetching and etching to the silicon substrate being formed with described initial oxide layer, described initial oxide layer is formed source region figure and the source electrode implant blocking layer being positioned at graphics field, described active area;

Grid is formed in the graphics field, active area of described initial oxide layer;

Described source electrode implant blocking layer and described grid is utilized to form source diffusion region and drain diffusion regions as mask in described epitaxial loayer inside.

2. manufacture method according to claim 1, is characterized in that, forms grid, specifically comprise in the graphics field, active area of described initial oxide layer:

The silicon substrate being formed with described source region figure and described source electrode implant blocking layer forms grid oxic horizon;

Described grid oxic horizon forms polysilicon layer;

Photoetching, etching are carried out to the silicon substrate being formed with described polysilicon layer, in the graphics field, active area of described initial oxide layer, forms grid.

3. manufacture method according to claim 1, is characterized in that, after the described initial oxide layer of formation, also comprises: form guard ring in described epitaxial loayer inside.

4. manufacture method according to claim 3, is characterized in that, forms guard ring, specifically comprise in described epitaxial loayer inside:

Photoetching, etching are carried out to the silicon substrate being formed with described initial oxide layer, described initial oxide layer is formed guard ring figure;

Ion is injected to the silicon substrate being formed with described guard ring figure, and anneals 160 ~ 200 minutes at 1100 ~ 1200 DEG C, form guard ring in described epitaxial loayer inside.

5., according to described manufacture method arbitrary in Claims 1-4, it is characterized in that, described source diffusion region and drain diffusion regions are N+ district.

6. manufacture method according to claim 5, is characterized in that, before the described formation source diffusion region of formation and drain diffusion regions, also comprises:

To forming the silicon substrate implanting p-type ion stating source electrode implant blocking layer and described grid to some extent, and annealing 100 ~ 200 minutes at 1100 ~ 1200 DEG C, forming P-district in described epitaxial loayer inside.

7. manufacture method according to claim 5, it is characterized in that, described source diffusion region and drain diffusion regions are N+ district, then utilize described source electrode implant blocking layer and described grid to form source diffusion region and drain diffusion regions as mask in described epitaxial loayer inside, specifically comprise:

Inject N-type ion to forming the silicon substrate stating source electrode implant blocking layer and described grid to some extent, and anneal 30 ~ 40 minutes at 800 ~ 900 DEG C, form source diffusion region and drain diffusion regions in described epitaxial loayer inside.

8. manufacture method according to claim 5, is characterized in that, after the described source diffusion region of formation and drain diffusion regions, also comprises:

The silicon substrate being formed with described source diffusion region and drain diffusion regions forms dielectric layer;

Photoetching is carried out to the silicon substrate being formed with described dielectric layer, be the source electrode implant blocking layer etching described dielectric layer and below thereof under the condition of 15 ~ 20 times of etch rate to described epitaxial loayer to the etch rate of described dielectric layer, the source electrode implant blocking layer position of side forms contact hole on said epitaxial layer there.

9. manufacture method according to claim 8, is characterized in that, after the described contact hole of formation, also comprises:

To the silicon substrate implanting p-type ion being formed with described contact hole, and anneal 30 ~ 40 minutes at 800 ~ 900 DEG C, form P+ district in described epitaxial loayer inside.

10. manufacture method according to claim 9, is characterized in that, after the described P+ district of formation, also comprises:

The silicon substrate being formed with described P+ district forms metal level; And

Photoetching, etching are carried out to the silicon substrate being formed with described metal level, described silicon substrate forms metal connection structure.