CN104810266A - Semiconductor device forming method - Google Patents

Abstract

A method for forming a semiconductor device, comprising: providing a substrate, a gate structure is formed on the surface of the substrate; forming doped regions in the substrate on both sides of the gate structure; forming a first metal layer on the surface of the doped region; forming a first metal contact layer on the surface of the heterogeneous region; forming a second metal layer on the surface of the first metal contact layer; performing a second annealing treatment on the second metal layer to diffuse the metal in the second metal layer into the first metal contact layer , transforming the first metal contact layer into a second metal contact layer, the Schottky barrier height between the second metal contact layer and the substrate is lower than the Schottky barrier height between the first metal contact layer and the substrate. The present invention uses an annealing process to diffuse metal atoms into the first metal contact layer, and the metal atoms in the formed second metal contact layer are evenly distributed, which has a strong ability to reduce the Schottky barrier between the second metal contact layer and the substrate A high degree of capability, thereby reducing the contact resistance of semiconductor devices and optimizing the driving performance of semiconductor devices.

Description

Method of forming semiconductor device

technical field

The invention relates to the technology in the field of semiconductor manufacturing, in particular to a method for forming a semiconductor device.

Background technique

As the integration of semiconductor devices continues to increase, the critical dimensions of semiconductor devices continue to decrease, and correspondingly many problems have arisen, such as the corresponding increase in the surface resistance and contact resistance of the device's drain-source region, resulting in a decrease in the response speed of the device and signal occurrence. Delay. Therefore, an interconnection structure with low resistivity becomes a key element in the manufacture of highly integrated semiconductor devices.

In order to reduce the contact resistance of the drain-source region of the device, a process method of metal silicide is introduced. The metal silicide has a lower resistivity and can significantly reduce the contact resistance of the drain-source. Metal silicides and salicides and their formation processes have been widely used to reduce the surface resistance and contact resistance of device sources and drains, thereby reducing the resistance-capacitance delay time.

In the existing salicide technology, nickel silicide is often used as the metal silicide. Since the metal silicide formed by using the nickel silicide has lower contact resistance, less silicon consumption, and is easy to achieve a narrower line width, nickel silicide is regarded as a relatively ideal metal silicide.

However, with the continuous reduction of the feature size of semiconductor devices, the contact resistance of semiconductor devices formed by the existing metal silicide technology has been difficult to meet the process requirements. It is urgent to find a new method of forming metal silicides to reduce the semiconductor The contact resistance of the device improves the operating speed of the semiconductor device.

Contents of the invention

The problem solved by the invention is to provide a method for forming a semiconductor device, reduce the contact resistance of the semiconductor device, and optimize the driving performance of the semiconductor device.

In order to solve the above problems, the present invention provides a method for forming a semiconductor device, comprising: providing a substrate, a gate structure is formed on the surface of the substrate; doping the substrates on both sides of the gate structure, and Forming a doped region in the substrate; forming a first metal layer on the surface of the doped region; performing a first annealing treatment on the first metal layer, forming a first metal contact layer on the surface of the doped region; A second metal layer is formed on the surface of the first metal contact layer, and the second metal layer has the function of adjusting the Schottky barrier height between the first metal contact layer and the substrate; performing second annealing on the second metal layer treatment, the metal atoms in the second metal layer are diffused into the first metal contact layer, the first metal contact layer is converted into the second metal contact layer, and the Schottky barrier between the second metal contact layer and the substrate The height is lower than the Schottky barrier height between the first metal contact layer and the substrate.

Optionally, metal atoms in the second metal layer include Al, Pt, Pd or rare earth metals, wherein the rare earth metals are Yb or Er.

Optionally, when the metal atoms of the second metal layer include Al, the material of the second metal layer is Al, TiAl or TaAl.

Optionally, the material of the second metal contact layer is NiAlSi.

Optionally, the second metal layer is formed by atomic layer deposition, chemical vapor deposition or physical vapor deposition.

Optionally, the thickness of the second metal layer is 5 angstroms to 20 angstroms.

Optionally, the second annealing treatment is immersion annealing, spike annealing, millisecond annealing or laser annealing.

Optionally, the process parameters of the immersion annealing are: the annealing temperature is 200°C to 600°C, and the annealing time is 5 seconds to 120 seconds; the process parameters of the spike annealing are: the annealing temperature is 300°C to 800°C; The process parameters of millisecond annealing or laser annealing are: the annealing temperature is 500°C to 900°C, and the annealing time is 0.1 millisecond to 1 second.

Optionally, before forming the second metal layer, a step is further included: performing a pre-cleaning treatment on the surface of the first metal contact layer, and the process of the pre-cleaning treatment is wet etching or plasma cleaning.

Optionally, the material of the first metal layer is single metal or alloy of Ni, W, Ti, Ta, Pt, Co.

Optionally, the first annealing treatment is one-step annealing treatment or multi-step annealing treatment.

Optionally, the multi-step annealing treatment includes a first-step annealing treatment and a second-step annealing treatment.

Optionally, the first step annealing treatment is immersion annealing, the annealing temperature is 250 to 350 degrees, and the annealing time is 20 seconds to 90 seconds; or the first step annealing treatment is millisecond annealing, and the annealing temperature is 650 degrees to 950 degrees, the annealing time is 0.25 milliseconds to 20 milliseconds.

Optionally, the second step annealing is immersion annealing, the annealing temperature is 350 to 500 degrees, and the annealing time is 20 seconds to 90 seconds; or the second step annealing is spike annealing, and the annealing temperature is 350 degrees to 550 degrees.

Optionally, before performing the first annealing treatment after forming the first metal layer, a step is further included: forming a protective layer on the surface of the first metal layer.

Optionally, the material of the protection layer is Ti, Ta, TiN or TaN.

Optionally, after the first metal contact layer is formed, the protection layer is removed.

Optionally, before forming the doped region, further steps are included: forming grooves in the substrate on both sides of the gate structure; and forming a stress layer filling the grooves by using a selective epitaxy process.

Optionally, the formed semiconductor device is an NMOS transistor, a PMOS transistor or a CMOS transistor.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the present invention, a first metal layer is formed on the surface of the doped region; a first metal contact layer is formed after the first annealing treatment is performed on the first metal layer; a second metal layer is formed on the surface of the first metal contact layer, and the second metal layer has adjusting the Schottky barrier height between the first metal contact layer and the substrate; performing a second annealing treatment on the second metal layer, so that metal atoms in the second metal diffuse into the first metal contact layer, and, Due to the effect of the annealing treatment, the distribution of metal atoms in the second metal contact layer is more uniform, and the uniform distribution of metal atoms is more conducive to reducing the effective work function of the second metal contact layer, so that the metal atoms regulate the second metal contact layer. The ability of the height of the Schottky barrier between the substrate and the substrate is effectively brought into play, and the reduction of the height of the Schottky barrier is conducive to reducing the contact resistivity, thereby reducing the contact resistance of the semiconductor device and increasing the operating speed of the semiconductor device.

Further, the material of the second metal layer of the present invention is TiAl, wherein the effective work function of the metal atom Al is low, and after being diffused into the first metal contact layer to form the second metal contact layer, the contact between the second metal contact layer and the lining can be reduced. The height of the Schottky barrier between the bottom; and, the Ti in the second metal layer has a certain inhibitory effect on the diffusion of Al atoms, preventing the diffusion of Al atoms from being too fast, and an appropriate diffusion speed is more conducive to the diffusion of Al atoms in the second metal layer. The uniform distribution in the metal contact layer further reduces the Schottky barrier height between the second metal contact layer and the substrate, thereby reducing the contact resistance of the semiconductor device and optimizing the driving performance of the semiconductor device.

Furthermore, the process of forming the first metal contact layer is a two-step annealing treatment, and the material of the first metal contact layer is NiSi. NiSi has the characteristics of low resistivity and high stability among nickel silicide series materials, so that the second The two-metal contact layer also has the characteristics of low resistivity and high stability, which further optimizes the electrical performance of the semiconductor device.

Description of drawings

1 to 3 are schematic cross-sectional structural diagrams of a semiconductor device formation process provided by an embodiment of the present invention;

4 to 9 are schematic cross-sectional structural views of the formation process of a semiconductor device provided by another embodiment of the present invention.

Detailed ways

It can be seen from the background art that the contact resistance of the semiconductor device formed in the prior art is large, and the operating speed of the semiconductor device is slow.

The contact resistance of semiconductor devices has a two-dimensional size dependence. With the continuous reduction of the feature size of semiconductor devices, the proportion of contact resistance in the total parasitic resistance of semiconductor devices is increasing, which seriously affects the driving ability of semiconductor devices. Conventional metal The silicide process is not sufficient to reduce the contact resistance of semiconductor devices.

According to the analysis of the influencing factors of contact resistance, it is found that the contact resistance is determined by the contact resistivity and the contact area. Specifically, the contact resistance is directly proportional to the contact resistivity and inversely proportional to the contact area. With the proportional reduction of semiconductor devices, the contact area shrinks at the speed of the square of the device size reduction speed. Therefore, it is difficult to reduce the contact resistance by increasing the contact area, and it is easier to reduce the contact resistivity. Therefore, the contact resistance of the semiconductor device can be reduced by reducing the contact resistivity.

The contact resistance of semiconductor devices is the contact resistance between metal and semiconductor. From the perspective of metal-semiconductor contact theory, the semiconductor energy band at the interface between semiconductor and metal is bent to form a high potential energy region, which is Schottky Potential barrier (SB: Schottky Barrier), the electrons in the semiconductor substrate must have energy higher than this barrier to cross the barrier and flow into the metal. The contact resistivity is closely related to the Schottky barrier height (SBH: Schottky Barrier Height) of the metal-semiconductor contact and the doping concentration of the semiconductor. Specifically, the contact resistivity is proportional to the height of the Schottky barrier and is proportional to The doping concentration is inversely proportional.

Using a conventional metal-semiconductor contact system, the metal material is NiSi, the semiconductor material is Si, the Schottky barrier height between the metal and semiconductor is about 0.6ev to 0.75ev, and the Schottky barrier height is a constant value. If necessary Reducing the contact resistivity requires increasing the doping concentration of the source and drain regions, and the doping concentration in the source and drain regions is limited by the solid solubility of dopant ions in the substrate material, and increasing the doping concentration of the source and drain regions The concentration will affect other electrical properties of the semiconductor device, therefore, it is difficult to reduce the contact resistance by increasing the doping concentration.

Based on the above analysis, it can be seen that reducing the metal-semiconductor Schottky barrier height is the most effective way to reduce the contact resistivity. The height of the metal-semiconductor Schottky barrier is proportional to the difference between the effective work function of the metal and the semiconductor, and the height of the metal-semiconductor Schottky barrier can be reduced by reducing the effective work function of the metal. Therefore, by selecting a suitable low potential Barrier contact materials (low work function materials) can achieve the purpose of reducing the height of the metal-semiconductor Schottky barrier, thereby reducing the contact resistivity, reducing the contact resistance of semiconductor devices, increasing the operating speed of semiconductor devices, and optimizing the drive of semiconductor devices performance.

To this end, an embodiment of the present invention provides a method for forming a semiconductor device, and FIG. 1 to FIG. 3 are schematic cross-sectional structure diagrams of the formation process of the semiconductor device provided in this embodiment.

Referring to FIG. 1, a substrate 100 is provided, an isolation structure 101 is formed in the substrate 100, a gate structure is formed on the surface of the substrate 100, and the gate structure includes a gate dielectric layer 111 on the surface of the substrate 100, and The gate electrode layer 112 located on the surface of the gate dielectric layer 111; the sidewall 102 is formed on the surface of the substrate 100, and the sidewall 102 is located on the sidewalls on both sides of the gate structure; the substrate on both sides of the gate structure 100 is doped to form doped regions 103 in the substrate 100 on both sides of the gate structure. ,

Referring to FIG. 2 , a metal layer is formed on the surface of the doped region 103 ; the metal layer is annealed to form a first metal contact layer 104 .

The material of the metal layer is a single metal or alloy of Ni, W, Ti, Ta, Pt, Co, which is used to provide metal atoms for subsequent formation of the metal contact layer. In this embodiment, the material of the metal layer is Ni.

In this embodiment, the material of the metal layer is Ni, and the material of the substrate 100 is Si. Under the action of annealing treatment, the material of the metal layer and the material of the substrate 100 undergo a silicide reaction to form a first metal contact. Layer 104, the material of the first metal contact layer 104 is NiSi.

Referring to FIG. 3 , ion implantation 106 is performed on the first metal contact layer 104 (please refer to FIG. 2 ) to transform the first metal contact layer 104 into a second metal contact layer 107 .

In order to reduce the Schottky barrier height between the first metal contact layer 104 and the substrate 100, the first metal contact layer 104 can be ion-implanted 106 with atoms with a lower work function, in order to reduce the first metal contact layer formed after doping. The Schottky barrier height between the two metal contact layers 107 and the substrate 100 .

The implanted ions of the ion implantation 106 are Al, Pt, Pd or rare earth metals, wherein the rare earth metals are Yb or Er.

However, the degree of reduction in the contact resistance of the semiconductor device formed by the above method is limited, and it still cannot meet the requirement of improving the driving performance of the semiconductor device.

According to the research on the formation method of the above-mentioned semiconductor device, it is found that the ion implanted into the first metal contact layer 105 is unevenly distributed in the semiconductor device, and because the ion concentration distribution of the ion implantation process presents a peak characteristic, the first metal contact layer 105 The implanted ions also present a distribution characteristic similar to Gaussian distribution, so that the ability to adjust the height of the Schottky barrier between the second metal contact layer 107 and the substrate 100 is limited, and the contact resistance of the semiconductor device is still relatively large. Moreover, due to the poor controllability of the ion implantation process, the implanted ion content at the bottom of the second metal contact layer 107 may be too small or the ion implantation into the doped region 103 will not only reduce the contact between the second metal contact layer 107 and the substrate 100 The height of the Schottky barrier between them is limited, and other electrical properties of the semiconductor device may be deteriorated due to ion implantation into the doped region 103 .

To this end, another embodiment of the present invention also provides a method for forming a semiconductor device. After forming the first metal contact layer, a second metal layer is formed on the surface of the first metal contact layer, and a second annealing is performed on the second metal layer. treatment, the metal in the second metal layer is diffused into the first metal contact layer, the first metal contact layer is converted into the second metal contact layer, and the Schottky barrier height between the second metal contact layer and the substrate It is lower than the Schottky barrier height between the first metal contact layer and the substrate. The present invention adopts the method of annealing to diffuse the metal to the second metal contact layer, so that the metal is evenly distributed in the second metal contact layer, effectively reducing the metal-semiconductor Schottky barrier height, thereby reducing the contact resistance of the semiconductor device , improve the operating speed of the semiconductor device, and optimize the driving performance of the semiconductor device.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

The semiconductor device formed in the present invention is an NMOS transistor, a PMOS transistor or a CMOS transistor. In this embodiment, the semiconductor device formed is an NMOS transistor for exemplary illustration.

4 to 9 are schematic cross-sectional structure diagrams of the formation process of the semiconductor device provided by this embodiment.

Referring to FIG. 4 , a substrate 200 is provided, and a gate structure is formed on the surface of the substrate 200 .

Specifically, the material of the substrate 200 is one of single crystal silicon, polycrystalline silicon, amorphous silicon or silicon on insulator; the substrate 200 can also be a Si substrate, a Ge substrate, a GeSi substrate or GaAs substrate.

Several epitaxial interface layers or strain layers can also be formed on the surface of the substrate 200 to improve the electrical performance of the semiconductor device.

In this embodiment, the substrate 200 is a Si substrate. In other embodiments of the present invention, the substrate may also be a substrate on which devices are formed, for example, transistors, capacitors or resistors, etc. are formed on the substrate.

In this embodiment, an isolation structure 201 is provided in the substrate 200 to prevent electrical connection between adjacent active regions. The material of the isolation structure 201 may be one or more of silicon oxide, silicon nitride or silicon oxynitride.

The gate structure includes: a gate dielectric layer 211 located on the surface of the substrate 200 , and a gate electrode layer 212 located on the surface of the gate dielectric layer 211 .

The gate structure may be a replacement gate structure, a metal gate structure or a polysilicon gate structure.

In this embodiment, the material of the gate dielectric layer 211 is silicon oxide or silicon oxynitride, and the material of the gate electrode layer 212 is polysilicon.

In another embodiment of the present invention, the material of the gate dielectric layer is a high-k dielectric material such as hafnium oxide, and the material of the gate electrode layer is metal or other conductive materials.

In order to prevent subsequent processes from damaging the sidewalls of the gate structure, in this embodiment, sidewalls 202 are formed on the sidewalls of the gate structure to protect the sidewalls of the gate structure. The side wall 202 is a single-layer structure or a multi-layer structure, and the material of the side wall 202 is silicon oxide, silicon nitride or silicon oxynitride.

It should also be noted that before forming the sidewall 202, a step may also be included: doping the substrate 200 on both sides of the gate structure to form a lightly doped region (LDD: Lightly Doped Drain), the lightly doped region It can alleviate the hot carrier effect (HCE: Hot carrier Effect) of semiconductor devices and improve the electrical performance of semiconductor devices.

Referring to FIG. 5 , the substrate 200 on both sides of the gate structure is doped to form a doped region 203 in the substrate 200 .

In this embodiment, the doping is performed by using an ion implantation process. In the embodiment of the present invention, the formed semiconductor device is an NMOS transistor for exemplary illustration, and the implanted ions of the ion implantation are N-type ions, and the N-type ions are P, As or Sb.

As an embodiment, the process parameters of the ion implantation process are: the implanted ions are P, the implantation energy is 10kev to 50kev, and the implantation dose is 1E18atom/cm ² to 5E20atom/cm ² .

In other embodiments, when the formed semiconductor device is a PMOS transistor, the implanted ions of the ion implantation are P-type ions, and the P-type ions are B, Ga or In. As an example, the process parameters of the ion implantation process are as follows: the implanted ions are B, the implantation energy is 5kev to 50kev, and the implantation dose is 1E17atom/cm ² to 5E19atom/cm ² .

After forming the doped region 203, it may also include the step of annealing the substrate 200, activating the dopant ions to redistribute the dopant ions in the substrate 200; lattice damage.

In other embodiments of the present invention, before forming the doped region, further steps are included: forming grooves in the substrate on both sides of the gate structure; forming a stress layer that fills the grooves by using a selective epitaxial process . As an embodiment, the formed semiconductor device is an NMOS transistor, the material of the stress layer is SiC or SiCP, and the stress layer applies tensile stress to the channel region of the semiconductor device to improve the electron mobility of the channel region, thereby Improve the operating speed of the semiconductor device; As another embodiment, the formed semiconductor device is a PMOS transistor, the material of the stress layer is SiGe or SiGeB, and the stress layer applies compressive stress to the semiconductor device to improve the space of the channel region. Hole mobility, thereby improving the operating speed of semiconductor devices and optimizing the electrical properties of semiconductor devices.

Referring to FIG. 6 , a first metal layer 204 is formed on the surface of the doped region 203 .

The material of the first metal layer 204 is single metal or alloy of Ni, W, Ti, Ta, Pt, Co. The formation process of the first metal layer 104 is physical vapor deposition, metal sputtering or atomic layer deposition.

The first metal layer 204 is used to provide metal atoms for the subsequent formation of the first metal contact layer. The material of the first metal layer 204 reacts with the material of the substrate 200 to form a first metal contact layer. The first metal layer 204 When the material of Ni is Ni, the material of the substrate 200 consumed by subsequent chemical reactions is low, and the line width of the formed first metal contact layer is narrow, and the process cost is relatively low.

In this embodiment, the material of the first metal layer 204 is Ni with a thickness of 50 angstroms to 200 angstroms, and the first metal layer 204 is formed by a physical vapor deposition process.

In this embodiment, in order to prevent the material of the first metal layer 204 from being oxidized by _O2 in the environment, after forming the first metal layer 204, a protective layer 205 is formed on the surface of the first metal layer 204, and the protective layer 205 makes The first metal layer 204 is isolated from O ₂ ; the material of the protection layer 205 is Ti, Ta, TiN or TaN.

Furthermore, in order to make the formed first metal layer 204 in close contact with the surface of the doped region 203 , before forming the first metal layer 204 , a step may be further included: cleaning the surface of the doped region 203 . In this embodiment, the cleaning process is wet etching to remove impurities on the surface of the doped region 203 and provide a good interface state for the formation of the first metal layer 204, so that the first metal layer 204 and the doped region The close contact of the surfaces of the 203 is beneficial to reduce the contact resistance between the subsequently formed first metal contact layer and the doped region 203 and improve the electrical performance of the semiconductor device.

Referring to FIG. 7 , a first annealing treatment is performed on the first metal layer 204 (please refer to FIG. 6 ), and a first metal contact layer 206 is formed on the surface of the doped region 203 .

The first metal contact layer 206 is used to reduce the contact resistance of the semiconductor device.

The first annealing treatment is one-step annealing treatment or multi-step annealing treatment. The multi-step annealing treatment includes a first-step annealing treatment and a second-step annealing treatment. In this embodiment, the multi-step annealing treatment on the first metal layer 204 is used as an exemplary illustration.

The first step annealing treatment can be immersion annealing, the annealing temperature is 250 degrees to 350 degrees, and the annealing time is 20 seconds to 90 seconds; the first step annealing treatment can also be millisecond annealing, the annealing temperature is 650 degrees to 950 degrees, the annealing time is 0.25 milliseconds to 20 milliseconds.

After the first annealing treatment, the nickel in the first metal layer 204 reacts with the silicon on the surface of the doped region 203 to form a Ni ₂ Si layer; a second annealing treatment is performed on the formed Ni ₂ Si layer.

The second step annealing treatment can be immersion annealing, the annealing temperature is 350 degrees to 500 degrees, and the annealing time is 20 seconds to 90 seconds; the second step annealing treatment can also be spike annealing, the annealing temperature is 350 degrees to 500 degrees 550 degrees.

After the second annealing treatment, the Ni ₂ Si continues to react with the silicon on the surface of the doped region 103 , and the first metal contact layer 206 is formed on the surface of the doped region 203 . The material of the first metal contact layer 206 is NiSi, NiSi has lower resistivity and higher stability than Ni ₂ Si. Therefore, the material of the first metal contact layer 206 formed after the two-step annealing treatment is NiSi, which is beneficial to improve the stability of the first metal contact layer 206 and reduce the resistance.

After forming the first metal contact layer 206 , a step is further included: removing the first metal layer 204 that has not chemically reacted with the substrate 200 . In this embodiment, a protective layer 205 is formed on the surface of the first metal layer 204 (please refer to FIG. 6 ), and the unreacted first metal layer 204 is removed at the same time as the protective layer 205, which is removed by a wet etching process. Unreacted first metal layer 204 and protective layer 205 . As an example, the etching liquid in the wet etching process is a mixed solution of sulfuric acid and hydrogen peroxide.

Referring to FIG. 8, a second metal layer 207 is formed on the surface of the first metal contact layer 206, and the second metal layer 207 has the function of adjusting the Schottky barrier height between the first metal contact layer 206 and the substrate 200. effect.

Although the first metal contact layer 206 is formed on the surface of the doped region 203, the formed first metal contact layer 206 is not enough to reduce the contact resistance of the semiconductor device to a desired range. Since the contact resistance is directly proportional to the contact resistivity, the contact resistance of the semiconductor device can be effectively reduced by reducing the contact resistivity. In this embodiment, the method of reducing the contact resistivity is used to reduce the contact resistance of the semiconductor device. Since the contact resistivity is related to the height of the Schottky barrier, the contact resistivity can be reduced by reducing the height of the Schottky barrier.

In order to reduce the Schottky barrier height between the first metal contact layer 206 and the substrate 200, the first metal contact layer 206 can be doped with a low potential barrier material (low effective work function material) to reduce the contact resistance rate, thereby reducing the contact resistance of the semiconductor device; and, the low barrier material also needs to meet the characteristics of little influence on the resistance of the first metal contact layer 206 itself, so as to prevent the Schottky barrier height from being reduced. However, it causes the problem that the resistance of the first metal contact layer 206 itself increases sharply, so as to prevent adverse effects on reducing the contact resistance of the semiconductor device. Therefore, the effective work function of the metal atoms of the second metal layer 207 is smaller than the effective work function of the metal atoms of the first metal layer.

Based on the above considerations, the metal atoms of the second metal layer 207 include Al, Pt, Pd or rare earth metals, wherein the rare earth metals are Yb or Er.

Because the cost of Al is lower, in this embodiment, the metal atoms of the second metal layer 207 include Al. When the metal atoms of the second metal layer 207 include Al, the material of the second metal layer 207 can be Al, TiAl or TaAl.

Al in the subsequent second metal layer 207 will diffuse into the first metal contact layer 206. If the material of the second metal layer 207 is Al, the subsequent Al diffusion rate may be too fast, resulting in the subsequent formation of the second metal contact layer. There is uneven distribution of Al in the metal, which is not conducive to improving the height of the Schottky barrier; therefore, in this embodiment, the material of the second metal layer 207 is TiAl or TaAl. Diffusion speed in the layer 206, makes Al distribute in the second metal contact layer as uniformly as possible, the material uniformity of the second metal contact layer formed is good, is more conducive to reducing the gap between the second metal contact layer and the substrate 200. The Schottky barrier height of .

The second metal layer 207 is formed by atomic layer deposition, chemical vapor deposition or physical vapor deposition.

In this embodiment, the material of the second metal layer 207 is TiAl, and the thickness of the second metal layer 207 is 5 angstroms to 20 angstroms.

It should also be noted that before forming the second metal layer 207, a step is further included: performing pre-cleaning treatment on the surface of the first metal contact layer 206, and the process of the pre-cleaning treatment is wet etching or plasma cleaning. The purpose of pre-cleaning the surface of the first metal contact layer 206 is to remove impurities on the surface of the first metal contact layer 206 and provide a good interface state for the formation of the second metal layer 207, so that Al in the subsequent second metal layer 207 It is easier to diffuse into the first metal contact layer 206 . This is because:

If there are impurities on the surface of the first metal contact layer 206, there will be holes between the second metal layer 207 formed on the surface of the first metal contact layer 206 with impurities and the first metal contact layer 206, and the Al in the second metal layer 207 It is difficult to diffuse into the first metal contact layer 206 through the holes.

Referring to FIG. 9 , the second annealing treatment is performed on the second metal layer 207 (please refer to FIG. 8 ), so that the metal in the second metal layer 207 diffuses into the first metal contact layer 206 (please refer to FIG. 8 ), The first metal contact layer 206 is converted into a second metal contact layer 208 .

In this embodiment, the material of the second metal layer 207 is TiAl, and the material of the first metal contact layer 206 is NiSi; under the process conditions of the second annealing treatment, Ti atoms are difficult to diffuse, and Al atoms diffuse to the first metal contact layer. 206 to form a second metal contact layer 208, and the material of the second metal contact layer 208 is NiAlSi.

Due to the lower effective work function of Al, its effective work function is 4.1ev to 4.3ev, the second metal contact layer 208 is compared with the first metal contact layer 206, and its effective work function has reduced, and the second metal contact layer 208 The difference between the effective work function and the substrate 200 is reduced, thereby reducing the height of the Schottky barrier between the second metal contact layer 208 and the substrate 200, achieving the purpose of reducing the contact resistivity, thereby reducing the contact resistance of the semiconductor device, Improving the driving performance of semiconductor devices.

In this embodiment, the first metal contact layer 206 with low resistivity is formed first, and then the second metal layer 207 is formed on the surface of the first metal contact layer 206, so that the formed second metal contact layer 208 itself Low resistance is beneficial to improve the operating speed of semiconductor devices.

It should be noted that the second annealing treatment in this embodiment is a different annealing step from the aforementioned first annealing treatment, and is not completed in the same process. If the second metal contact layer material (AlNiSi) is formed by annealing after the formation of the Ni-containing metal layer and the Al-containing metal layer, since the diffusion ability of Al is stronger than that of Ni, Al will be the first to combine with the substrate 200. The material reacts to form Al silicide, so that the remaining material of the substrate 200 that can react with Ni is less, and the content of Ni silicide is too low, because the resistivity of Al silicide is much greater than that of Ni silicide , so that the resistance of the formed second metal contact layer itself is too large, which is not conducive to optimizing the electrical performance of the semiconductor device.

In addition, the second annealing process is used in this embodiment to form the second metal contact layer 208, so that the distribution of metal atoms diffused into the first metal contact layer 206 is even, especially, between the second metal contact layer 208 and the lining The uniform distribution of Al atoms at the junction of the bottom 200 is more conducive to reducing the height of the Schottky barrier between the second metal contact layer 208 and the substrate 200 .

The second annealing treatment is immersion annealing, spike annealing, millisecond annealing or laser annealing.

When the second annealing treatment is immersion annealing, the process parameters of the immersion annealing are: the annealing temperature is 200°C to 600°C, and the annealing time is 5 seconds to 120 seconds.

When the second annealing treatment is spike annealing, the process parameters of the spike annealing are: the annealing temperature is 300°C to 800°C.

When the second annealing treatment is millisecond annealing or laser annealing, the process parameters of the millisecond annealing or laser annealing are: the annealing temperature is 500°C to 900°C, and the annealing time is 0.1 millisecond to 1 second.

After forming the second metal contact layer 208, a step is further included: removing the second metal layer 207 after the second annealing treatment, and the material of the second metal layer 207 at this time is mainly Ti atoms.

In summary, the technical solution of the semiconductor device provided by the present invention has the following advantages:

Firstly, the present invention forms the first metal layer on the surface of the doped region; forms the first metal contact layer after performing the first annealing treatment on the first metal layer; forms the second metal layer on the surface of the first metal contact layer, and the second metal The layer has the function of adjusting the height of the Schottky barrier between the first metal contact layer and the substrate; the second annealing treatment is performed on the second metal layer, so that the metal atoms in the second metal diffuse into the first metal contact layer, Moreover, due to the effect of the annealing treatment, the distribution of metal atoms in the second metal contact layer is relatively uniform, and the uniform distribution of metal atoms is more conducive to reducing the effective work function of the second metal contact layer, so that the metal atoms regulate the second metal contact layer. The ability of the height of the Schottky barrier between the contact layer and the substrate is effectively brought into play, and the reduction of the Schottky barrier is conducive to reducing the contact resistivity, thereby reducing the contact resistance of the semiconductor device and increasing the operating speed of the semiconductor device.

Secondly, the material of the second metal layer of the present invention is TiAl, wherein, the effective work function of the metal atom Al is low, and after diffusing into the first metal contact layer to form the second metal contact layer, the contact between the second metal contact layer and the substrate can be reduced. The height of the Schottky barrier between the bottom; and, the Ti in the second metal layer has a certain inhibitory effect on the diffusion of Al atoms, preventing the diffusion of Al atoms from being too fast, and an appropriate diffusion speed is more conducive to the diffusion of Al atoms in the second metal layer. The uniform distribution in the metal contact layer further reduces the Schottky barrier height between the second metal contact layer and the substrate, reduces the contact resistance of the semiconductor device, and optimizes the driving performance of the semiconductor device.

Again, the process of forming the first metal contact layer is a two-step annealing treatment. The material of the first metal contact layer is NiSi. NiSi has the characteristics of low resistivity and high stability among nickel silicide series materials, so that the second The metal contact layer also has the characteristics of low resistivity and high stability, which further optimizes the electrical performance of semiconductor devices.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (20)

1. A method for forming a semiconductor device, comprising: providing a substrate, a gate structure is formed on the surface of the substrate; Doping the substrates on both sides of the gate structure to form doped regions in the substrate; forming a first metal layer on the surface of the doped region; performing a first annealing treatment on the first metal layer to form a first metal contact layer on the surface of the doped region; forming a second metal layer on the surface of the first metal contact layer, the second metal layer has the function of adjusting the Schottky barrier height between the first metal contact layer and the substrate; performing a second annealing treatment on the second metal layer, so that the metal atoms in the second metal layer diffuse into the first metal contact layer, transforming the first metal contact layer into a second metal contact layer, and the second metal contact layer The Schottky barrier height between the layer and the substrate is lower than the Schottky barrier height between the first metal contact layer and the substrate. 2 . The method for forming a semiconductor device according to claim 1 , wherein the effective work function of the metal atoms in the second metal layer is smaller than the effective work function of the metal atoms in the first metal layer. 3 . 3 . The method for forming a semiconductor device according to claim 1 , wherein the metal atoms of the second metal layer include Al, Pt, Pd or rare earth metals, wherein the rare earth metals are Yb or Er. 4 . The method for forming a semiconductor device according to claim 3 , wherein when the metal atoms of the second metal layer include Al, the material of the second metal layer is Al, TiAl or TaAl. 5. The method for forming a semiconductor device according to claim 4, wherein the material of the second metal contact layer is NiAlSi. 6 . The method for forming a semiconductor device according to claim 1 , wherein the second metal layer is formed by atomic layer deposition, chemical vapor deposition or physical vapor deposition. 7. The method for forming a semiconductor device according to claim 1, wherein the second metal layer has a thickness of 5 angstroms to 20 angstroms. 8 . The method for forming a semiconductor device according to claim 1 , wherein the second annealing treatment is immersion annealing, spike annealing, millisecond annealing or laser annealing. 9. The method for forming a semiconductor device according to claim 8, wherein the process parameters of the immersion annealing are: the annealing temperature is 200°C to 600°C, and the annealing time is 5 seconds to 120 seconds; the peak The process parameters of annealing are: the annealing temperature is 300°C to 800°C; the process parameters of the millisecond annealing or laser annealing are: the annealing temperature is 500°C to 900°C, and the annealing time is 0.1 millisecond to 1 second. 10. The method for forming a semiconductor device according to claim 1, further comprising the step of: performing a pre-cleaning treatment on the surface of the first metal contact layer before forming the second metal layer, the process of the pre-cleaning treatment for wet etching or plasma cleaning. 11. The method for forming a semiconductor device according to claim 1, wherein the material of the first metal layer is a single metal or an alloy of Ni, W, Ti, Ta, Pt, Co. 12 . The method for forming a semiconductor device according to claim 1 , wherein the first annealing treatment is one-step annealing treatment or multi-step annealing treatment. 13 . 13. The method for forming a semiconductor device according to claim 12, wherein the multi-step annealing treatment comprises a first-step annealing treatment and a second-step annealing treatment. 14. The method for forming a semiconductor device according to claim 13, wherein the first annealing treatment is immersion annealing, the annealing temperature is 250°C to 350°C, and the annealing time is 20 seconds to 90 seconds; or The first annealing treatment is millisecond annealing, the annealing temperature is 650-950 degrees, and the annealing time is 0.25 milliseconds to 20 milliseconds. 15. The method for forming a semiconductor device according to claim 13, wherein the second annealing treatment is immersion annealing, the annealing temperature is 350°C to 500°C, and the annealing time is 20 seconds to 90 seconds; or The second annealing treatment is spike annealing, and the annealing temperature is 350°C to 550°C. 16 . The method for forming a semiconductor device according to claim 1 , further comprising a step of forming a protective layer on the surface of the first metal layer before performing the first annealing treatment after forming the first metal layer. 17. The method for forming a semiconductor device according to claim 16, wherein the protective layer is made of Ti, Ta, TiN or TaN. 18. The method for forming a semiconductor device according to claim 16, wherein after forming the first metal contact layer, the protection layer is removed. 19. The method for forming a semiconductor device according to claim 1, further comprising the steps of: forming grooves in the substrate on both sides of the gate structure before forming the doped region; using a selective epitaxial process to form A stress layer that fills the groove. 20. The method for forming a semiconductor device according to claim 1, wherein the formed semiconductor device is an NMOS transistor, a PMOS transistor or a CMOS transistor.