CN104796201A - Digital optical transceiver based on secondary multiplexing and demultiplexing - Google Patents

Abstract

The invention discloses a digital optical transceiver based on secondary multiplexing, which includes a transmitting end and a receiving end connected through an optical fiber. It includes a branching processing module, a serial-parallel processing module and an optical receiving module, and the multiplexing processing module and the branching processing module are connected with a video interface, an audio interface, a data interface and a network interface. The present invention uses online system programmable technology and field programmable logic array FPGA to perform secondary multiplexing, specifically a synchronous secondary multiplexing mode by byte, and realizes reliable transmission of video, audio, data, and network signals , improving channel utilization and saving fiber resources.

Description

Digital Optical Transceiver Based on Double Multiplexing

technical field

The invention relates to a digital optical transceiver, in particular to a digital optical transceiver based on double multiplexing.

Background technique

At present, a large amount of information is transmitted through optical fibers. With the increase of the types of transmitted information, traditional transmission equipment that can only transmit a single information, such as equipment that only transmits video or transmits the network, each monopolizes optical fibers, resulting in a waste of optical fiber resources. . The multiple access technology uses time division multiplexing technology to combine and separate different data, which is beneficial to the transmission of various information. The application of programmable logic device (FPGA) makes the realization of multiple tap technology easy. FPGA is highly integrated and suitable for high-speed, high-density digital logic circuit design.

The multiplexing method used by the current optical transceivers is not flexible enough, and the data of different rates cannot be multiplexed for transmission after processing, resulting in low channel utilization.

Contents of the invention

The purpose of the present invention is to provide a digital optical transceiver based on secondary multiplexing, which can flexibly process data of different rates and multiplex them together for transmission, thereby improving channel utilization.

In order to achieve the above-mentioned technical purpose and achieve the above-mentioned technical effect, the present invention is realized through the following technical solutions:

A digital optical transceiver based on secondary multiplexing, including a transmitting end and a receiving end connected by an optical fiber, the transmitting end includes a multiplexing processing module, a parallel-serial processing module and an optical transmission module, and the receiving end includes a branching processing module module, a serial-parallel processing module and an optical receiving module, and the multiplexing processing module and the branching processing module are connected with a video interface, an audio interface, a data interface and a network interface.

Further, the parallel-serial processing module uses an LV1023 chip.

Further, the serial-parallel processing module uses an LV1224 chip.

Further, the video interface of the transmitting end uses an AD9280 chip, and the video interface of the receiving end uses an AD9708 chip.

Further, the audio interface of the transmitting end uses a CS5340 chip, and the audio interface of the receiving end uses a CS4344 chip.

Further, the data interfaces of the transmitting end and the receiving end both use a MAX232 chip for converting data interface levels and TTL levels.

Further, the network interfaces of the transmitting end and the receiving end are used to convert 100Mbit/s Ethernet data into 5-bit rate of 25Mbit/s data or convert 5-bit rate of 25Mbit/s data into 100Mbit/s KSZ8995 chip for Ethernet data.

The method of digital multiplexing is divided into bit-based multiplexing, word-based multiplexing and frame-based multiplexing according to the interleaving length of each branch signal. The bit-based multiplexing method requires simple equipment, small storage capacity, and is easy to implement. It is required that the code rate and phase of each branch are the same. When multiplexing by frame, the original structure of each frame is not destroyed, which is beneficial to exchange, but a large-capacity buffer memory is required. The present invention combines the above two multiplexing methods and adopts the word-based synchronous multiplexing mode, which is flexible and does not require a large-capacity buffer memory. A code word is composed of a byte, that is, an 8-bit code.

The digital multiplexing method is divided into synchronous multiplexing, asynchronous multiplexing and quasi-synchronous multiplexing from the perspective of the relationship between the signal clocks of each branch in the multiplexing. There is a synchronous relationship, which is called asynchronous multiplexing. For asynchronous multiplexing, asynchronous data synchronization is generally performed through asynchronous FIFO, etc. If it is not handled properly, it is easy to enter a metastable state. Compared with the synchronous multiplexing technology, quasi-synchronous multiplexing adds the link of code rate adjustment and code rate recovery. The present invention adopts the method of synchronous multiplexing. Compared with the above two methods, it is not easy to enter the metastable state, and there is no link of code speed processing, so the system is more stable and reliable.

The beneficial effects of the present invention are:

The present invention uses online system programmable technology and field programmable logic array FPGA to perform secondary multiplexing, specifically a synchronous secondary multiplexing mode by byte, which realizes reliable transmission of video, audio, data, and network signals , improving channel utilization and saving fiber resources.

Description of drawings

The accompanying drawings described here are used to provide a further understanding of the present invention and constitute a part of the application. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations to the present invention. In the attached picture:

Fig. 1 is a structural representation of the present invention;

Fig. 2 is the schematic diagram of the principle of secondary multiple tap of the present invention;

Explanation of symbols in the figure: 1-transmitter, 11-multiplex processing module, 12-parallel serial processing module, 13-optical transmission module, 14-video interface of the transmitter, 15-audio interface of the transmitter, 16-data interface of the transmitter , 17-network interface of the transmitting end, 2-receiving end, 21-split processing module, 22-serial parallel processing module, 23-optical receiving module, 24-video interface of the receiving end, 25-audio interface of the receiving end, 26-receiving The data interface at the end, 27-the network interface at the receiving end, 3-optical fiber,

Network x.y- the yth data of the xth network data after serial-to-parallel conversion,

Video x.y- The y-th bit data of the x-th video after eight-bit digital quantization.

Detailed ways

The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

As shown in Figure 1, a digital optical transceiver based on double multiplexing includes a transmitting end 1 and a receiving end 2 connected by an optical fiber 3, and the transmitting end 1 includes a multiplex processing module 11 and a parallel-serial processing module 12 And the light-emitting module 13, the receiving end 2 includes a branching processing module 21, a serial-parallel processing module 22 and an optical receiving module 23, and the multiplexing processing module 11 and the branching processing module 21 are all connected with video interfaces 14, 24, Audio interface 15,25, data interface 16,26 and network interface 17,27.

Further, the parallel-serial processing module 12 uses an LV1023 chip.

Further, the serial-parallel processing module 22 uses an LV1224 chip.

Further, the video interface 14 of the transmitting end uses an AD9280 chip, and the video interface 24 of the receiving end uses an AD9708 chip.

Further, the audio interface 15 of the transmitting end uses a CS5340 chip, and the audio interface 25 of the receiving end uses a CS4344 chip.

Further, the data interfaces 16 and 26 of the transmitting end and the receiving end both use a MAX232 chip for converting data interface levels and TTL levels.

Further, the network interfaces 17 and 27 of the transmitting end and the receiving end are all used to convert 100Mbit/s Ethernet data into 5-bit rate of 25Mbit/s data or convert 5-bit rate of 25Mbit/s data into KSZ8995 chip for 100Mbit/s Ethernet data.

The working principle of this embodiment is:

The synchronous multiplexing method of word-by-word multiplexing is adopted. This method is flexible and does not require a large-capacity buffer memory. One codeword is composed of one byte, that is, an 8-bit code, and it is not easy to enter a metastable state, and there is no code speed processing. link, the system is more stable and reliable. The present invention transmits 2 channels of video, 2 channels of stereo audio, 8 channels of data and 1 channel of Ethernet data in a single-mode single optical fiber, specifically as shown in Figure 2, including:

(1) Processing of network data: Use the shift register inside the FPGA to perform serial-to-parallel conversion of the network data, and convert 5 pieces of 25Mbit/s network data into 25 pieces of 5Mbit/s data.

(2) One-time multiplexing: Use the rise of the 15MHz clock to trigger a counter with a modulus of 3. Before one multiplexing, it is 5Mbit/s data, and after multiplexing, it is 15Mbit/s data. The multiplexing is divided into two groups.

(3) Secondary multiplexing: Use the rising edge of the 60MHz clock to trigger a counter with a modulus of 4, and before the secondary multiplexing, it is 15Mbit/s data, and after multiplexing, it is 60Mbit/s data.

(4) Splitting: It is the reverse process of the second multiplexing and the first multiplexing. After the splitting, 25 pieces of 5Mbit/s data are restored to five pieces of 25Mbit/s network data.

Claims (7)

1. A digital optical transceiver based on secondary multiplexing, including a transmitting end (1) and a receiving end (2) connected through an optical fiber (3), characterized in that: the transmitting end (1) includes multiplexing processing module (11), a parallel-serial processing module (12) and an optical transmission module (13), the receiving end (2) includes a tap processing module (21), a serial-parallel processing module (22) and an optical receiving module (23), the The multiplexing processing module (11) and the branching processing module (21) are connected with video interfaces (14, 24), audio interfaces (15, 25), data interfaces (16, 26) and network interfaces (17, 27 ). 2. A digital optical transceiver based on double multiplexing according to claim 1, characterized in that: the parallel-serial processing module (12) uses an LV1023 chip. 3. A digital optical transceiver based on double multiplexing according to claim 1, characterized in that: the serial-parallel processing module (22) uses an LV1224 chip. 4. A digital optical transceiver based on secondary multiplexing according to claim 1, characterized in that: the video interface (14) at the transmitting end uses an AD9280 chip, and the video interface (24) at the receiving end uses an AD9708 chip . 5. A digital optical transceiver based on secondary multiplexing according to claim 1, characterized in that: the audio interface (15) at the transmitting end uses a CS5340 chip, and the audio interface (25) at the receiving end uses a CS4344 chip . 6. A digital optical transceiver based on secondary multiplexing according to claim 1, characterized in that: the data interfaces (16, 26) of the transmitting end and the receiving end are both used to complete the data interface level and TTL electrical level Level conversion MAX232 chip. 7. A digital optical transceiver based on secondary multiplexing according to claim 1, characterized in that: the network interfaces (17, 27) of the transmitting end and the receiving end are both used to transmit 100Mbit/s Ethernet data KSZ8995 chip that converts data with 5-bit rate of 25Mbit/s or converts data with 5-bit rate of 25Mbit/s into 100Mbit/s Ethernet data.