CN104733433A - Structure and method achieving partial interconnection - Google Patents
Structure and method achieving partial interconnection Download PDFInfo
- Publication number
- CN104733433A CN104733433A CN201510131865.6A CN201510131865A CN104733433A CN 104733433 A CN104733433 A CN 104733433A CN 201510131865 A CN201510131865 A CN 201510131865A CN 104733433 A CN104733433 A CN 104733433A
- Authority
- CN
- China
- Prior art keywords
- control gate
- connecting line
- local interlinkage
- electrically connected
- separator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 30
- 238000002955 isolation Methods 0.000 claims abstract description 25
- 229910052710 silicon Inorganic materials 0.000 claims description 18
- 239000010703 silicon Substances 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 8
- 239000004020 conductor Substances 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 11
- 239000004065 semiconductor Substances 0.000 abstract description 7
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 230000003068 static effect Effects 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000007667 floating Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 239000008280 blood Substances 0.000 description 2
- 210000004369 blood Anatomy 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000015654 memory Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention relates to a semiconductor device structure and the technical field of semiconductor device manufacturing, in particular to a structure and method achieving partial interconnection by using control grids. In a Flash structure, the control grids are arranged on a shallow channel isolation structure, the control grids are used for partial interconnection among devices, the used layer number of the devices can be reduced through partial interconnection wires, the area of the devices can be decreased, and device crosstalk cannot be caused.
Description
Technical field
The present invention relates to semiconductor device structure and manufacturing technology field thereof, particularly relate to a kind of utilize control gate to realize local interlinkage structure and method.
Background technology
Modern electronic circuit is coupled together by specific electric path by the device be separated one by one, therefore must semiconductor device can be kept apart in integrated circuit fabrication, these devices are also wanted can interconnect to form required specific circuit structure subsequently.Interconnection line between current semiconductor device is generally metal etc., along with the development of integrated circuit, the scale of integrated circuit is increasing, that is increasing device needs to interconnect, therefore need increasing level in the fabrication of integrated circuits to realize interconnection, the area of integrated circuit will be made so increasing.
Therefore how to find a kind of structure and the method that realize local interlinkage, to reduce the level used by each several part connection, and then the area reducing circuit becomes the direction that those skilled in the art are devoted to research.
Summary of the invention
For above-mentioned Problems existing, the invention discloses a kind of structure realizing local interlinkage, comprising:
Substrate, has fleet plough groove isolation structure and active area;
Separator, is positioned at the upper surface of described fleet plough groove isolation structure, and is not formed with described active area and contact;
Control gate, is positioned at the upper surface of described separator, and by described separator and described fleet plough groove isolation structure mutually isolated;
Connecting line, is electrically connected to be drawn by described control gate with described control gate, and then realizes local interlinkage.
The above-mentioned structure realizing local interlinkage, wherein, described connecting line embeds the both sides being arranged at described control gate top or being positioned at described control gate.
The above-mentioned structure realizing local interlinkage, wherein, described structure also comprises:
Interconnection layer, is electrically connected to be drawn by described control gate with described connecting line, and then realizes local interlinkage.
The above-mentioned structure realizing local interlinkage, wherein, described interconnection layer is metal or polysilicon gate.
The above-mentioned structure realizing local interlinkage, wherein, described separator is the sandwich structure that the oxide of the nitride-silicon of the oxide-silicon of silicon is formed.
The invention also discloses a kind of method realizing local interlinkage, wherein, comprise the steps:
The substrate that one has fleet plough groove isolation structure and an active area is provided;
After the top of described fleet plough groove isolation structure forms separator, prepare the upper surface that a control gate covers described separator;
Continue to form the connecting line be electrically connected with described control gate, by described connecting line, described control gate is drawn to realize local interlinkage.
The above-mentioned method realizing local interlinkage, wherein, forms the connecting line be electrically connected with described control gate, is specially:
Adopt CMOS contact hole technique, control gate described in partial etching forms contact hole;
In described contact hole, filled conductive material forms described connecting line.
The above-mentioned method realizing local interlinkage, wherein, forms the connecting line be electrically connected with described control gate, is specially:
Adopt CMOS contact hole technique, form described connecting line respectively in described control gate both sides.
The above-mentioned method realizing local interlinkage, wherein, described method also comprises:
After forming the described connecting line be electrically connected with described control gate, continue to form the interconnection layer be electrically connected with described connecting line.
The above-mentioned method realizing local interlinkage, wherein, described separator is the sandwich structure that the oxide of the nitride-silicon of the oxide-silicon of silicon is formed.
A kind of structure and method realizing local interlinkage disclosed by the invention, by control gate in Flash structure is arranged on the top of isolation structure of shallow trench, the control gate in this Flash structure is utilized to do local interlinkage between device, device level used can be reduced by the interconnection line of these local, thus reduce the area of device, and device crosstalk can not be caused.
Concrete accompanying drawing explanation
By reading the detailed description done non-limiting example with reference to the following drawings, the present invention and feature, profile and advantage will become more apparent.Mark identical in whole accompanying drawing indicates identical part.Proportionally can not draw accompanying drawing, focus on purport of the present invention is shown.
Fig. 1 is the basic cell structure schematic diagram of conventional 1-T Flash;
Fig. 2 is the basic cell structure schematic diagram of conventional Flash;
Fig. 3 is the basic cell structure schematic diagram of the Flash realizing local interlinkage in the embodiment of the present invention;
Fig. 4 is the structural representation utilizing control gate to realize local interlinkage in one embodiment of the invention;
Fig. 5 is the structural representation utilizing control gate to realize local interlinkage in another embodiment of the present invention;
Fig. 6 is the circuit diagram of 6 pipe SRAM in the embodiment of the present invention;
Fig. 7 is the domain carrying out the 6 pipe SRAM interconnected with metal;
Fig. 8 is the domain carrying out the 6 pipe SRAM interconnected with control gate;
Wherein, 1 is substrate; 2 is control gates; 3 is floating booms; 4 is oxide layers; 5 is logic gates; 6 is fleet plough groove isolation structures; 7 is separators; 8 (10) is connecting line; 9 is interconnection layers; 11 is metal interconnecting wires; 12 is the first metal; 13 is the second metal; 14 is grid; 15 is active area; 16 is control gate interconnection line.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment, the present invention is further illustrated, but not as limiting to the invention.
As shown in Figure 1, being positioned at the floating boom 3 above oxide layer 4 due to the restriction of isolation structure of shallow trench 6 can not move, and in current Flash manufacture craft, control gate 2 is same level with the grid of peripheral logical circuit.The novel Flash structure that American SS T company proposes as shown in Figure 2, control gate 2, floating boom 3 and logic gate 5 are respectively different polysilicon levels, and the manufacture craft of control gate 2 will before the manufacture craft of logic gate 5, control gate 2 can not be separately existed in outside storage array in such an embodiment.
Based on Flash structure in above-mentioned Fig. 1 and Fig. 2, the invention discloses a kind of structure and the method that realize local interlinkage, utilize the control gate in Flash structure as the interconnection of local, thus control gate can be allowed independently to be present in circuit, for the interconnection of local, when control gate does local interconnection line, can not above active area, if because control gate is above active area, and control gate and the too near words of active area distance, control gate and active area will form metal-oxide-semiconductor, such control gate does not only have the effect of local interlinkage, also can destroy original circuit structure, therefore here using control gate as local interlinkage line time, the position of control gate will be positioned at above shallow trench isolation layer.
As in Figure 3-5, the present embodiment relates to a kind of structure realizing local interlinkage, this structure can based on Flash structure, concrete, this structure comprises: the substrate 1 with fleet plough groove isolation structure 6 and active area, and be positioned at the separator 7 of fleet plough groove isolation structure 6 upper surface, and this separator 7 is not formed with active area and contacts; And being positioned at the control gate 2 of separator upper surface, this control gate 2 is mutually isolated by separator 7 and fleet plough groove isolation structure 6; This structure also comprises connecting line 8 (connecting line 10 in corresponding diagram 5), and connecting line 8 (10) is electrically connected to be drawn by control gate 2 with control gate 2, and then realizes local interlinkage.
In the present invention's preferred embodiment, connecting line 8 embeds and is arranged at control gate 2 top, and the upper surface flush of the upper surface of connecting line 8 and control gate 2, structure as shown in Figure 4.
In the present invention's preferred embodiment, connecting line 10 is positioned at the both sides of control gate 2, and is all formed with the both sides of control gate 2 and contact, structure as shown in Figure 5.
In the present invention's preferred embodiment, the above-mentioned structure realizing local interlinkage also comprises: be electrically connected to be drawn by control gate 2 with connecting line 8 (10), and then realize the interconnection layer 9 (this interconnection layer 9 is not in shown in Fig. 5) of local interlinkage, structure as shown in Figure 4.
On this basis, further, above-mentioned interconnection layer 9 is metal or polysilicon gate.
In the present invention's preferred embodiment, the material of control gate 2 is polysilicon.
In the present invention's preferred embodiment, separator 7 is the ONO sandwich structure that the oxide of the nitride-silicon of the oxide-silicon of silicon is formed.
In addition, as in Figure 3-5, the present embodiment also discloses a kind of method realizing local interlinkage, specifically comprises the steps:
Step S1, provides the substrate 1 that has fleet plough groove isolation structure 6 and an active area, utilizes fleet plough groove isolation structure 6 to be isolated active area.The technique forming the substrate 1 that this has fleet plough groove isolation structure 6 and active area is well known to those skilled in the art, and at this, just it will not go into details.
Step S2, after the top of fleet plough groove isolation structure 6 forms separator 7, prepares the upper surface that a control gate 2 covers separator 7, forms structure as shown in Figure 3.
In the present invention's preferred embodiment, separator 7 is the ONO sandwich structure that the oxide of the nitride-silicon of the oxide-silicon of silicon is formed.
In the present invention's preferred embodiment, the material of control gate 2 is polysilicon.
Concrete, first, deposit the first silicon oxide layer, silicon nitride layer, the second silicon nitride layer and polysilicon layer successively in the top of fleet plough groove isolation structure 6; Secondly, remove unnecessary polysilicon layer, the second silicon oxide layer, silicon nitride layer and the first silicon nitride layer successively, remaining second silicon oxide layer, silicon nitride layer and the first silicon nitride layer form the separator 7 only covering fleet plough groove isolation structure 6 upper surface, and remaining polysilicon layer forms above-mentioned control gate 2.
Step S3, continues to form the connecting line 8 (10) be electrically connected with control gate 2, is drawn to realize local interlinkage by control gate 2 by connecting line 8 (10).
In the present invention's preferred embodiment, form the connecting line 8 be electrically connected with control gate 2, be specially: first, adopt CMOS contact hole technique (directly can punch on control gate 2), partial etching control gate 2 forms contact hole; Secondly, in contact hole, filled conductive material forms connecting line 8.
In the present invention's preferred embodiment, after forming the connecting line 8 (10) be electrically connected with control gate 2, continue to form the interconnection layer 9 (this interconnection layer 9 is not in shown in Fig. 5) be electrically connected with connecting line 8 (10), this interconnection layer 9 is formed with connecting line 8 (10) and contacts, by this connecting line 8 (10) and interconnection layer 9, control gate 2 is drawn to realize local interlinkage, form structure as shown in Figure 4.
In the present invention's preferred embodiment, the first interconnection layer 9 is the level of interconnection when interconnecting with control gate 2, and this first interconnection layer 9 can be metal or polysilicon gate etc.
In the present invention's preferred embodiment, form the connecting line 8 be electrically connected with control gate 2, be specially: adopt CMOS contact hole technique, form connecting line 10 respectively in control gate 2 both sides, form structure as shown in Figure 5.
In the present invention, no matter be above-mentioned any embodiment, the manufacture craft making local interlinkage of control gate is all before the manufacture craft of logic gate.
Be not difficult to find, the present embodiment is the embodiment of the method corresponding with the above-mentioned embodiment realizing the structure of local interlinkage, and the present embodiment can be worked in coordination with the above-mentioned embodiment realizing the structure of local interlinkage and be implemented.The above-mentioned relevant technical details realizing mentioning in the embodiment of the structure of local interlinkage is still effective in the present embodiment, in order to reduce repetition, repeats no more here.Correspondingly, the relevant technical details mentioned in the present embodiment also can be applicable to above-mentioned realization in the embodiment of the structure of local interlinkage.
Our explanation control gate of giving an example does the application of local interlinkage below.
We illustrate for 6 pipe static random access memorys (SRAM), the circuit diagram of 6 pipe static random access memorys as shown in Figure 6, wherein T1 to T6 is 6 metal-oxide-semiconductors, in the manufacture craft of modern SRAM, interconnection between the grid of T3 and T5 and the active area of T4 and T6 is with metal interconnected, interconnection between the grid of T4 and T6 and the active area of T3 and T5 is also by metal interconnected, and as shown in Figure 7, in figure, 11 is metal interconnecting wires to corresponding domain.
Control gate is utilized to do the domain of 6 pipe static random access memory (SRAM) unit of local interlinkage as shown in Figure 8 in the present invention.Metal interconnecting wires 11 between the grid of T3 and T5 and the active area of T4 and T6 changes and does control gate interconnection line 16 by we, metal interconnecting wires 11 between the grid of T4 and T6 and the active area of T3 and T5 also changes and does control gate interconnection line 16, number of metal used can be reduced like this, reduce the level that device is used, thus effectively reduce the area of device, and replace metal to do interconnection line with control gate, increase Fig. 6 interior joint a, b, c, the electric capacity of d, increase the speed of coupling, signal can be very fast from coupled one end to other one end, node b is coupled to from node a in such as Fig. 6, node c is coupled to from node d, accelerate the reversal rate of device, improve the speed of static random access memory.
In sum, a kind of structure and method realizing local interlinkage disclosed by the invention, by control gate being arranged on the top of isolation structure of shallow trench, in production of integrated circuits, control gate is applied to local interlinkage, thus device level used can be reduced, and then reduce the area of device, and device crosstalk can not be caused.
It should be appreciated by those skilled in the art that those skilled in the art are realizing change case in conjunction with prior art and above-described embodiment, do not repeat at this.Such change case does not affect flesh and blood of the present invention, does not repeat them here.
Above preferred embodiment of the present invention is described.It is to be appreciated that the present invention is not limited to above-mentioned particular implementation, the equipment wherein do not described in detail to the greatest extent and structure are construed as to be implemented with the common mode in this area; Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or being revised as the Equivalent embodiments of equivalent variations, this does not affect flesh and blood of the present invention.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (10)
1. realize a structure for local interlinkage, it is characterized in that, comprising:
Substrate, has fleet plough groove isolation structure and active area;
Separator, is positioned at the upper surface of described fleet plough groove isolation structure, and is not formed with described active area and contact;
Control gate, is positioned at the upper surface of described separator, and by described separator and described fleet plough groove isolation structure mutually isolated;
Connecting line, is electrically connected to be drawn by described control gate with described control gate, and then realizes local interlinkage.
2. realize the structure of local interlinkage as claimed in claim 1, it is characterized in that, described connecting line embeds the both sides being arranged at described control gate top or being positioned at described control gate.
3. realize the structure of local interlinkage as claimed in claim 1, it is characterized in that, described structure also comprises:
Interconnection layer, is electrically connected to be drawn by described control gate with described connecting line, and then realizes local interlinkage.
4. realize the structure of local interlinkage as claimed in claim 3, it is characterized in that, described interconnection layer is metal or polysilicon gate.
5. realize the structure of local interlinkage as claimed in claim 1, it is characterized in that, described separator is the sandwich structure that the oxide of the nitride-silicon of the oxide-silicon of silicon is formed.
6. realize a method for local interlinkage, it is characterized in that, comprise the steps:
The substrate that one has fleet plough groove isolation structure and an active area is provided;
After the top of described fleet plough groove isolation structure forms separator, prepare the upper surface that a control gate covers described separator;
Continue to form the connecting line be electrically connected with described control gate, by described connecting line, described control gate is drawn to realize local interlinkage.
7. realize the method for local interlinkage as claimed in claim 6, it is characterized in that, form the connecting line be electrically connected with described control gate, be specially:
Adopt CMOS contact hole technique, control gate described in partial etching forms contact hole;
In described contact hole, filled conductive material forms described connecting line.
8. realize the method for local interlinkage as claimed in claim 6, it is characterized in that, form the connecting line be electrically connected with described control gate, be specially:
Adopt CMOS contact hole technique, form described connecting line respectively in described control gate both sides.
9. realize the method for local interlinkage as claimed in claim 6, it is characterized in that, described method also comprises:
After forming the described connecting line be electrically connected with described control gate, continue to form the interconnection layer be electrically connected with described connecting line.
10. realize the method for local interlinkage as claimed in claim 6, it is characterized in that, described separator is the sandwich structure that the oxide of the nitride-silicon of the oxide-silicon of silicon is formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510131865.6A CN104733433B (en) | 2015-03-24 | 2015-03-24 | A kind of structure and method for realizing local interlinkage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510131865.6A CN104733433B (en) | 2015-03-24 | 2015-03-24 | A kind of structure and method for realizing local interlinkage |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104733433A true CN104733433A (en) | 2015-06-24 |
| CN104733433B CN104733433B (en) | 2019-06-25 |
Family
ID=53457185
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510131865.6A Active CN104733433B (en) | 2015-03-24 | 2015-03-24 | A kind of structure and method for realizing local interlinkage |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104733433B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020187606A1 (en) * | 2000-06-16 | 2002-12-12 | Drynan John M. | Interconnect line selectively isolated from an underlying contact plug |
| JP2010153735A (en) * | 2008-12-26 | 2010-07-08 | Toshiba Corp | Semiconductor device |
| CN103855098A (en) * | 2012-12-04 | 2014-06-11 | 中芯国际集成电路制造(上海)有限公司 | Method for forming storage unit of flash memory |
| CN103872059A (en) * | 2014-03-24 | 2014-06-18 | 上海华力微电子有限公司 | P-type channel flash memory and manufacturing method thereof |
| CN103887160A (en) * | 2014-03-20 | 2014-06-25 | 上海华力微电子有限公司 | Method for etching control grid |
| CN104425386A (en) * | 2013-08-20 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Flash memory and method for manufacturing same |
-
2015
- 2015-03-24 CN CN201510131865.6A patent/CN104733433B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020187606A1 (en) * | 2000-06-16 | 2002-12-12 | Drynan John M. | Interconnect line selectively isolated from an underlying contact plug |
| JP2010153735A (en) * | 2008-12-26 | 2010-07-08 | Toshiba Corp | Semiconductor device |
| CN103855098A (en) * | 2012-12-04 | 2014-06-11 | 中芯国际集成电路制造(上海)有限公司 | Method for forming storage unit of flash memory |
| CN104425386A (en) * | 2013-08-20 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Flash memory and method for manufacturing same |
| CN103887160A (en) * | 2014-03-20 | 2014-06-25 | 上海华力微电子有限公司 | Method for etching control grid |
| CN103872059A (en) * | 2014-03-24 | 2014-06-18 | 上海华力微电子有限公司 | P-type channel flash memory and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104733433B (en) | 2019-06-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7973314B2 (en) | Semiconductor device and method of manufacturing the same | |
| US10164121B2 (en) | Stacked independently contacted field effect transistor having electrically separated first and second gates | |
| CN102683291B (en) | Manufacture the method for 3D nonvolatile semiconductor memory member | |
| US9496179B2 (en) | Method of manufacturing semiconductor devices | |
| KR102173638B1 (en) | Semiconductor device and method of forming the same | |
| US8704205B2 (en) | Semiconductor structure with improved capacitance of bit line | |
| KR101034914B1 (en) | Flash Memory with Recessed Floating Gate | |
| CN108922889A (en) | Semiconductor devices | |
| US9035389B2 (en) | Layout schemes for cascade MOS transistors | |
| US11201160B2 (en) | Semiconductor memory device including multiple conductive line layers | |
| JP2024001284A (en) | semiconductor equipment | |
| CN106057793A (en) | Semiconductor devices and methods for manufacturing the same | |
| US9559178B2 (en) | Non-volatile memory (NVM) cell and device structure integration | |
| CN103346157A (en) | Split-gate type flash memory structure and manufacturing method thereof | |
| CN104733433A (en) | Structure and method achieving partial interconnection | |
| CN103219288A (en) | Semiconductor device and forming method thereof | |
| KR102148914B1 (en) | Back gate in select transistor for edram | |
| CN103021956A (en) | PIP (poly-insulator-poly) capacitor of split gate type flash memory and manufacturing method of PIP capacitor | |
| CN103021999B (en) | Semiconductor structure and manufacture method thereof | |
| CN101714560A (en) | Eeprom and method for manufacturing the eeprom | |
| JP2009194369A (en) | Semiconductor device | |
| US20180151571A1 (en) | LAYOUT of SEMICONDUCTOR TRANSISTOR DEVICE | |
| CN107170750A (en) | A kind of semiconductor components and devices structure and preparation method thereof | |
| US8089125B2 (en) | Integrated circuit system with triode | |
| CN103633096B (en) | Semiconductor Structures for Improving Bit Line Capacitance |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |