CN104700807A - Data transmission device and method of embedded clock point-to-point transmission architecture - Google Patents

Abstract

The invention provides a data transmission device and a data transmission method for an embedded clock point-to-point transmission framework of a liquid crystal display. The method comprises the following steps: the first time sequence generating unit provides a first clock signal; the first data processor packages data to be transmitted into a series of packets according to a first clock signal; the first data processor encodes each packet to obtain encoded data; the second time sequence generating unit provides a second clock signal; and the second data processor decodes the second clock signal and the coded data according to the second clock signal to obtain the effective data of the packet. Compared with the prior art, the invention provides a method for defining the packet state aiming at the embedded clock point-to-point transmission architecture, and the packet state information of each packet is given by the combination of some special data bits, so that the transmission between the timing controller and the source driver can be flexibly adjusted according to the system state and the requirement.

Description

Data transmission device and method of embedded clock point-to-point transmission architecture

technical field

The present invention relates to a data transmission technology, in particular to a data transmission device and a method thereof for an embedded clock (Clock Embedded) point-to-point (Point to Point) transmission architecture of a liquid crystal display.

Background technique

The timing controller (Timing Controller, Tcon) and the source driver (Source Driver, SD) are two key components of the panel display driver. In simple terms, the main function of the timing controller when transmitting display data is to receive an input signal of a specific format (such as LVDS), where the input signal can be generated by a signal source such as a signal generator, and then passed through a transfer board (transfer board) After conversion, the above-mentioned input signals are properly arranged according to the corresponding number of output channels, encoded (encoded) or scrambled (scrambled), and then output to the source driver. On the side of the source driver, its main function when transmitting display data is to receive the signal output by the timing controller, and analyze the display data and setting data, and write the display data into the register of the source driver itself for reference. The LCD panel is driven when the signal appears. Here, the setting data is mainly used to provide information required by the source driver, such as polarity, number of channels, and so on.

In the prior art, the early transmission interfaces mostly adopt a "multi drop" architecture (that is, a multi-drop architecture), and the timing controller routes the data signal and the clock signal separately and transmits them to the source driver. Because the electromagnetic interference (EMI) of a single signal line is large, it is not conducive to high-speed transmission, so the signal on the transmission mostly uses a differential pair (differential pair), such as a miniature low voltage differential signal (mini Low Voltage Differential Signal, mini -LVDS) interface or low-swing differential signal (Reduced Swing Differential Signal, RSDS) interface. As the resolution requirements of displays are getting higher and higher, there are more and more requirements for data transmission. For example, it is hoped that data can be transmitted faster and wiring is more streamlined. Limited by the impedance matching problem, the multi-point architecture has a great limitation on the transmission rate. In addition, in the high-frequency state, the routing structure in which the clock signal and the data signal are transmitted separately may easily cause clock skew or skew (clock skew), so that the clock signal received by the source driver cannot correctly capture valid data.

In order to increase the signal transmission speed, the current mainstream method is a point-to-point architecture with an embedded clock signal (clock embedded signal). In addition, in order to confirm that the source driver has resolved the clock information sent by the timing controller, a “Lock” signal can also be set to display the current clock status. Its action mode is: when the clock signal is not locked (unlock), the logic opposite to that of the lock (lock) is returned. When using the above-mentioned point-to-point transmission interface to operate, the timing controller first transmits the training code (training code) to the source driver until the internal clock data recovery (Clock Data Recovery, CDR) circuit of the source driver returns the "lock" status , the data transfer can begin. Furthermore, in addition to display data, the transmission signal between the timing controller and the source driver also needs to transmit the register setting value of the source driver (Register Setting). If a transmission protocol is not established, the buffer settings of the source driver can only be transmitted through additional hardware wiring, which will consume a lot of space and cost on the printed circuit board (PCB). Although the display data (Display data) and the setting value (Setting) of the source driver register can be transmitted smoothly by the above method, it lacks flexibility. For example, once the packet number of the buffer setting value of the source driver needs to be changed, or even the transmission state needs to be added or the sequence needs to be changed, the transmission protocol must be redefined.

In view of this, how to design a flexible data transmission protocol based on the embedded clock point-to-point transmission architecture between the timing controller and the source driver, so as to eliminate the above-mentioned defects and deficiencies in the prior art, is an important task for relevant technical personnel in the industry. A problem that needs to be solved urgently.

Contents of the invention

Aiming at the above-mentioned defects in the prior art when the timing controller and the source driver transmit the display data and the buffer setting value of the source driver based on the embedded clock point-to-point transmission architecture, the present invention provides a liquid crystal display The data transmission device and method of the embedded clock point-to-point transmission architecture.

According to one aspect of the present invention, a data transmission method for an embedded clock point-to-point transmission architecture is provided, the embedded clock point-to-point transmission architecture includes a timing controller and at least one source driver, wherein the data transmission method includes The following steps:

The first timing generating unit of the timing controller provides a first clock signal;

The first data processor of the timing controller encapsulates the data to be transmitted into a series of packets according to the received first clock signal;

The first data processor encodes each packet to obtain encoded data, wherein the encoded data is used to flexibly define the packet state of the packet;

The second timing generating unit of the source driver provides a second clock signal; and

The second data processor of the source driver decodes the encoded data according to the received second clock signal and the encoded data so as to obtain the valid data of the packet.

In one embodiment, the packet state of each packet corresponds to a setting field, a display field, a blank field or an end field.

In one of the embodiments, each packet is composed of (N-1) data bits and 1 additional bit, the first data bit is the first flag bit, and the second data bit to (N-2)th The data bits include at least one extended flag bit, and the (N-1)th data bit is a second flag bit, which is determined by a combination of the first flag bit, the extended flag bit, and the second flag bit The package state is the setting field, the display field, the blank field or the end field, wherein N is a natural number greater than 3.

In one of the embodiments, the judgment rule for determining the setting field, the display field, the blank field or the end field is:

When the first flag bit of the Nth packet is not equal to the second flag bit of the (N-1)th packet, the packet status corresponds to the display field;

When the first flag bit of the Nth packet is equal to the second flag bit of the (N-1)th packet and is different from the extended flag bit of the Nth packet, the packet status corresponds to the setting field;

When the first flag bit of the Nth packet is equal to the second flag bit of the (N-1)th packet and the extension flag bit of the Nth packet, the packet state corresponds to a blank field; and

The packet state corresponds to the end field when all data bits in the packet are 1.

In one of the embodiments, the above-mentioned step of encoding each packet by the first data processor to obtain an encoded data further includes: adding 1 additional bit to increase the packet from (N-1) data bits to N data bits, wherein the additional bit is used to record the flipping action of the display field; and determine the packet state to be encoded, and adjust the first flag bit, the second flag bit according to the determined packet state The two flag bits and/or the extended flag bits conform to the state indicator (state indicator) of the corresponding field.

In one of the embodiments, the step of decoding the coded data by the second data processor of the source driver according to the received second clock signal and the coded data further includes: comparing the first Whether the first flag bit, the second flag bit and the extended flag bit match the status indicator; and determine whether to flip the data bits in the packet according to the matching result, so as to take out the valid data of the packet.

In one of the embodiments, when the packet state corresponds to a display field, if the additional bit is not flagged and flipped, the valid data is all data bits in the packet except the additional bit; if If the additional bit has been marked inverted, the valid data is all data bits in the packet after the first flag bit has been inverted except the additional bit.

According to another aspect of the present invention, a data transmission device for an embedded clock point-to-point transmission architecture is provided, including:

The timing controller has: a first timing generation unit, configured to provide a first clock signal; and a first data processor, configured to package the data to be transmitted into a series of and encoding each packet to obtain encoded data, wherein the encoded data is used to flexibly define the packet state of the packet; and

The source driver has: a second timing generation unit for receiving encoded data from the first data processor and providing a second clock signal; signal and the coded data, and decode the coded data to obtain valid data of the packet.

In one of the embodiments, the first data processor sequentially includes a state-defining encoder and a scrambler, and the second data processor sequentially includes a descrambler and a state-defining decoder, wherein the The scrambler is electrically connected with the descrambler.

In one of the embodiments, the first data processor sequentially includes a scrambler and a state-defining encoder, and the second data processor sequentially includes a state-defining decoder and a descrambler, wherein the The state definition encoder is electrically connected to the state definition decoder.

Using the data transmission device and method of the embedded clock point-to-point transmission architecture for liquid crystal displays of the present invention, the first timing generation unit of the timing controller provides a first clock signal, and the first data processor according to the received first clock signal A clock signal encapsulates the data to be transmitted into a series of packets, and the first data processor encodes each packet to obtain encoded data, where the encoded data is used to flexibly define the packet status of the packets. The second timing generating unit of the source driver provides a second clock signal, and the second data processor of the source driver decodes the encoded data according to the received second clock signal and the encoded data to obtain valid data in the package. Compared with the prior art, the present invention proposes a method for defining the state of the packet for the built-in clock point-to-point transmission architecture. The packet state information of each packet is given by the combination of some special data bits, such as display field, setting Packet status such as field, blank field, and end field. In this way, the source driver can compare the data bits in the received packet data with the defined status indicator, and determine whether to flip the data bits in the packet according to the comparison result, so as to take out the valid data of the packet , so that the transmission between the timing controller and the source driver can be flexibly adjusted in response to system status and requirements.

Description of drawings

Readers will have a clearer understanding of various aspects of the present invention after reading the detailed description of the present invention with reference to the accompanying drawings. in,

FIG. 1 shows a schematic diagram of data transmission using a multi-point architecture in the prior art;

FIG. 2 shows a schematic diagram of data transmission using a point-to-point architecture in the prior art;

FIG. 3 shows a schematic diagram of defining the sequence and quantity of packets using the point-to-point architecture of FIG. 2;

4 shows a schematic structural diagram of a data transmission device based on an embedded clock point-to-point transmission architecture and can flexibly define the packet state of a packet according to an embodiment of the present invention;

Fig. 5 a shows a specific embodiment of the first data processor and the second data processor in the data transmission device of Fig. 4;

Fig. 5b shows another specific embodiment of the first data processor and the second data processor in the data transmission device of Fig. 4;

FIG. 6 shows a schematic diagram of the state of frame-by-frame data transmission through the packet form defined by the present invention;

FIG. 7a shows a schematic diagram of packet distribution of a liquid crystal display device during a V-active period;

Figure 7b shows a schematic embodiment of each special flag bit used to flexibly define the packet state of the packet in the present invention;

Figures 8a to 8d show schematic diagrams of setting additional bits for the (N-1)th packet and the Nth packet, respectively;

Figures 9a to 9d respectively show schematic diagrams when the first flag bit, the second flag bit and/or the extended flag bit conform to the state indicator of the corresponding field in the packet state of display data;

Figures 10a to 10f respectively show schematic diagrams when the first flag bit, the second flag bit and/or the extended flag bit do not conform to the state indicator of the corresponding field in the packet state of display data; and

FIG. 11 shows a flow chart of a data transmission method based on an embedded clock point-to-point transmission architecture and can flexibly define a packet state of a packet according to another embodiment of the present invention.

Detailed ways

In order to make the technical content disclosed in this application more detailed and complete, reference may be made to the drawings and the following various specific embodiments of the present invention, and the same symbols in the drawings represent the same or similar components. However, those skilled in the art should understand that the examples provided below are not intended to limit the scope of the present invention. In addition, the drawings are only for schematic illustration and are not drawn according to their original scale.

Figure 1 shows a schematic diagram of data transmission using a multi-point architecture in the prior art, Figure 2 shows a schematic diagram of data transmission in the prior art using a point-to-point architecture, and Figure 3 shows the definition of a point-to-point architecture using Figure 2 Schematic diagram of the sequence and number of packets.

Referring to FIG. 1, as mentioned above, when the "multi drop" architecture (ie, multi-point architecture) is adopted, the timing controller routes the data signal and the clock signal separately and transmits them to each source driver after receiving parallel data. Due to the large electromagnetic interference during the transmission of a single signal line, it is not conducive to high-speed transmission. As the display resolution becomes higher and higher, there are more and more requirements for data transmission. However, due to the impedance matching problem, this architecture has a great limitation on the transmission rate.

Referring to Figure 2 and Figure 3, in order to increase the signal transmission speed, it can be changed to a point-to-point architecture with an embedded clock. After receiving the parallel data, the timing controller embeds the data to be transmitted into the clock signal and transmits it to the corresponding A source driver, and the source driver sets a "Lock" signal to display the current clock state when parsing out the clock information sent by the timing controller. For example, in Figure 3, the "clock training" state is first defined, and the timing controller transmits the clock training code packet to the source driver until the source driver locks the clock signal, then directly enters the "Setting" state, and finally enters the "Display" state. In order to determine whether the content of the currently transmitted packet is the set value or display data of the source driver buffer, the timing controller and the source driver will first determine the number of packets received continuously in the Setting state, as shown in the figure M packets . After the transmission of the timing controller is completed, it will enter the Display state and start to display the data transmission. The number of packets is N packets as shown in the figure. Obviously, although this method can smoothly transmit display data and setting values, it lacks flexibility. Once the packet number of the buffer setting value of the source driver needs to be changed, or even the transmission status needs to be added or the sequence needs to be changed, the transmission protocol must be redefined.

In order to solve the above problems in the prior art, the present invention provides a new data transmission device. FIG. 4 shows a schematic structural diagram of a data transmission device based on an embedded clock point-to-point transmission architecture and can flexibly define the packet state of a packet according to an embodiment of the present invention.

Referring to FIG. 4 , the data transmission device used in the embedded clock point-to-point transmission architecture of the present invention includes a timing controller 10 and at least one source driver 20 .

Specifically, the timing controller 10 has a first timing generating unit and a first data processor 102 . The source driver 20 has a second timing generation unit and a second data processor 202 . The first timing generating unit receives a clock reference signal clk_ref and a latch signal LOCK, and outputs a first clock signal clk_1. The first data processor 102 receives a parallel data Data_P and a first clock signal clk_1, thereby packaging the data to be transmitted into a series of packets, and encoding each packet to obtain an encoded data Data_S, wherein the encoded data Data_S can be Elasticity defines the packet state of the packet.

The second timing generation unit receives the encoded data Data_S from the first data processor 102 and provides a second clock signal clk_2 and a latch signal LOCK. The second data processor 202 is configured to decode the coded data Data_S according to the received second clock signal clk_2 and the coded data Data_S so as to obtain the packaged valid data.

In a specific embodiment, as shown in Figure 7b, each packet is composed of (N-1) data bits and 1 additional bit, the first data bit is the first flag bit sp_1, the second data bit is to The (N-2)th data bit includes at least one extended flag sp_ext, the (N-1)th data bit is a second flag sp_2, by the first flag sp_1, the extended flag sp_ext and the second flag The combination of bits sp_2 determines the packet status as setting field (Setting), display field (Display), blank field (Blank) or end field (EOL), where N is a natural number greater than 3. For example, N equals 9, and each packet includes 8 data bits and 1 overhead bit.

In a specific embodiment, the judgment rule for determining the setting field, display field, blank field or end field is:

When the first flag of the Nth packet is not equal to the second flag of the (N-1)th packet, that is, sp_1 (N) is not equal to sp_2 (N-1), the packet state corresponds to the display field;

When the first flag bit of the Nth packet is equal to the second flag bit of the (N-1)th packet and different from the extended flag bit of the Nth packet, that is, sp_1(N) is equal to sp_2(N-1) and Not equal to sp_ext(N), the packet state corresponds to the setting field;

When the first flag bit of the Nth packet is equal to the second flag bit of the (N-1)th packet and the extension flag bit of the Nth packet, that is, sp_1(N) is equal to sp_2(N-1) and equal to sp_ext (N), the packet status corresponds to a blank field; and

When all data bits in the packet are 1, the packet state corresponds to the end field.

Fig. 5 a shows a specific embodiment of the first data processor and the second data processor in the data transmission device of Fig. 4, and Fig. 5 b shows the first data processor and the second data processor in the data transmission device of Fig. 4 Another specific embodiment of a processor.

With reference to Fig. 5 a, in this embodiment, the first data processor 102 comprises a state definition coder and a scrambler successively, and the second data processor 202 comprises a descrambler and a state definition decoder successively, and the scrambler The device is electrically connected with the descrambler.

With reference to Fig. 5 b, in this embodiment, the first data processor 102 comprises a scrambler and a state definition encoder successively, and the second data processor 202 comprises a state definition decoder and a descrambler successively, the state definition The encoder is electrically connected to the state definition decoder. It can be seen from Fig. 5a and Fig. 5b that the scrambler is a unit that scrambles data to provide better balance and avoid high EMI problems caused by repetitive data patterns.

FIG. 6 is a schematic diagram showing the state of frame-by-frame data transmission through the packet format defined by the present invention.

Referring to Fig. 6, it describes the state of the data transmission device after power-on (power on). Initial is a period before the system enters the first V-active (that is, V-active(1)). During the Initial period, the timing controller starts to transmit the clock training code packet to the source driver after it is powered on, and the Initial period ends and enters the first A V-active period. The states transmitted in V-active are source driver setting value (Setting), display data (Display), clock correction interval (Blank) and line end period (End of Line, EOL). In the V-blank interval, the state combination of each scanning line can be defined as the source driver setting value (Setting), the clock correction interval (Blank) and the end of line period (End of Line, EOL). In addition, during clock training, two situations can occur: 1) the Lock signal is low, indicating that the clock signal is not locked, and the timing controller immediately transmits the training code; 2) the Lock signal is high, and the timing controller is in "Setting" Set the value of the register in the cycle and inform the source driver to start clock training in the next scan line.

FIG. 7a shows a schematic diagram of the packet distribution of the liquid crystal display device during the V-active period, and FIG. 7b shows a schematic embodiment of each special flag used to flexibly define the packet state of the packet according to the present invention.

Referring to FIG. 7a and FIG. 7b, the status distribution of the display in the V-active interval is described. Taking the Nth scanning line as an example, each line can be divided into H-active and H-blank intervals, in which the setting value (Setting) and display data (Display) of the transmission source driver can be defined in the H-active interval. The H-blank interval is the start time position of the source driver writing the analog signal to the panel and the interval for clock correction. Each can define the end field to indicate the end of the packet, and then start to transmit the data transmission of the next one.

In FIG. 7b, each packet has an overhead bit, and multiple data bits are defined as special bits (specific bits, which may be referred to as "sp" for short). For example, the original packet is (N-1)bit, and after adding an additional bit, it becomes N bit. In addition, bit1, bit2 and bit(N-1) are respectively defined as the first flag sp_1, the extended flag sp_ext and the second flag sp_2.

8a to 8d respectively show schematic diagrams of setting additional bits for the (N-1)th packet and the Nth packet.

In FIG. 8a, the (N-1)th packet includes 8 data bits, and an additional bit (overhead bit) is added to the input packet, and the packet becomes 9 data bits, as shown in FIG. 8b. Here, the function of the additional bit is to record the action of “reversing the packet” in the display data state. When the additional bit is 1, some bits in the packet will be flipped, including sp_1. Similarly, in Figure 8c, the (N)th packet includes 8 data bits, adding 1 overhead bit to the input packet, the packet becomes 9 data bits, as shown in Figure 8d.

FIGS. 9a to 9d respectively show schematic diagrams when the first flag bit, the second flag bit and/or the extended flag bit conform to the state indicator of the corresponding field in the packet state of displaying data.

Referring to Figures 9a to 9d, if the state of the packet is display data, and the data bit of the packet completely matches the state indicator (state indicator) of the display data, that is, sp_1(N) is 1, and sp_2(N-1) is 0, sp_1(N) is not equal to sp_2(N-1); or, sp_1(N-1) is 0, sp_2(N-2) is 1, sp_1(N-1) is not equal to sp_2(N-2) , so there is no need to flip any data bit of the packet. At this time, set the overhead bit (N) and (N-1) to 0. On the contrary, in the process of data decoding (Decoding), for this combination, there is no need to flip the packet data, and the valid data is 8 bits other than the overhead bit.

FIGS. 10a to 10f respectively show schematic diagrams when the first flag bit, the second flag bit and/or the extended flag bit do not match the state indicator of the corresponding field in the packet state of displaying data.

Referring to Figures 10a to 10f, if the state of the packet is display data, and the data bits of the packet do not conform to the state indicator (state indicator) of the display data, that is, sp_1(N) is 0, and sp_2(N-1) is 0, sp_1(N) is equal to sp_2(N-1), so the packet needs to be reversed. At this time, the additional bit overhead bit (N) and (N-1) should be set to "1" first to mark that the packet has been flipped. Then flip over the packet (N), which must contain the first flag sp_1 (N). This embodiment only takes

The overhead bit mark flips sp_1(N), and after flipping, it is found that after the reversal, it conforms to the packet state definition of the displayed data. For example, sp_1(N) changes from "0" in Figure 10e to "1" in Figure 10f. On the contrary, in the process of data decoding (Decoding), because the overhead bit has marked the reverse state, after confirming that the current packet is in the display state according to the combination of specific bits and the description of the state indicator, the corresponding data reflection can be carried out change. The valid data is 8 bits other than the overhead bit. Referring to FIG. 10a to FIG. 10f, since only sp_1(N) is reversed during data encoding (Encoding), it is only necessary to reverse sp_1(N) during restoration.

FIG. 11 shows a flow chart of a data transmission method based on an embedded clock point-to-point transmission architecture and can flexibly define a packet state of a packet according to another embodiment of the present invention.

11, in conjunction with FIG. 4, in the data transmission method, first execute step S11, the first timing generation unit of the timing controller 10 provides a first clock signal clk_1; then execute step S13, the first timing controller 10 A data processor 102 encapsulates the data to be transmitted into a series of packets according to the received first clock signal clk_1; then in step S15, the first data processor 102 encodes each packet to obtain an encoded data Data_S, wherein the encoded data is used to flexibly define the packet state of the packet; then step S17 is executed, and the second timing generation unit of the source driver 20 provides a second clock signal clk_2; finally in step S19, the second data processing of the source driver 20 The device 202 decodes the coded data according to the received second clock signal clk_2 and the coded data Data_S to obtain the packaged valid data.

In a specific embodiment, the above-mentioned step of encoding each packet by the above-mentioned first data processor to obtain an encoded data further includes: adding 1 additional bit to increase the packet from (N-1) data bits to N data bits, wherein the additional bit is used to record the flipping action of the display field; and determine the packet state to be encoded, and adjust the first flag bit, the second flag bit according to the determined packet state The flag bits and/or the extended flag bits are made to conform to the status indicators of the corresponding fields.

In a specific embodiment, the step of decoding the coded data by the second data processor of the source driver according to the received second clock signal and the coded data further includes: comparing the first Whether the flag bit, the second flag bit and the extension flag bit match the status indicator; and determine whether to flip the data bit in the packet according to the matching result, so as to take out the valid data of the packet.

Using the data transmission device and method of the embedded clock point-to-point transmission architecture for liquid crystal displays of the present invention, the first timing generation unit of the timing controller provides a first clock signal, and the first data processor according to the received first clock signal A clock signal encapsulates the data to be transmitted into a series of packets, and the first data processor encodes each packet to obtain encoded data, where the encoded data is used to flexibly define the packet status of the packets. The second timing generating unit of the source driver provides a second clock signal, and the second data processor of the source driver decodes the encoded data according to the received second clock signal and the encoded data to obtain valid data in the package. Compared with the prior art, the present invention proposes a method for defining the state of the packet for the built-in clock point-to-point transmission architecture. The packet state information of each packet is given by the combination of some special data bits, such as display field, setting Packet status such as field, blank field, and end field. In this way, the source driver can compare the data bits in the received packet data with the defined status indicator, and determine whether to flip the data bits in the packet according to the comparison result, so as to take out the valid data of the packet , so that the transmission between the timing controller and the source driver can be flexibly adjusted in response to system status and requirements.

Hereinbefore, specific embodiments of the present invention have been described with reference to the accompanying drawings. However, those skilled in the art can understand that without departing from the spirit and scope of the present invention, various changes and substitutions can be made to the specific embodiments of the present invention. These changes and substitutions all fall within the scope defined by the claims of the present invention.

Claims (10)

1. A data transmission method for an embedded clock point-to-point transmission architecture, the embedded clock point-to-point transmission architecture comprising a timing controller and at least one source driver, the data transmission method comprising the steps of:

a first time sequence generating unit of the time sequence controller provides a first clock signal;

a first data processor of the time schedule controller packages data to be transmitted into a series of packets according to the received first clock signal;

the first data processor encodes each packet to obtain encoded data, wherein the encoded data is used for flexibly defining the packet state of the packet;

the second time sequence generating unit of the source driver provides a second clock signal; and

and the second data processor of the source driver decodes the coded data according to the received second clock signal and the coded data so as to obtain the effective data of the packet.

2. The data transmission method of claim 1, wherein the packet status of each packet corresponds to a set field, a display field, a blank field, or an end field.

3. The data transmission method according to claim 2, wherein each packet is composed of (N-1) data bits and 1 additional bit, the 1 st data bit is a first flag bit, the 2 nd to (N-2) th data bits include at least one extended flag bit, the (N-1) th data bit is a second flag bit, and the packet status is determined as the set field, the display field, the blank field, or the end field by a combination of the first flag bit, the extended flag bit, and the second flag bit, where N is a natural number greater than 3.

4. The data transmission method according to claim 3, wherein the determination rule for determining the setting field, the display field, the blank field or the end field is:

when the first flag bit of the Nth packet is not equal to the second flag bit of the (N-1) th packet, the packet state corresponds to a display field;

when a first flag bit of an Nth packet is equal to a second flag bit of an (N-1) th packet and is different from an extended flag bit of the Nth packet, the packet status corresponds to a set field;

when the first flag bit of the Nth packet is equal to the second flag bit of the (N-1) th packet and the extended flag bit of the Nth packet, the packet status corresponds to a blank field; and

the packet status corresponds to the end field when all data bits in the packet are 1.

5. The data transmission method of claim 4, wherein the step of the first data processor encoding each packet to obtain an encoded data further comprises:

adding 1 additional bit to increase the packet from (N-1) data bits to N data bits, wherein the additional bit is used for recording the flipping action of the display field; and

and determining the packet state to be coded, and adjusting the first zone bit, the second zone bit and/or the extended zone bit according to the determined packet state to enable the first zone bit, the second zone bit and/or the extended zone bit to accord with the state indicator of the corresponding field.

6. The data transmission method of claim 1, wherein the step of decoding the encoded data by the second data processor of the source driver according to the received second clock signal and the encoded data further comprises:

comparing whether the first zone bit, the second zone bit and the expansion zone bit in the packet are matched with the state indicator or not; and

and determining whether to flip the data bits in the packet according to the matching result so as to take out the valid data of the packet.

7. The data transmission method according to claim 6, wherein when the packet status corresponds to a display field,

if the additional bit is not marked to be turned over, the valid data is all data bits except the additional bit in the packet;

and if the additional bit is marked to be inverted, the effective data are all data bits, except the additional bit, of the packet, of which the first flag bit is inverted.

8. A data transmission apparatus for an embedded clock point-to-point transmission architecture, the data transmission apparatus comprising:

a timing controller having: a first timing generation unit for providing a first clock signal; the first data processor is used for packaging data to be transmitted into a series of packets according to the received first clock signal and coding each packet to obtain coded data, wherein the coded data is used for flexibly defining the packet state of the packet; and

a source driver having: a second timing generation unit for receiving the encoded data from the first data processor and providing a second clock signal; and the second data processor is used for decoding the coded data according to the received second clock signal and the coded data so as to obtain the effective data of the packet.

9. The data transmission apparatus of claim 8, wherein the first data processor comprises a state-defined coder and a scrambler, and the second data processor comprises a descrambler and a state-defined decoder, wherein the scrambler is electrically connected to the descrambler.

10. The data transmission apparatus of claim 8, wherein the first data processor comprises a scrambler and a state definition encoder in sequence, and the second data processor comprises a state definition decoder and a descrambler in sequence, wherein the state definition encoder is electrically connected to the state definition decoder.