CN104636521A - Smart card chip security authentication method based on VMM and authentication environment platform - Google Patents
Smart card chip security authentication method based on VMM and authentication environment platform Download PDFInfo
- Publication number
- CN104636521A CN104636521A CN201310563775.5A CN201310563775A CN104636521A CN 104636521 A CN104636521 A CN 104636521A CN 201310563775 A CN201310563775 A CN 201310563775A CN 104636521 A CN104636521 A CN 104636521A
- Authority
- CN
- China
- Prior art keywords
- safety check
- register
- model
- verification
- card chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 32
- 238000012360 testing method Methods 0.000 claims abstract description 55
- 238000012795 verification Methods 0.000 claims description 51
- 230000006870 function Effects 0.000 claims description 32
- 238000007689 inspection Methods 0.000 claims description 12
- 238000013461 design Methods 0.000 claims description 11
- 230000007613 environmental effect Effects 0.000 claims description 9
- 238000005086 pumping Methods 0.000 claims description 7
- 230000009471 action Effects 0.000 claims description 5
- 230000011664 signaling Effects 0.000 claims description 5
- 238000013507 mapping Methods 0.000 claims description 3
- 230000004044 response Effects 0.000 claims description 3
- 238000010276 construction Methods 0.000 claims description 2
- 238000005070 sampling Methods 0.000 claims description 2
- 239000013598 vector Substances 0.000 abstract 1
- 230000005284 excitation Effects 0.000 description 7
- 230000008569 process Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000000875 corresponding effect Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 238000001558 permutation test Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
Landscapes
- Storage Device Security (AREA)
Abstract
The invention discloses a smart card chip security function authentication method based on a VMM. The authentication method does not rely on system software, an authentication environment platform is established through an AHB host authentication model, test vectors are randomly sent, the security function is authenticated, results can be automatically compared, and coverage information can be automatically counted. The invention further discloses the smart card chip security authentication environment platform used for the authentication method. The smart card chip security authentication environment platform comprises a security data packet generator, a security manager, a security model, a register model, an AHB host authentication model and a scoreboard. As a DUT, and a smart card chip sub-system without a CPU core is connected with the AHB host authentication model through an AHB interface and connected with the security manager through a security signal interface. By means of the method and the platform, the authentication efficiency and completeness can be improved.
Description
Technical field
The present invention relates to the functional simulation checking field in smart card SoC (System on Chip system level chip) chip design, particularly relate to a kind of based on VMM(Verification Methodology Manual verification methodology handbook) the verification method of intelligent card chip safety check function.The invention still further relates to a kind of intelligent card chip Mag & Bag Authentication environmental level for described verification method.
Background technology
Verify and play vital effect in SoC chip design, a good verification platform and method play key effect for project schedule and chip quality.
Along with the development of chip design and verification technique, it is also more and more higher to the requirement of complex modules functional verification after chip design completes, how can complete the functional verification to complex modules at short notice, guarantee logic function is correct, has higher requirement to the completeness of verification environment and automaticity.
Smart card is vulnerable to polytype attack, and safety check function is the critical function of intelligent card chip, and for the monitoring of chip operation environment and warning, protection smart card resists attack.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of verification method of the intelligent card chip safety check function based on VMM, can complete checking fast, improves verification efficiency and checking completeness; For this reason, the present invention also will provide a kind of intelligent card chip Mag & Bag Authentication environmental level for described verification method.
For solving the problems of the technologies described above, the verification method of the intelligent card chip safety check function based on VMM of the present invention, following technical scheme is adopted to realize: to adopt VMM verification methodology, utilize SYNOPSYS(Synopsys) the AHB(Advanced High Performance Bus Advanced High-Performance Bus of company) host verification model construction intelligent card chip Mag & Bag Authentication environmental level, ambient vibration test and function coverage is utilized to collect, using not containing CPU(Central Processing Unit central processing unit) the intelligent card chip subsystem of core is as the tested design of DUT(Design Under Test), safety check function is verified.
The functional verification implemented refers to: verification environment produces random safety check content measurement, configuration DUT corresponding registers starts safety check and tests and apply test and excitation to DUT, by the test result of generation and expected result automatic comparison, and robotization statistical function coverage rate.
The intelligent card chip Mag & Bag Authentication environmental level adopted in described verification method, adopts system hardware descriptive language SystemVerilog to complete; Comprise:
One safety inspection data bag maker, complete the definition of randomization data bag, comprise safety check test enable, safety check makes mistakes enable, and the response that resets is enable, and low pressure is enable, the test such as model selection option information; Automatically safety check test configurations and test condition is sent by the form of random data bag;
One safety check manager, is connected with described safety inspection data bag maker by first passage; For resolving the random data bag obtained from described first passage, and send the action of safety check register configuration according to parsing content and produce dependence test pumping signal driving safety check signaling interface; After safety check has been tested, send the action of reading correlation behavior register, produce the actual test result of safety check;
One register model, for setting up the mapping of DUT register in verification platform, described safety check manager operates on it the operation that can be mapped to DUT register by the internalist methodology calling this register model, realize the access to register and checking;
One AHB host verification model, is connected with described register model by second channel, for the register access affairs of register model transmission being converted to pumping signal actual on AHB interface;
One safety check model, is connected with described safety inspection data bag maker by first passage, for resolving the random data bag that described safety inspection data bag maker produces, and expects test result data accordingly according to the generation of safety check detecting information;
One scoring plug, obtains data respectively by call back function, compares the test result of the actual test result of safety check and expectation in real time from described safety check manager and safety check model;
Not containing the intelligent card chip subsystem of CPU core, as tested design DUT by AHB interface and safety check signaling interface, be connected with described AHB host verification model and safety check manager respectively.
The VMM verification methodology that the present invention adopts SYNOPSYS company to provide, utilize arbitrary excitation and function coverage, construct a kind of checking that can complete fast safety check function, automatized script runs, automatic transmission test and excitation, the intelligent card chip Mag & Bag Authentication environmental level of automatic comparison result.Randomized method of testing produces test and excitation at random, test case quantity and test case size of code can be reduced, improve easy care degree, verification efficiency is greatly improved, the completeness verified can be ensured by the collection of function coverage, and the Random Test Stimulus that can produce according to test case constraint due to verification environment automatically carries out system configuration and starts safety check test, just can carry out checking work without the need to system software code.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:
Accompanying drawing is described intelligent card chip Mag & Bag Authentication environmental level schematic diagram.
Embodiment
Need in the verification method of the described intelligent card chip safety check function based on VMM verify to as if not containing CPU core intelligent card chip subsystem in safety check function.
As shown in drawings, safety inspection data bag maker produces detecting information packet at random.On the one hand, start safety check testing process by register model with the relevant DUT register of AHB host verification model configuration after safety check manager resolution data bag, send test and excitation signal to DUT, and collect test result information; On the other hand, generate after safety check model analyzing packet and expect test result information accordingly.Actual test result information and expectation test result information are sent to scoring plug and automatically compare.
By reference to the accompanying drawings, described intelligent card chip safety check functional verification environmental level, adopts SystemVerilog to complete; Mainly comprise following six assemblies: safety inspection data bag maker, safety check manager, safety check model, register model, AHB host verification model, scoring plug.By passage between assembly, call back function is connected or communication.
The primitive generator class vmm_atomic_gen that safety inspection data bag maker carries based on VMM generates, the main packet generating band safety check test option information, safety check test option information mainly comprises: whether (temperature detection is tested in enable every safety check, voltage detecting, light detects, power supply burr detection etc.), whether produce safety check false actuation signals, whether enable reset responds, and low pressure is enable, model selection etc.By the combination of these safety checks test option information, various test option and condition can be produced.These safety checks test option information can obtain at random, also can add certain constraint condition.
Safety inspection data bag maker will comprise the Packet Generation of safety check test option information to safety check manager and safety check model by first passage.Safety check manager parses current needs from packet and carries out which kind of safety check test, the need of detecting informations such as generation false activation.According to analysis result, safety check manager configures corresponding DUT register by safety check testing process and sends correct or wrong pumping signal by safety check signaling interface to DUT.After having tested, safety check manager reads DUT and to be correlated with safety check status register value reading result is sent to scoring plug by call back function, as actual test result.Safety check model, according to the packet content received, generates the correct result that current test is expected to produce, and sends to scoring plug by call back function, compares with actual test result as expectation test result.
Register model utilizes based on the RAL(Register Abstraction Layer register level of abstraction of VMM) the chip register model set up of verification technique and scheme.Owing to relating to more register configuration and reading in Mag & Bag Authentication test process, use RAL to register modeling, verification environment can be mapped to the operation to DUT register to the operation that register model carries out, and this goes access DUT register to want simple, intuitive a lot of than directly sending ahb bus operation.The access to register and checking can be completed on the one hand simply, efficiently; Be conducive on the other hand improving verification environment platform building speed, improve the readability of verification environment code.The RAL of safety check manager accesses register operation can be changed into AHB affairs by register model, and by passage, AHB affairs is passed to AHB host verification model, and then changes into the signal that can drive ahb bus.
AHB host verification model is the verification model that SYNOPSYS company provides.It is converted into concrete signal level excitation the AHB abstract level affairs that verification environment sends, thus drives ahb bus signal.Return signal can be converted into AHB abstract level affairs for verification environment by it in addition.
Function coverage is added up in safety check manager, covers point by function coverage group (covergroup) function defined function, and covers some programming count coverage rate by sampling functions.
The invention enables complete to the checking of safety check function and fully, the producing method of randomization test excitation, the result comparison of robotization, also facilitates checking to carry out regression test (Regression).
Above by embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (6)
1. the intelligent card chip safety check function verification method based on VMM, it is characterized in that: adopt VMM verification methodology, utilize Advanced High-Performance Bus AHB host verification model construction intelligent card chip Mag & Bag Authentication environmental level, ambient vibration test and function coverage is utilized to collect, not contain the intelligent card chip subsystem of CPU core as tested design DUT, the safety check Function implementation of intelligent card chip is verified.
2. verification method according to claim 1, is characterized in that: produce corresponding pumping signal and register configuration action according to safety check test option information; By setting up the mapping of register in verification environment to the modeling of tested design DUT register, complete register configuration by Advanced High-Performance Bus AHB host verification model-driven Advanced High-Performance Bus AHB interface signal.
3. verification method according to claim 1 and 2, it is characterized in that: randomization produces safety check test option information automatically, and perform corresponding registers configuration flow according to stochastic generation content and produce pumping signal, automatization judgement response results, and robotization statistical function coverage rate.
4. verification method according to claim 3, is characterized in that: described robotization statistical function coverage rate, covers point, and realized by described functional coverage point of sampling by safety check manager by functional coverage group function defined function.
5. for an intelligent card chip Mag & Bag Authentication environmental level for described verification method arbitrary in claim 1-4, it is characterized in that: adopt system hardware descriptive language SystemVerilog to complete; Comprise:
One safety inspection data bag maker, completes the definition of randomization data bag, automatically sends safety check test configurations and test condition by the form of random data bag;
One safety check manager, is connected with described safety inspection data bag maker by first passage; For resolving the random data bag obtained from described first passage, and send the action of safety check register configuration according to parsing content and produce dependence test pumping signal driving safety check signaling interface; After safety check has been tested, send the action of reading relevant safety check status register, produce the actual test result of safety check;
One register model, for setting up the mapping of tested design DUT register in verification platform, described safety check manager operates on it the operation that can be mapped to DUT register by the internalist methodology calling this register model, realize the access to register and checking;
One Advanced High-Performance Bus AHB host verification model, is connected with described register model by second channel, and the register access affairs for being transmitted by described register model are converted to pumping signal actual on Advanced High-Performance Bus AHB interface;
One safety check model, is connected with described safety inspection data bag maker by first passage; For resolving the random data bag that safety inspection data bag maker produces, and expect test result data accordingly according to the generation of safety check detecting information;
One scoring plug, obtains data respectively by call back function, compares the test result of the actual test result of safety check and expectation in real time from described safety check manager and safety check model;
Not containing the intelligent card chip subsystem of CPU core, as tested design DUT by Advanced High-Performance Bus AHB interface and safety check signaling interface, be connected with described Advanced High-Performance Bus AHB host verification model and safety check manager respectively.
6. verification environment platform according to claim 5, is characterized in that: the definition of described randomization data bag, comprises safety check test option information, this safety check test option information comprises safety check test enable, and safety check makes mistakes enable, and the response that resets is enable, low pressure is enable, model selection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310563775.5A CN104636521A (en) | 2013-11-14 | 2013-11-14 | Smart card chip security authentication method based on VMM and authentication environment platform |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310563775.5A CN104636521A (en) | 2013-11-14 | 2013-11-14 | Smart card chip security authentication method based on VMM and authentication environment platform |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104636521A true CN104636521A (en) | 2015-05-20 |
Family
ID=53215265
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310563775.5A Pending CN104636521A (en) | 2013-11-14 | 2013-11-14 | Smart card chip security authentication method based on VMM and authentication environment platform |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104636521A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106503308A (en) * | 2016-10-08 | 2017-03-15 | 中国电子科技集团公司第五十八研究所 | A kind of CAN controller IP verification platform based on UVM |
| CN106991213A (en) * | 2017-03-09 | 2017-07-28 | 记忆科技(深圳)有限公司 | A kind of method for the interaction mechanism for realizing SoC checkings |
| CN109711057A (en) * | 2018-12-28 | 2019-05-03 | 深圳忆联信息系统有限公司 | A kind of method and its system for proofing chip environment completeness |
| CN111861858A (en) * | 2020-07-10 | 2020-10-30 | 浪潮(北京)电子信息产业有限公司 | A method, device and related equipment for starting image compression function verification |
| CN114384403A (en) * | 2022-03-22 | 2022-04-22 | 浙江大学 | Chip verification IP device and test method thereof |
| CN114741308A (en) * | 2022-04-22 | 2022-07-12 | 山东云海国创云计算装备产业创新中心有限公司 | Front-end verification processing method, device and medium |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101183406A (en) * | 2007-12-25 | 2008-05-21 | 盛科网络（苏州）有限公司 | Method for establishing network chip module level function checking testing platform |
| US20090150839A1 (en) * | 2007-12-10 | 2009-06-11 | Inpa Systems, Inc. | Integrated prototyping system for validating an electronic system design |
| CN101515301A (en) * | 2008-02-23 | 2009-08-26 | 炬力集成电路设计有限公司 | Method and device for verifying SoC (system on a chip) chips |
| CN102096628A (en) * | 2009-12-15 | 2011-06-15 | 上海华虹集成电路有限责任公司 | Method for realizing microprogrammed control unit (MCU) verification platform based on verification methodology of verification methodology manual (VMM) |
| CN102591757A (en) * | 2011-01-05 | 2012-07-18 | 上海华虹集成电路有限责任公司 | Verification method and verification environment platform based on intelligent card universal serial bus (IC-USB) interface module of verification methodology (VMM) |
-
2013
- 2013-11-14 CN CN201310563775.5A patent/CN104636521A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090150839A1 (en) * | 2007-12-10 | 2009-06-11 | Inpa Systems, Inc. | Integrated prototyping system for validating an electronic system design |
| CN101183406A (en) * | 2007-12-25 | 2008-05-21 | 盛科网络（苏州）有限公司 | Method for establishing network chip module level function checking testing platform |
| CN101515301A (en) * | 2008-02-23 | 2009-08-26 | 炬力集成电路设计有限公司 | Method and device for verifying SoC (system on a chip) chips |
| CN102096628A (en) * | 2009-12-15 | 2011-06-15 | 上海华虹集成电路有限责任公司 | Method for realizing microprogrammed control unit (MCU) verification platform based on verification methodology of verification methodology manual (VMM) |
| CN102591757A (en) * | 2011-01-05 | 2012-07-18 | 上海华虹集成电路有限责任公司 | Verification method and verification environment platform based on intelligent card universal serial bus (IC-USB) interface module of verification methodology (VMM) |
Non-Patent Citations (4)
| Title |
|---|
| 侯超等: ""利用VMM搭建NANDFlash控制器验证平台"", 《广东电信技术》 * |
| 李磊等: ""基于VMM方法的SOC集成验证"", 《电子测量技术》 * |
| 章林柯等: ""基于VMM方法学的系统级软硬件协同仿真验证"", 《微型机与应用》 * |
| 肖庚亮: ""基于VMM的SOC可重用验证平台设计"", 《科学技术与工程》 * |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106503308A (en) * | 2016-10-08 | 2017-03-15 | 中国电子科技集团公司第五十八研究所 | A kind of CAN controller IP verification platform based on UVM |
| CN106503308B (en) * | 2016-10-08 | 2019-03-19 | 中国电子科技集团公司第五十八研究所 | A kind of CAN controller IP verification platform based on UVM |
| CN106991213A (en) * | 2017-03-09 | 2017-07-28 | 记忆科技(深圳)有限公司 | A kind of method for the interaction mechanism for realizing SoC checkings |
| CN109711057A (en) * | 2018-12-28 | 2019-05-03 | 深圳忆联信息系统有限公司 | A kind of method and its system for proofing chip environment completeness |
| CN111861858A (en) * | 2020-07-10 | 2020-10-30 | 浪潮(北京)电子信息产业有限公司 | A method, device and related equipment for starting image compression function verification |
| CN114384403A (en) * | 2022-03-22 | 2022-04-22 | 浙江大学 | Chip verification IP device and test method thereof |
| CN114741308A (en) * | 2022-04-22 | 2022-07-12 | 山东云海国创云计算装备产业创新中心有限公司 | Front-end verification processing method, device and medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104636521A (en) | Smart card chip security authentication method based on VMM and authentication environment platform | |
| CN108446215B (en) | Method, device, system and terminal for POS machine testing | |
| CN106874187B (en) | Code coverage rate collection method and device | |
| KR101414720B1 (en) | Functional safety testing device for train control system software and the method thereof | |
| CN106133537A (en) | A kind of FPGA function module emulation verification method and system thereof | |
| CN103530216A (en) | PCIE verification method based on UVM | |
| CN106201892B (en) | Abnormal interrupt source position finding and detection method for embedded software | |
| CN105787364B (en) | Automatic testing method, device and system for tasks | |
| CN113312226B (en) | Verification platform, device and storage medium for testing abnormal characteristics of logic design | |
| CN105738854A (en) | Simulation memory test board system for intelligent ammeter embedded application and test method | |
| CN113407393A (en) | Chip verification method, terminal device, verification platform and storage medium | |
| CN103577313A (en) | Mobile terminal application program testing method and device | |
| CN111459616B (en) | A test method, device, equipment and storage medium | |
| CN103077110B (en) | A kind of method of testing and device | |
| CN112367680B (en) | External communication test method, device and computer equipment based on smart meter | |
| CN103905270A (en) | Smart grid android system safety base line automatic checking system and method | |
| CN104486169A (en) | Reusable automatic detection and random verification system and method | |
| CN107819611B (en) | Client test method based on IEC61850 multi-server simulation | |
| CN103530209A (en) | Automated testing method for code keyboard | |
| CN106802863A (en) | Interprocess communication security formalization analysis checking system based on micro-kernel prototype | |
| CN108108276A (en) | A kind of universal testing method and device for log alarming function | |
| CN105187608A (en) | Method and device obtaining power consumption of application program in mobile terminal | |
| CN113704126A (en) | Verification method and device, computer storage medium and processor | |
| CN113535578A (en) | CTS (clear to send) testing method, device and testing equipment | |
| CN103078740A (en) | RFID (Radio Frequency Identification Devices) smart card digital baseband verification system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20150520 |