CN104616989A - Method for manufacturing IGBT having current-carrying electron storage layer - Google Patents

Abstract

The present invention provides a method for manufacturing an IGBT with a current-carrying electron storage layer, which includes: providing a substrate having a first surface and a second surface; forming a first groove on the first surface of the substrate; Epitaxially forming a first epitaxial layer of the same conductivity type as the substrate on the first groove, the first epitaxial layer fills the first groove; grinding the first epitaxial layer until the first surface of the substrate is exposed ; Forming a second groove with a depth and a width less than the depth and width of the first groove on the upper surface of the first epitaxial layer after grinding to leave a part of the first epitaxial layer, and the remaining first epitaxial layer is used as a current-carrying electron storage layer; epitaxially forming a second epitaxial layer of the same conductivity type as the substrate on the second groove, the second epitaxial layer filling the second groove; grinding the second epitaxial layer until the lining is exposed the first surface of the bottom. This method can avoid the problem of low breakdown voltage of the device due to the concentration problem at the corner of CS.

Description

A method of manufacturing an IGBT with a current-carrying electron storage layer

【Technical field】

The invention relates to the technical field of semiconductor design and manufacture, in particular to a method for manufacturing an IGBT (Insulated Gate Bipolar Transistor, insulated gate bipolar transistor) with a current-carrying electron storage layer.

【Background technique】

IGBT is a composite fully-controlled voltage-driven power semiconductor device composed of BJT (Bipolar Junction Transistor, bipolar junction transistor) and MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor, metal-oxide-semiconductor field-effect transistor) , has both the advantages of high input impedance of MOSFET and low conduction voltage drop of BJT. It has the characteristics of high operating frequency, simple control circuit, high current density and low on-state voltage. It is widely used in the field of power control. In practical applications, IGBT is rarely used as an independent device, especially under the condition of inductive load, IGBT needs a fast recovery diode freewheeling. Therefore, the existing IGBT products generally use a freewheeling diode (FWD for short) connected in parallel to protect the IGBT.

The existing IGBT with a current-carrying electron storage layer mainly uses ion implantation to form a current-carrying electron storage layer (CS layer). The well takes a long time; and the corner of the CS layer is easy to break down, resulting in a low overall breakdown voltage of the device.

Therefore, it is necessary to provide an improved technical solution to overcome the above problems.

【Content of invention】

The purpose of the present invention is to provide a method for manufacturing an IGBT with a current-carrying electron storage layer, which is compatible with the existing conventional process, and the concentration of the CS layer is easy to control, high in efficiency, and can avoid the problem of the concentration of the CS corner causing the device to The problem of low breakdown voltage.

In order to solve the above problems, according to one aspect of the present invention, the present invention provides a method for manufacturing an IGBT with a current-carrying electron storage layer, which includes:

providing a substrate having a first surface and a second surface;

forming a first groove on the first surface of the substrate;

A first epitaxial layer of the same conductivity type as the substrate is epitaxially formed on the first groove, and the first epitaxial layer fills the first groove, wherein the doping concentration of the first epitaxial layer is higher than that of the substrate high concentration;

grinding the first epitaxial layer until the first surface of the substrate is exposed;

On the upper surface of the polished first epitaxial layer, a second groove with a depth and width smaller than the depth and width of the first groove is formed to leave a part of the first epitaxial layer, and the remaining first epitaxial layer is used as a carrier electron storage layer;

epitaxially forming a second epitaxial layer of the same conductivity type as the substrate on the second groove, the second epitaxial layer filling the second groove; and

Grinding the second epitaxial layer until the first surface of the substrate is exposed.

As a preferred embodiment of the present invention, the doping concentration of the second epitaxial layer is equal to the doping concentration of the substrate.

As a preferred embodiment of the present invention, the front structure of the IGBT is formed on one side of the first surface of the substrate formed with the first epitaxial layer and the second epitaxial layer,

A reverse structure of the IGBT is formed on one side of the second surface of the substrate on which the first epitaxial layer and the second epitaxial layer are formed.

As a preferred embodiment of the present invention, the front structure of the IGBT includes:

selectively forming a base region with a conductivity type different from that of the substrate on the first epitaxial layer;

An emitter region of the same conductivity type as the substrate is selectively formed in the base region;

a gate oxide layer on the substrate;

a polysilicon gate formed on the surface of the gate oxide layer;

a dielectric layer covering the gate oxide layer and the polysilicon gate;

a front metal electrode in electrical contact with the base region and the emitter region;

The reverse structure of the IGBT includes:

forming a collector layer of a conductivity type different from that of the substrate on the second surface of the substrate;

A back metal electrode is formed on the collector layer, and the back metal electrode is in electrical contact with the collector layer.

As a preferred embodiment of the present invention, the front structure of the IGBT further includes:

A passivation layer formed on the outside of the front metal electrode.

The present invention also provides another method for manufacturing an IGBT with a current-carrying electron storage layer, which includes:

providing a substrate having a first surface and a second surface;

forming a first groove on the first surface of the substrate;

A first epitaxial layer of the same conductivity type as the substrate is epitaxially formed on the first groove, and the first epitaxial layer fills the first groove, wherein the doping concentration of the first epitaxial layer is higher than that of the substrate high concentration;

grinding the first epitaxial layer until the first surface of the substrate is exposed;

forming the front side structure of the IGBT directly on the side of the first surface of the substrate on which the first epitaxial layer is formed, and

A reverse structure of the IGBT is formed on one side of the second surface of the substrate on which the first epitaxial layer is formed.

As a preferred embodiment of the present invention, the front structure of the IGBT includes:

selectively forming a base region with a conductivity type different from that of the substrate on the first epitaxial layer;

An emitter region of the same conductivity type as the substrate is selectively formed in the base region;

a gate oxide layer on the substrate;

a polysilicon gate formed on the surface of the gate oxide layer;

a dielectric layer covering the gate oxide layer and the polysilicon gate;

a front metal electrode in electrical contact with the base region and the emitter region;

The reverse structure of the IGBT includes:

forming a collector layer of a conductivity type different from that of the substrate on the second surface of the substrate;

A back metal electrode is formed on the collector layer, and the back metal electrode is in electrical contact with the collector layer.

As a preferred embodiment of the present invention, the front structure of the IGBT further includes:

A passivation layer formed on the outside of the front metal electrode.

As a preferred embodiment of the present invention, the grinding method is a chemical mechanical polishing process.

Compared with the prior art, in a method for manufacturing an IGBT with a current-carrying electron storage layer in the present invention, the CS layer is realized by using an epitaxial growth method compatible with conventional existing processes, the process is simple, the concentration of the CS layer is easy to control, and the efficiency is high. High, and can avoid the problem of low breakdown voltage of the device due to the concentration problem at the corner of CS.

【Description of drawings】

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the accompanying drawings that need to be used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For Those of ordinary skill in the art can also obtain other drawings based on these drawings without any creative effort. in:

Fig. 1 is the flowchart in one embodiment of the manufacturing method of the IGBT with current-carrying electron storage layer in the present invention;

FIG. 2 to FIG. 7 are longitudinal cross-sectional schematic diagrams of wafers obtained in each manufacturing process of the manufacturing method in FIG. 1 .

【Detailed ways】

In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

Reference herein to "one embodiment" or "an embodiment" refers to a particular feature, structure or characteristic that can be included in at least one implementation of the present invention. "In one embodiment" appearing in different places in this specification does not all refer to the same embodiment, nor is it a separate or selective embodiment that is mutually exclusive with other embodiments.

Before introducing the manufacturing method of the IGBT with the current-carrying electron storage layer in the present invention, it should be noted that the surface where the emitter and the gate of the IGBT are generally understood as the front side, and the surface where the collector of the IGBT is generally Understand reverse or back side.

FIG. 1 is a flow chart of an embodiment of a method 100 for manufacturing an IGBT with a current-carrying electron storage layer in the present invention. As shown in FIG. 1 , the manufacturing method 100 includes the following steps.

Step 110 , providing an N-type or P-type substrate 10 having a first surface 11 and a second surface 12 .

Specifically, the substrate 10 is a silicon wafer, and its thickness is normal. For example, the thickness of a 6-inch wafer is the thickness of a normal circulation silicon wafer. For example, the normal thickness of a 6-inch wafer is 625 μm/675 μm, and the normal thickness of an 8-inch wafer is is 725 μm.

Step 120 , as shown in FIG. 2 , forms a first groove 13 on the first surface 11 of the substrate 10 .

In one embodiment, the first groove 13 may be formed by an etching process, of course, other processes may also be used.

Step 130, as shown in FIG. 3, performs epitaxial filling on the first groove 13 to form an N-type or P-type first epitaxial layer 14, and the first epitaxial layer 14 fills the first groove 13, so The doping concentration of the first epitaxial layer 14 is higher than the doping concentration of the substrate 10 .

Specifically, the lower surface of the first epitaxial layer is in contact with the first surface 11 of the substrate, and the lowest point of the upper surface of the first epitaxial layer is higher than the highest point of the first surface 11 of the substrate. point.

When the substrate is N-type, an N-type first epitaxial layer 14 is formed in the step 130, and when the substrate 10 is P-type, a P-type first epitaxial layer 14 is formed in the step 130, both The conductivity type between them is the same. In the embodiments shown in FIGS. 2-7 , the substrate material 10 is N-type, and the first epitaxial layer 14 is N-type as an example for introduction. Specifically, as shown in FIG. 3 , epitaxial filling is performed on the first groove 13 to form an N-type first epitaxial layer 14 with a resistivity of 5˜100Ω*cm. The doping concentration of the first epitaxial layer 14 is higher than that of the substrate 10 , and the doping substance is N-type impurity ions (such as phosphorus or arsenic).

Step 140 , as shown in FIG. 4 , grinds the first epitaxial layer 14 until the first surface 11 of the substrate 10 is exposed.

Specifically, the first epitaxial layer 14 is polished from the upper surface of the first epitaxial layer 14 by chemical mechanical polishing (CMP) until the first surface 11 of the substrate 10 is exposed. An upper surface of an epitaxial layer 14 is flush with the first surface 11 of the substrate 10 .

Step 150, as shown in FIG. 5 , forms a second groove 17 with a depth and width smaller than the depth and width of the first groove 13 on the upper surface of the ground first epitaxial layer 14 to leave a part of the first epitaxial layer , the remaining first epitaxial layer serves as the current-carrying electron storage layer 18;

Specifically, a second groove 17 is formed on the upper surface of the first epitaxial layer 14; at this time, the first epitaxial layer 14 forms a current-carrying electron storage layer 18; the depth and width of the first groove 13 are greater than The depth and width of the second groove 17.

Step 160, performing epitaxial filling on the second groove 17 to form an N-type second epitaxial layer 19, and the second epitaxial layer 19 fills the second groove 17;

Specifically, the lower surface of the second epitaxial layer 19 is in contact with the upper surface of the first epitaxial layer 14, and the lowest point of the upper surface of the second epitaxial layer 19 is higher than that of the first epitaxial layer 14. At the highest point on the upper surface, the doping concentration of the second epitaxial layer 19 is equal to the doping concentration of the substrate 10 , in order to be compatible with the existing process, without changing the subsequent process.

Step 170 , as shown in FIG. 6 , grinds the second epitaxial layer 19 until the first surface 11 of the substrate 10 is exposed.

Specifically, the second epitaxial layer 19 is polished from the upper surface of the second epitaxial layer 19 until the first surface 11 of the substrate is exposed through a chemical mechanical polishing process.

Step 180, as shown in FIG. 7 , forms the front structure of the IGBT on one side of the first surface 11 of the substrate 10 on which the first epitaxial layer 14 and the second epitaxial layer 19 are formed,

Step 190 , as shown in FIG. 7 , forms the reverse structure of the IGBT on one side of the second surface 12 of the substrate 10 on which the first epitaxial layer 14 and the second epitaxial layer 19 are formed.

Specifically, as shown in FIG. 7 , the N-type substrate 10 is used as the drift region 22 , and the front structure and the back structure of the IGBT with the current-carrying electron storage layer are formed based on the drift region 22 .

FIG. 7 schematically shows a front structure of a planar IGBT. The front structure of the IGBT includes: a P-type base region (P-body) 23 selectively formed on the surface of the first epitaxial layer 14, and an N-body selectively formed in the P-type base region 23. Type emitter region 24, a gate oxide layer (not shown) located on the first surface 11 of the drift region 22, a polysilicon gate 25 formed on the gate oxide layer, covering the gate oxide layer The dielectric layer with the polysilicon gate 25 is not shown, and the front metal electrode (ie, the emitter, not shown) electrically contacts the P-type base region 23 and the N-type emitter region 24 .

FIG. 7 only schematically shows the front metal electrodes. In fact, the front metal electrodes may cover the entire dielectric layer. In addition, the front structure of the IGBT may further include a passivation layer (not shown), such as silicon dioxide and silicon nitride, formed outside the front metal electrode.

In other embodiments, trench type IGBTs can also be manufactured, and the front structure of the trench type IGBT is different from that of the IGBT in FIG. 7 , but many trench type IGBTs have been disclosed in the prior art. The description will not be repeated here. It should be known that, from a certain point of view of the present invention, the present invention does not particularly care about the specific front structure of the IGBT, as long as there is a front structure and a usable IGBT device can be formed.

The present invention proposes an example of the manufacturing process of the front structure of the IGBT in FIG. 7, the process includes:

Step 1, growing a gate oxide layer, for example, with a thickness of

Step 2, generate a polysilicon gate layer on the gate oxide layer, for example, the thickness is

Step 3: polysilicon gate photolithography, etching, ion implantation, and well push to form a P base region. The implantation dose of P-type impurities is 1E12-1E15cm ^-2 , and the implantation energy is 20keV-1MeV; the well push temperature is 1000-1250°C, and the time is 10min~1000min.

Step 4: Photolithography, ion implantation, and annealing of the N-type emission region to form N-type, the dose is 1E14-1E16cm ^-2 , the energy is 20keV-1MeVcm ^-2 ; the annealing temperature is 800-1000°C, and the time is 10min-1000min;

Step five, growth medium layer, thickness:

Step 6, contact hole photolithography and etching to form a contact hole, which communicates with the N-type emitter region and the P-type base region;

Step 7. Depositing the front metal layer with a thickness of about 2 μm to 6 μm;

Step eight, passivation layer deposition.

FIG. 7 also shows the back structure of the IGBT. The back structure of the IGBT includes: forming a P-type collector layer 26 on the second surface 12 of the drift region 22;

A back metal electrode is formed on the P-type collector layer 26 , and the back metal electrode is in electrical contact with the P-type collector layer 26 .

From another point of view, the specific manufacturing process of the front and back structures of the IGBT does not belong to the key point of the present invention, which can be manufactured by various existing manufacturing processes. Therefore, in order to highlight the key points of the present invention, the relevant IGBT The specific manufacturing process of the front and back structures is not described in detail in this paper.

The present invention also provides another implementation manner. The steps in this implementation manner include the above steps 110-140, so steps 110-140 will not be repeated here.

After step 140, the front structure of the IGBT is directly formed on one side of the first surface 11 of the substrate 10 on which the first epitaxial layer 14 is formed,

The reverse structure of the IGBT is formed on the side of the second surface 12 of the substrate 10 where the first epitaxial layer 14 is formed.

Since the fabrication of the front and back structures of the IGBT has been introduced in detail in the first fabrication method of the IGBT with the current-carrying electron storage layer, it will not be repeated here.

It should be noted that in this manufacturing method, the implantation energy and dose of the P-type base region (P-body) 23 and the N-type emitter region 24 need to be reset. Because the doping concentration of the first epitaxial layer 14 is higher than that of the substrate 10, in order to ensure that the turn-on voltage Vth does not decrease, the implantation dose of the P-type base region 23 needs to be increased (the energy may not be changed), so as to compensate for the doping of the substrate 10. The specific increase depends on the doping concentration of the first epitaxial layer 14. Similarly, the implantation dose of the N-type emitter region 24 can be reduced (the energy can not be changed).

Those of ordinary skill in the art should be able to understand that one of the characteristics or purposes of the present invention is: using the method of epitaxially growing the CS layer to effectively control the doping concentration of the CS layer, and compatible with conventional existing processes, the process is simple, The efficiency is high, and the concentration of the CS corner is better handled, and it will not become a weak point of breakdown.

The N type in the above embodiments may be referred to as the first conductivity type, and the P type may be referred to as the second conductivity type. In other embodiments, all the P-type regions involved in the above-mentioned embodiments (such as P base region, P-type collector region) can be changed to N-type, and all N-type regions (N-type drift region , N-type current-carrying electron storage layer, and N-type emitter region) can all be changed to P-type. At this time, it can be considered that the first conductivity type is N-type, and the second conductivity type is P-type.

It should be pointed out that any changes made by those skilled in the art to the specific embodiments of the present invention will not depart from the scope of the claims of the present invention. Accordingly, the scope of the claims of the present invention is not limited only to the foregoing specific embodiments.

Claims (9)

1. A method for manufacturing an IGBT with a current-carrying electron storage layer, characterized in that it comprises: providing a substrate having a first surface and a second surface; forming a first groove on the first surface of the substrate; A first epitaxial layer of the same conductivity type as the substrate is epitaxially formed on the first groove, and the first epitaxial layer fills the first groove, wherein the doping concentration of the first epitaxial layer is higher than that of the substrate high concentration; grinding the first epitaxial layer until the first surface of the substrate is exposed; On the upper surface of the polished first epitaxial layer, a second groove with a depth and width smaller than the depth and width of the first groove is formed to leave a part of the first epitaxial layer, and the remaining first epitaxial layer is used as a carrier electron storage layer; epitaxially forming a second epitaxial layer of the same conductivity type as the substrate on the second groove, the second epitaxial layer filling the second groove; and Grinding the second epitaxial layer until the first surface of the substrate is exposed. 2. The method for manufacturing an IGBT with a current-carrying electron storage layer according to claim 1, further comprising: The doping concentration of the second epitaxial layer is equal to the doping concentration of the substrate. 3. The method for manufacturing an IGBT with a current-carrying electron storage layer according to claim 1, further comprising: forming a front structure of the IGBT on one side of the first surface of the substrate formed with the first epitaxial layer and the second epitaxial layer, A reverse structure of the IGBT is formed on one side of the second surface of the substrate on which the first epitaxial layer and the second epitaxial layer are formed. 4. The method for manufacturing an IGBT with a current-carrying electron storage layer according to claim 3, characterized in that, The front structure of the IGBT includes: selectively forming a base region with a conductivity type different from that of the substrate on the first epitaxial layer; An emitter region of the same conductivity type as the substrate is selectively formed in the base region; a gate oxide layer on the substrate; a polysilicon gate formed on the surface of the gate oxide layer; a dielectric layer covering the gate oxide layer and the polysilicon gate; and a front metal electrode in electrical contact with the base region and the emitter region; The reverse structure of the IGBT includes: forming a collector layer of a conductivity type different from that of the substrate on the second surface of the substrate; A back metal electrode is formed on the collector layer, and the back metal electrode is in electrical contact with the collector layer. 5. The method for manufacturing an IGBT with a current-carrying electron storage layer according to claim 4, wherein the front structure of the IGBT further comprises: A passivation layer formed on the outside of the front metal electrode. 6. A method for manufacturing an IGBT with a current-carrying electron storage layer, characterized in that it comprises: providing a substrate having a first surface and a second surface; forming a first groove on the first surface of the substrate; A first epitaxial layer of the same conductivity type as the substrate is epitaxially formed on the first groove, and the first epitaxial layer fills the first groove, wherein the doping concentration of the first epitaxial layer is higher than that of the substrate high concentration; grinding the first epitaxial layer until the first surface of the substrate is exposed; forming the front structure of the IGBT directly on the side of the first surface of the substrate formed with the first epitaxial layer; and A reverse structure of the IGBT is formed on one side of the second surface of the substrate on which the first epitaxial layer is formed. 7. The method for manufacturing an IGBT with a current-carrying electron storage layer according to claim 6, characterized in that, The front structure of the IGBT includes: selectively forming a base region with a conductivity type different from that of the substrate on the first epitaxial layer; An emitter region of the same conductivity type as the substrate is selectively formed in the base region; a gate oxide layer on the substrate; a polysilicon gate formed on the surface of the gate oxide layer; a dielectric layer covering the gate oxide layer and the polysilicon gate; a front metal electrode in electrical contact with the base region and the emitter region; The reverse structure of the IGBT includes: forming a collector layer of a conductivity type different from that of the substrate on the second surface of the substrate; A back metal electrode is formed on the collector layer, and the back metal electrode is in electrical contact with the collector layer. 8. The method for manufacturing an IGBT with a current-carrying electron storage layer according to claim 7, wherein the front structure of the IGBT further comprises: A passivation layer formed on the outside of the front metal electrode. 9. The method for manufacturing an IGBT with a current-carrying electron storage layer according to claim 1 or 6, wherein The grinding method is a chemical mechanical polishing process.