CN104601924A - FPGA (Field Programmable Gate Array) based video image compensating method and device - Google Patents
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Abstract
The invention provides FPGA (Field Programmable Gate Array) based video image compensating method and device. The device is a DDR3 storage is hung to the outside of the FPGA. The method comprises the steps of storing the images into the DDR3 storage according to frame; determining whether the images are deviated in the horizontal direction; if so, distributing an instruction by a host computer to adjust the reading time of the line data or adjusting the generation time of the line synchronizing signals and carrying out the next step; if not so, carrying out the next step; determining whether the images are deviated in the vertical direction; if so, distributing an instruction by a host computer to adjust the reading time of the first line data or adjusting the generation time of the field synchronizing signals; if not so, remaining the images at the current position in a video display device. The FPGA based video image compensating method and device have the beneficial effects that the user video experience is increased; the adjusting range is out of limitation; special chips are not used; the complexity of development implementation can be reduced; the stability of the system is improved; the cost is reduced.
Description
Technical field
The present invention relates to field of video transmission, particularly a kind of video image compensation method based on FPGA and device.
Background technology
In transmission of video display field, VGA is as analog video signal, still in a large amount of uses, but owing to having decay in analog signal transmission, be easily interfered, the video pictures finally presented on the display device is occurred, and picture shields partially, or left avertence, or right avertence, or partially upper, or partially lower, bring very bad video tastes to user.
Therefore, this just needs to carry out adjustment compensation, picture is adjusted to the middle of video display apparatus to video picture.Prior art is realized by specialized simulation chip, the adjustable range in direction, picture upper and lower, left and right is limited or only support the adjustment of single dimension, and integrate the exploitation implementation procedure more complicated used, cost is higher, thus make design become more complicated, the therefore stability of influential system.It is not easy to unitized in multiple product use, affects the consistency of product design.Old product upgrades real must redesign, and time cost and Material Cost are all huge.Use and need to pay high software copyright expense or license expense, so cost is higher.
Summary of the invention
The technical problem to be solved in the present invention is, limited for the video tastes of the above-mentioned user of impact of prior art, adjustable range, must to use special chip, exploitation implementation procedure more complicated, the system defect that stability is not high, cost is higher, provides the video tastes of a kind of user of lifting, adjustable range does not limit, need not use special chip, reduces the complexity of exploitation implementation procedure, the stability improving system, the video image compensation method based on FPGA reduced costs and device.
The technical solution adopted for the present invention to solve the technical problems is: construct a kind of video image compensation method based on FPGA, a kind of video image compensation method based on FPGA, it is characterized in that, hang with DDR3 memory outside described FPGA, described method comprises the steps:
A) image is stored in frame by frame in described DDR3 memory;
B) judge whether described image offsets in the horizontal direction, in this way, send instructions under host computer the reading time of adjustment row data or the generation time of adjustment line synchronizing signal, performs step C); Otherwise, perform step C);
C) judge whether described image offsets in vertical direction, in this way, send instructions under described host computer the reading time of adjustment first trip data or the generation time of adjustment field sync signal; Otherwise, keep the current location of described image in video display apparatus.
Of the present invention based in the video image compensation method of FPGA, described step B) comprise further:
B1) judge image whether left avertence, in this way, send instructions under host computer and delay a bat or clap read line data more, or send instructions under described host computer and one clap and produce line synchronizing signal in advance, perform step B2); Otherwise, perform step B2);
B2) judge described image whether right avertence, in this way, send instructions under described host computer one to clap or clap reads described row data morely, or send instructions under described host computer in advance and delay a bat and produce described line synchronizing signal, perform step C); Otherwise, perform step C).
Of the present invention based in the video image compensation method of FPGA, described step C) comprise further:
C1) judge whether image is gone up partially, in this way, send instructions under host computer and delay a line or multirow reading first trip data, or a line in advance that sends instructions under described host computer produces described field sync signal, performs step C2); Otherwise, perform step C2);
C2) judge that described image is whether partially lower, in this way, send instructions under described host computer a line or multirow in advance read described first trip data, or send instructions under described host computer and delay a line and produce described field sync signal; Otherwise, keep the current location of described image in video display apparatus.
Of the present invention based in the video image compensation method of FPGA, a described bat is exactly a pixel.
The invention still further relates to a kind of device realizing the above-mentioned video image compensation method based on FPGA, hang with DDR3 memory outside described FPGA, described device comprises:
Memory cell: for image being stored in frame by frame in described DDR3 memory;
Horizontal-shift judging unit: for judging whether described image offsets in the horizontal direction, in this way, send instructions under host computer the reading time of adjustment row data or the generation time of adjustment line synchronizing signal; Otherwise, judge whether described image offsets in vertical direction;
Vertical shift judging unit: for judging whether described image offsets in vertical direction, in this way, send instructions under described host computer the reading time of adjustment first trip data or the generation time of adjustment field sync signal; Otherwise, keep the current location of described image in video display apparatus.
In device of the present invention, described horizontal-shift judging unit comprises further:
Left avertence judge module: for judging image whether left avertence, in this way, sends instructions under host computer and delays a bat or clap read line data more, or sends instructions under described host computer and one clap and produce line synchronizing signal in advance; Otherwise, judge described image whether right avertence;
Right avertence judge module: for judging described image whether right avertence, in this way, sends instructions under described host computer one to clap or clap reads described row data morely, or send instructions under described host computer in advance and delays a bat and produce described line synchronizing signal; Otherwise, judge whether described image offsets in vertical direction.
In device of the present invention, described vertical shift judging unit comprises further:
Upper inclined judge module: for judging whether image is gone up partially, in this way, sends instructions and delay a line or multirow reading first trip data, or a line in advance that sends instructions under described host computer produces described field sync signal under host computer; Otherwise, judge that whether described image is partially lower;
Lower inclined judge module: for judging that whether described image is partially lower, in this way, send instructions under described host computer a line or multirow in advance read described first trip data, or send instructions under described host computer and delay a line and produce described field sync signal; Otherwise, keep the current location of described image in video display apparatus.
In device of the present invention, a described bat is exactly a pixel.
Implement the video image compensation method based on FPGA of the present invention and device, there is following beneficial effect: owing to image being stored in frame by frame in DDR3 memory; When skew occurs image in the horizontal direction, send instructions under host computer the reading time of adjustment row data or the generation time of adjustment line synchronizing signal; When whether image there is skew in vertical direction, send instructions under host computer the reading time of adjustment row data or the generation time of adjustment field sync signal, it need not use special chip, thus its can promote the video tastes of user, adjustable range does not limit, need not use special chip, reduce the complexity of exploitation implementation procedure, improve the stability of system, reduce costs.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the flow chart that the present invention is based on method in the video image compensation method of FPGA and device embodiment;
Fig. 2 judges in described embodiment whether image the particular flow sheet offset occurs in the horizontal direction;
Fig. 3 is the sequential chart of often going in described embodiment;
Fig. 4 judges in described embodiment whether image the particular flow sheet offset occurs in vertical direction;
Fig. 5 is the sequential chart of every frame in described embodiment;
Fig. 6 be in described embodiment image left avertence and upper inclined time the schematic diagram that compensates;
Fig. 7 is the structural representation of device in described embodiment.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
In the video image compensation method that the present invention is based on FPGA and device embodiment, its flow chart based on the video image compensation method of FPGA as shown in Figure 1.In the present embodiment, hang with DDR3 memory outside FPGA, the inside of FPGA is provided with DDR3 controller, in Fig. 1, should comprise the steps: based on the video image compensation method of FPGA
Image is stored in DDR3 memory by step S01 frame by frame: the present invention is based on DDR3 memory technology, uses the DDR3 controller of FPGA inside to complete the access of data.According to the relation between the row, column of image, these three keys of pixel, dynamically adjust image, real-Time Compensation image shift.In this step, be stored in frame by frame by image in DDR3 memory, namely first image on a frame-by-frame basis being circulated is stored in DDR3 memory.
Step S02 judges whether image offsets in the horizontal direction: in this step, judge whether image offsets in the horizontal direction, namely when the middle of image not at video display apparatus, judge whether image there occurs skew in the horizontal direction, if the result judged is yes, then perform step S03; Otherwise, perform step S04.
Send instructions under step S03 host computer the reading time of adjustment row data or the generation time of adjustment line synchronizing signal: if the judged result of above-mentioned steps S02 is yes, then perform this step.In this step, send instructions under host computer the reading time of adjustment row data or the generation time of adjustment line synchronizing signal, and specifically how to adjust, rear extended meeting is described in detail.Execute this step, perform step S04.
Step S04 judges whether image offsets in vertical direction: in this step, judges whether image offsets in vertical direction, if the result judged is yes, then performs step S06; Otherwise, perform step S05.
Step S05 keeps the current location of image in video display apparatus: if the judged result of above-mentioned steps S04 is no, then perform this step.In this step, keep the current location of image in video display apparatus.
Send instructions under step S06 host computer the reading time of adjustment first trip data or the generation time of adjustment field sync signal: if the judged result of above-mentioned steps S04 is yes, then perform this step.In this step, send instructions under host computer the reading time of adjustment first trip data or the generation time of adjustment field sync signal, and about what specifically how to adjust, rear extended meeting is described in detail.Due to need not special chip be used, thus its can promote the video tastes of user, adjustable range does not limit, need not use special chip, reduce the complexity of exploitation implementation procedure, improve the stability of system, reduce costs.
For the present embodiment, above-mentioned steps S02-step S03 also can refinement further, and the flow chart after its refinement as shown in Figure 2.In Fig. 2, above-mentioned steps S02-step S03 comprises further:
Step S21 judges image whether left avertence: in this step, judges image whether left avertence, if the result judged is yes, then performs step S22; Otherwise, perform step S23.
Send instructions under step S22 host computer and delay a bat or many bat read line data, or the bat in advance that sends instructions under host computer produces line synchronizing signal: if the judged result of above-mentioned steps S21 is yes, then perform this step.In this step, send instructions under host computer and delay a bat or many bat read line data, or send instructions under host computer and one clap generation line synchronizing signal in advance, concrete, if image left avertence, description line data are exported in advance, user can send instructions and delay pixel read line data from host computer, if image still left avertence, then continues to delay pixel read line data, or send instructions under host computer line synchronizing signal shift to an earlier date one bat produce, until image is placed in the middle.Here a bat is exactly a pixel.Execute this step, perform step S23.
Step S23 judges image whether right avertence: in this step, judges image whether right avertence, if the result judged is yes, then performs step S24; Otherwise, perform step S04.
Send instructions under step S24 host computer one to clap or many bat read line data, or send instructions under host computer in advance and delay a bat generation line synchronizing signal: if the judged result of above-mentioned steps S23 is yes, then perform in this step.In this step, send instructions under host computer and one clap or many bat read line data (pixel data of often going) in advance, or send instructions under host computer and delay a bat generation line synchronizing signal, concrete, if image right avertence, description line data are delayed output, user can send instructions and shift to an earlier date pixel read line data from host computer, if image is right avertence still, then continue to put forward previous pixel read line data, or send instructions under host computer line synchronizing signal delay one bat produce, until image is placed in the middle.That eliminate special chip, reduce cost.
The concrete time sequence parameter of each resolution, it is the foundation that the present invention designs, for 1920x1080p@59.94/60Hz resolution, its sequential chart of often going as shown in Figure 3, in Fig. 3, often capable total 2200 pixel clock period, wherein 280 is blanking zone, 1920 is the effective video data transmitted, i.e. payload.Judge that the condition of valid data is data enable signal data enable as high level, FPGA inside can be judged as logical one; The width of line synchronizing signal hsync is 44 clock cycle, 88 clock cycle of trailing edge of its rising edge range data enable signal data enable, rises 148 clock cycle of rising edge along range data enable signal dataenable under it.FPGA is inner when structure exports data, can adjust the size of these parameters, to improve the problem of image left avertence or right avertence.
For the present embodiment, above-mentioned steps S04-step S06 also can refinement further, and the flow chart after its refinement as shown in Figure 4.In Fig. 4, above-mentioned steps S04-step S06 comprises further:
Step S41 judges whether image is gone up partially: in this step, judges whether image is gone up partially, if the result judged is yes, then performs step S42; Otherwise, perform step S43.
Send instructions under step S42 host computer and delay a line or multirow reading first trip data, or a line in advance that sends instructions under host computer produces field sync signal: if the judged result of above-mentioned steps S41 is yes, then perform this step.In this step, send instructions under host computer and delay a line or multirow reading first trip data, or a line in advance that sends instructions under host computer produces field sync signal, concrete, if on image partially, illustrate that data are exported in advance with behavior unit, user can send instructions and delay a line reading first trip data from host computer, if image is still gone up partially, then continues to delay a line and reads first trip data, or send instructions under host computer field sync signal shift to an earlier date a line produce, until image is placed in the middle.Execute this step, perform step S43.
Step S43 judges that whether image is partially lower: in this step, judges that whether image is lower partially, if the result judged is yes, then performs step S45; Otherwise, perform step S44.
Step S44 keeps the current location of image in video display apparatus: if the judged result of above-mentioned steps S43 is no, then perform this step.In this step, keep the current location of image in video display apparatus.
Send instructions under step S45 host computer in advance a line or multirow read line data, or send instructions under host computer and delay a line and produce field sync signal: if the judged result of above-mentioned steps S43 is yes, then perform this step.In this step, if under image partially, illustrate that data are delayed output with behavior unit, user can send instructions and shift to an earlier date a line reading first trip data from host computer, if image is still partially lower, then continue in advance a line and read first trip data, or send instructions under host computer and field sync signal is delayed a line produce, until image is placed in the middle.The inclined screen problem that the image that the invention solves VGA transmission often occurs, obviously improves video tastes and the satisfaction of user.
For 1920x1080p@59.94/60Hz resolution, the sequential chart of its every frame as shown in Figure 5.In Fig. 5, every frame comprises 45 blank lines, 1080 effective video data lines.Field sync signal vsync continues to set high level between the 5th departure date at the 1st row, and FPGA can move its position.To the 1121st row from the 42nd row, amounting to 1080 row, is effective row, effectively the payload of data enable signal data enable be namely the part of high level be this line in row.To the 41st row from the 1st row, and the 1122nd row is to the 1125th row, amounts to 45 row, is blank lines and inactive line, and black-out intervals, FPGA does not carry out data sampling.FPGA is inner can adjust the size of these parameters when structure exports data, to improve the problem of image up/down skew.
Fig. 6 be in the present embodiment image left avertence and upper inclined time the schematic diagram that compensates, demonstrate in Fig. 4 when image left avertence and upper inclined time, by method of the present invention, N is delayed (here to each row of data, N is positive integer) individual pixel reading, carry out the fine setting of N according to display effect, solve the problem of image left avertence; The capable reading of N is delayed to every frame data, carries out the fine setting of N according to display effect, solve problem inclined on image.The side-play amount relevant to VGA chip, solves by adjusting the position of field sync signal and line synchronizing signal.
The present embodiment also relates to a kind of device realizing the above-mentioned video image compensation method based on FPGA, and its structural representation as shown in Figure 7.In the present embodiment, outside FPGA, hang with DDR3 memory.In Fig. 7, this device comprises storage control unit 1, horizontal-shift judging unit 2 and vertical shift judging unit 3; Wherein, storage control unit 1 is for being stored in DDR3 memory frame by frame by image; Horizontal-shift judging unit 2 is for judging whether image offsets in the horizontal direction, and in this way, send instructions under host computer the reading time of adjustment row data or the generation time of adjustment line synchronizing signal; Otherwise, judge whether image offsets in vertical direction; Vertical shift judging unit 3 is for judging whether image offsets in vertical direction, and in this way, send instructions under host computer the reading time of adjustment first trip data or the generation time of adjustment field sync signal; Otherwise, keep the current location of image in video display apparatus.Due to need not special chip be used, thus its can promote the video tastes of user, adjustable range does not limit, need not use special chip, reduce the complexity of exploitation implementation procedure, improve the stability of system, reduce costs.
In the present embodiment, horizontal-shift judging unit 2 comprises left avertence judge module 21 and right avertence judge module 22 further; Wherein, left avertence judge module 21, for judging image whether left avertence, in this way, sends instructions under host computer and delays a bat or clap read line data more, or sends instructions under host computer and one clap and produce line synchronizing signal in advance; Otherwise, judge image whether right avertence; Right avertence judge module 22, for judging image whether right avertence, in this way, sends instructions under host computer and one claps or clap read line data more in advance, or sends instructions under host computer and delay a bat and produce described line synchronizing signal; Otherwise, judge whether image offsets in vertical direction.In the present embodiment, a bat is exactly a pixel.
In the present embodiment, vertical shift judging unit 3 comprises inclined judge module 31 and lower inclined judge module 32 further; Wherein, upper inclined judge module 31, for judging whether image is gone up partially, in this way, sends instructions and delay a line or multirow reading first trip data, or a line in advance that sends instructions under host computer produces field sync signal under host computer; Otherwise, judge that whether image is partially lower; Lower inclined judge module 32 is for judging that whether image is partially lower, and in this way, send instructions under host computer a line or multirow in advance read first trip data, or sends instructions under host computer and delay a line and produce field sync signal; Otherwise, keep the current location of image in video display apparatus.
In a word, in the present embodiment, when skew occurs image, if move image on thinking, just capable beginning of N reads first trip data in advance; If want to move down image, just delay capable beginning of N and read first trip data; If want the image that moves to left, just N number of pixel starts to read the pixel data of often going in advance; If want the image that moves to right, just delay N number of pixel and start to read the pixel data of often going.In addition, by line synchronizing signal hsync and field sync signal vsync in mobile video signal, VGA output special chip can also be compensated and deals with the image shift caused improperly.The present invention supports the real-time adjustment of picture upper and lower, left and right four dimensions, and its adjustable range does not limit; Utilize FPGA to realize, facilitate the consistency of the system integration and products scheme, decrease the Job engagement that secondary development brings; Need not special chip be used, reduce the complexity of system, improve the stability of product.Avoid payment software copyright fee or license expense, reduce exploitation and the Material Cost of product.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (8)
1. based on a video image compensation method of FPGA, it is characterized in that, hang with DDR3 memory outside described FPGA, described method comprises the steps:
A) image is stored in frame by frame in described DDR3 memory;
B) judge whether described image offsets in the horizontal direction, in this way, send instructions under host computer the reading time of adjustment row data or the generation time of adjustment line synchronizing signal, performs step C); Otherwise, perform step C);
C) judge whether described image offsets in vertical direction, in this way, send instructions under described host computer the reading time of adjustment first trip data or the generation time of adjustment field sync signal; Otherwise, keep the current location of described image in video display apparatus.
2. the video image compensation method based on FPGA according to claim 1, is characterized in that, described step B) comprise further:
B1) judge image whether left avertence, in this way, send instructions under host computer and delay a bat or clap read line data more, or send instructions under described host computer and one clap and produce line synchronizing signal in advance, perform step B2); Otherwise, perform step B2);
B2) judge described image whether right avertence, in this way, send instructions under described host computer one to clap or clap reads described row data morely, or send instructions under described host computer in advance and delay a bat and produce described line synchronizing signal, perform step C); Otherwise, perform step C).
3. the video image compensation method based on FPGA according to claim 2, is characterized in that, described step C) comprise further:
C1) judge whether image is gone up partially, in this way, send instructions under host computer and delay a line or multirow reading first trip data, or a line in advance that sends instructions under described host computer produces described field sync signal, performs step C2); Otherwise, perform step C2);
C2) judge that described image is whether partially lower, in this way, send instructions under described host computer a line or multirow in advance read described first trip data, or send instructions under described host computer and delay a line and produce described field sync signal; Otherwise, keep the current location of described image in video display apparatus.
4. the video image compensation method based on FPGA according to claim 3, is characterized in that, a described bat is exactly a pixel.
5. realize as claimed in claim 1 based on a device for the video image compensation method of FPGA, it is characterized in that, hang with DDR3 memory outside described FPGA, described device comprises:
Memory cell: for image being stored in frame by frame in described DDR3 memory;
Horizontal-shift judging unit: for judging whether described image offsets in the horizontal direction, in this way, send instructions under host computer the reading time of adjustment row data or the generation time of adjustment line synchronizing signal; Otherwise, judge whether described image offsets in vertical direction;
Vertical shift judging unit: for judging whether described image offsets in vertical direction, in this way, send instructions under described host computer the reading time of adjustment first trip data or the generation time of adjustment field sync signal; Otherwise, keep the current location of described image in video display apparatus.
6. device according to claim 5, is characterized in that, described horizontal-shift judging unit comprises further:
Left avertence judge module: for judging image whether left avertence, in this way, sends instructions under host computer and delays a bat or clap read line data more, or sends instructions under described host computer and one clap and produce line synchronizing signal in advance; Otherwise, judge described image whether right avertence;
Right avertence judge module: for judging described image whether right avertence, in this way, sends instructions under described host computer one to clap or clap reads described row data morely, or send instructions under described host computer in advance and delays a bat and produce described line synchronizing signal; Otherwise, judge whether described image offsets in vertical direction.
7. device according to claim 6, is characterized in that, described vertical shift judging unit comprises further:
Upper inclined judge module: for judging whether image is gone up partially, in this way, sends instructions and delay a line or multirow reading first trip data, or a line in advance that sends instructions under described host computer produces described field sync signal under host computer; Otherwise, judge that whether described image is partially lower;
Lower inclined judge module: for judging that whether described image is partially lower, in this way, send instructions under described host computer a line or multirow in advance read described first trip data, or send instructions under described host computer and delay a line and produce described field sync signal; Otherwise, keep the current location of described image in video display apparatus.
8. device according to claim 7, is characterized in that, a described bat is exactly a pixel.
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| 张永祥等: "视频图像运动补偿系统的设计与实现", 《液晶与显示》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106488163A (en) * | 2015-08-28 | 2017-03-08 | Arm有限公司 | The method and apparatus of adjustment data array |
| CN106488163B (en) * | 2015-08-28 | 2020-10-09 | Arm有限公司 | Method for adjusting data array and adjusting device |
| CN105574881A (en) * | 2015-12-29 | 2016-05-11 | 合肥宏晶微电子科技股份有限公司 | Vga boundary detection technology |
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