CN104601123A - Low-power consumption three-level operational amplifier for driving large-load capacitor - Google Patents

Abstract

The invention discloses a three-stage operational amplifier with low power consumption for driving a large load capacitance. The amplifier consists of first to eighth PMOS transistors M ₁₀ , M ₁₁ , M ₁₂ , M ₁₇ , M ₁₈ , M ₂₁ , M ₂₄ , M ₃₁ , and the first to seventh NMOS transistors M ₁₃ , M ₁₄ , M ₁₅ , M ₁₆ , M ₂₂ , M ₂₃ , and M ₃₀ are 15 MOS transistors in total, and two capacitors are the first compensation capacitor Cm and the second capacitor Two compensating capacitors Ca and one resistor Ra are formed. Compared with the prior art, the present invention can drive large load capacitance (hundreds of pF) under the condition of low voltage and low power consumption (μW), and has large gain-bandwidth product and better slew rate.

Description

Low Power Three-Stage Op Amp for Driving Large Load Capacitance

technical field

The invention relates to a low-voltage low-power multistage operational amplifier, in particular to a low-voltage low-power multistage operational amplifier.

Background technique

The technical research of low-voltage and low-power multi-stage operational amplifiers has always been a very active research field for low-power circuits. The compensation technology of multi-stage operational amplifiers can be widely used in portable electronic devices, such as mobile phone batteries, notebook batteries, LDOs, etc. . In recent years, due to the inherent limitations of the well-known multi-stage compensation method for three-stage operational amplifiers—Nested Miller Compensation (NMC), namely: the compensation technology has a right-half-plane zero point and two large compensation capacitors; these deficiencies greatly It limits its application in low-voltage and low-power multi-stage operational amplifier circuits. Subsequently, many compensation methods for multi-stage operational amplifiers emerged to improve the NMC technology. They greatly improved the stability of the operational amplifier under the condition of low power consumption, and also expanded the gain-bandwidth product and slew rate. However, the above technologies also have some shortcomings. For example, some compensation capacitors are proportional to the load capacitance, resulting in an increase in the chip area, and the final manufacturing cost of the circuit is also increased; so the later compensation technology began to make the area of the compensation capacitor proportional to the load capacitance. The geometric mean, which greatly saves the area of the chip.

Contents of the invention

In order to overcome the above prior art, the present invention proposes a low-power three-stage operational amplifier for driving large load capacitance, and proposes active feedback and RC series compensation (AFMCRC) technology, which is connected in series at the second-stage output terminal through RC Pole-ZeroDoublets are formed by introducing zero points to improve the large-signal and small-signal performance of the operational amplifier - gain-bandwidth product and transient response, while further reducing power consumption, striving to obtain better gain bandwidth under low power consumption conditions products and better transient response.

The present invention proposes a low-power three-stage operational amplifier for driving large load capacitance, the amplifier consists of first to eighth PMOS transistors M ₁₀ , M ₁₁ , M ₁₂ , M ₁₇ , M ₁₈ , M ₂₁ , M ₂₄ , M ₃₁ , and the first to seventh NMOS transistors M ₁₃ , M ₁₄ , M ₁₅ , M ₁₆ , M ₂₂ , M ₂₃ , and M ₃₀ are 15 MOS transistors in total, and two capacitors are the first compensation capacitor Cm and The second compensation capacitor Ca and a resistor Ra are formed; where:

The sources of the first, fourth to seventh PMOS transistors M ₁₀ , M ₁₇ , M ₁₈ , M ₂₁ , M ₂₄ , and M ₃₁ are commonly connected to the power supply V _DD ; except for the second to third PMOS transistors M ₁₁ , M ₁₂ The substrate terminals of the first, fourth to seventh PMOS transistors M ₁₀ , M ₁₇ , M ₁₈ , M ₂₁ , M ₂₄ , and M ₃₁ are connected to the power supply V _DD ; 2. The sources of the fifth to seventh NMOS transistors M ₁₃ , M ₁₄ , M ₂₂ , M ₂₃ , and M ₃₀ are commonly grounded to GND; the first to seventh NMOS transistors M ₁₃ , M ₁₄ , M ₁₅ , M ₁₆ , M ₂₂ , The substrate ends of M ₂₃ and M ₃₀ are grounded to GND;

The gate of the first PMOS transistor M ₁₀ is connected to the first bias voltage V _b1 , and the drain is connected to the sources of the second to third PMOS transistors M ₁₁ and M ₁₂ ; the gates of the first to second PMOS transistors M ₁₁ and M ₁₂ The gates are respectively connected to the input voltage V _in- and V _in+ terminals; the drains of the first PMOS transistor M ₁₁ and the first NMOS transistor M ₁₃ are jointly connected to the source of the third NMOS transistor M 15 , the third PMOS transistor M ₁₂ , the first NMOS transistor M ₁₅ The drains of the two NMOS transistors M ₁₄ are commonly connected to the source of M ₁₆ ; the gates of the first to second NMOS transistors M ₁₃ and M ₁₄ are commonly connected to the second bias voltage V _b2 , and the third to fourth NMOS transistors M ₁₅ The gates of M _{16 and} M 16 are connected to the third bias voltage V _b3 ; the gates of the sixth PMOS transistor M ₂₁ and the eighth PMOS transistor M ₃₁ are connected to the drains of the fourth NMOS transistor M ₁₆ and the fifth PMOS transistor M ₁₈ ; The gates of the fourth to fifth PMOS transistors M ₁₇ and M ₁₈ are connected to the drains of the fourth PMOS transistor M ₁₇ and the third NMOS transistor M ₁₅ ; the source of the fourth NMOS transistor M ₁₆ is connected to the first compensation capacitor Cm The left end of the first compensation capacitor Cm is connected to the output terminal V _OUT on the right end;

The drains of the sixth PMOS transistor M ₂₁ and the fifth NMOS transistor M ₂₂ are jointly connected to the gates of the fifth to sixth NMOS transistors M ₂₂ and M ₂₃ ; the drains of the sixth NMOS transistor M ₂₃ and the seventh PMOS transistor M ₂₄ Commonly connected to the gate of M ₃₀ ; the gate of the seventh PMOS transistor M ₂₄ is connected to the fourth bias voltage V _b4 ; the drains of the seventh NMOS transistor M ₃₀ and the eighth PMOS transistor M ₃₁ are commonly connected to the output terminal V _OUT ; the resistor Ra One end is commonly connected to the gate of the seventh NMOS transistor _M30 ; the other end of the resistor Ra is connected to one end of the capacitor Ca, and the other end of the capacitor Ca is grounded to GND; the external load capacitor C _L is connected to V _OUT .

Compared with the prior art, the present invention can drive a large load capacitance (hundreds of pF) under low voltage and low power consumption (μW) conditions, while having a large gain-bandwidth product and better slew rate .

Description of drawings

Figure 1. The schematic block diagram of the three-stage operational amplifier; where: 1stage is the folded cascode differential input stage; 2stage is the gain stage; 3stage is the push-pull output stage;

Figure 2 is the open-loop frequency response curve of a three-stage operational amplifier driving load capacitances of 500pF and 2nF;

Figure 3 is the transient response curve of three-stage operational amplifiers driving load capacitances of 500pF and 2nF.

Detailed ways

The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments, but the implementation scope of the present invention is not limited thereto.

This multi-stage operational amplifier consists of 15 MOS transistors (PMOS: M ₁₀ , M ₁₁ , M ₁₂ , M ₁₇ , M ₁₈ , M ₂₁ , M ₂₄ and M ₃₁ ; NMOS: M ₁₃ , M ₁₄ , M ₁₅ , M ₁₆ , M ₂₂ , M ₂₃ and M ₃₀ ), two capacitors, namely the first compensation capacitor Cm and the second compensation capacitor Ca, and one resistor Ra. Connection mode: the sources of M ₁₀ , M ₁₇ , M ₁₈ , M ₂₁ , M ₂₄ and M ₃₁ are commonly connected to the power supply V _DD ; except for the substrate terminals of M ₁₁ and M ₁₂ connected to the source, M ₁₀ , M ₁₇ , M ₁₈ , M ₂₁ , M ₂₄ , and M ₃₁ are connected to the power supply V _DD at the substrate termination. The sources of M ₁₃ , M ₁₄ , M ₂₂ , M ₂₃ and M ₃₀ are commonly grounded to GND; the substrate terminals of M ₁₃ , M ₁₄ , M ₁₅ , M ₁₆ , M ₂₂ , M ₂₃ and M ₃₀ are grounded to GND.

The gate of M ₁₀ is connected to the bias voltage V _b1 , the drain of M ₁₀ is connected to the sources of M ₁₁ and M ₁₂ ; the gates of M ₁₁ and M ₁₂ are respectively connected to the input voltage V _in- and V _in+ terminals; M ₁₁ and M The drain of _M13 is connected to the source of _M15 , the drains of _M12 and _M14 are connected to the source of _M16 ; the gates of _M13 and _M14 are connected to the bias voltage V _b2 , and _M15 and _M16 The gates are connected to the bias voltage V _b3 ; the gates of M ₂₁ and M ₃₁ are connected to the drains of M ₁₆ and M ₁₈ ; the gates of M ₁₇ and M ₁₈ are connected to the drains of M ₁₇ and M ₁₅ ; M ₁₆ The source of the first compensation capacitor Cm is connected to the left end of the first compensation capacitor Cm, and the right end of the first compensation capacitor Cm is connected to the output terminal V _OUT .

The drains of M ₂₁ and M ₂₂ are connected to the gates of M ₂₂ and M ₂₃ ; the drains of M ₂₃ and M ₂₄ are connected to the gate of M ₃₀ ; the gate of M ₂₄ is connected to the bias voltage V _b4 ; M ₃₀ and M The drains of ₃₁ are commonly connected to the output terminal V _OUT ; one end of the resistor Ra is commonly connected to the gate of M ₃₀ ; the other end of the resistor Ra is connected to one end of the capacitor Ca, and the other end of the capacitor Ca is grounded to GND; the external load capacitor C _L is connected to V _OUT .

The following are the AC analysis and transient analysis simulation parameters and results when the Hspice simulator is used in the SMIC 65nm CMOS process to drive a load capacitance of C _L =500pF. It can be seen that: the gain-bandwidth product GBW=5.98MHz, the phase margin PM=56.4°, the slew rate SR=0.54V/μs, and the power consumption is 24μW. In addition, the first compensation capacitor Cm is reduced, that is, the area of the chip is reduced, which is very beneficial for low-voltage and low-power consumption circuit applications. Therefore, this multi-stage operational amplifier is suitable for high-speed applications with low voltage and low power consumption.

Under the condition of low voltage and low power consumption (μW), the three-stage operational amplifier can drive large load capacitance (hundreds of pF), and has large gain-bandwidth product and better slew rate. To verify its effect, set the The large load capacitance is 500pF. The open-loop frequency response curve (Figure 2) and transient response curve (Figure 3) are obtained through AC simulation and transient simulation. The simulation parameters and results are shown in Table 1 and Table 2.

Table 1 Simulation parameter C _L =500pF

Table 2. Simulation results C _L =500pF

Parameter This work Gain(dB) 114 PM (deg.) 56.4 GBW(MHz) 5.98 SR+/-(V/μs) 0.54/0.49 Power(mW) 0.024 Supply(V) 1.2 C _L (pF) 500

*Typical valueTT Corner, 25℃.

Claims (1)

1. A low-power three-stage operational amplifier for driving large load capacitance, characterized in that, the amplifier consists of the first to eighth PMOS transistors M ₁₀ , M ₁₁ , M ₁₂ , M ₁₇ , M ₁₈ , M ₂₁ , M ₂₄ , M ₃₁ and the first to seventh NMOS transistors M ₁₃ , M ₁₄ , M ₁₅ , M ₁₆ , M ₂₂ , M ₂₃ , M ₃₀ , a total of 15 MOS transistors, and two capacitors, namely the first compensation capacitor Cm and the second compensation capacitor Ca, and a resistor Ra; wherein: The sources of the first, fourth to seventh PMOS transistors M ₁₀ , M ₁₇ , M ₁₈ , M ₂₁ , M ₂₄ , and M ₃₁ are commonly connected to the power supply V _DD ; except for the second to third PMOS transistors M ₁₁ , M ₁₂ The substrate terminals of the first, fourth to seventh PMOS transistors M ₁₀ , M ₁₇ , M ₁₈ , M ₂₁ , M ₂₄ , and M ₃₁ are connected to the power supply V _DD ; 2. The sources of the fifth to seventh NMOS transistors M ₁₃ , M ₁₄ , M ₂₂ , M ₂₃ , and M ₃₀ are commonly grounded to GND; the first to seventh NMOS transistors M ₁₃ , M ₁₄ , M ₁₅ , M ₁₆ , M ₂₂ , The substrate ends of M ₂₃ and M ₃₀ are grounded to GND; The gate of the first PMOS transistor M ₁₀ is connected to the first bias voltage V _b1 , and the drain is connected to the sources of the second to third PMOS transistors M ₁₁ and M ₁₂ ; the gates of the first to second PMOS transistors M ₁₁ and M ₁₂ The gates are respectively connected to the input voltage V _in- and V _in+ terminals; the drains of the first PMOS transistor M ₁₁ and the first NMOS transistor M ₁₃ are jointly connected to the source of the third NMOS transistor M 15 , the third PMOS transistor M ₁₂ , the first NMOS transistor M ₁₅ The drains of the two NMOS transistors M ₁₄ are commonly connected to the source of M ₁₆ ; the gates of the first to second NMOS transistors M ₁₃ and M ₁₄ are commonly connected to the second bias voltage V _b2 , and the third to fourth NMOS transistors M ₁₅ The gates of M _{16 and} M 16 are connected to the third bias voltage V _b3 ; the gates of the sixth PMOS transistor M ₂₁ and the eighth PMOS transistor M ₃₁ are connected to the drains of the fourth NMOS transistor M ₁₆ and the fifth PMOS transistor M ₁₈ ; The gates of the fourth to fifth PMOS transistors M ₁₇ and M ₁₈ are connected to the drains of the fourth PMOS transistor M ₁₇ and the third NMOS transistor M ₁₅ ; the source of the fourth NMOS transistor M ₁₆ is connected to the first compensation capacitor Cm The left end of the first compensation capacitor Cm is connected to the output terminal V _OUT on the right end; The drains of the sixth PMOS transistor M ₂₁ and the fifth NMOS transistor M ₂₂ are jointly connected to the gates of the fifth to sixth NMOS transistors M ₂₂ and M ₂₃ ; the drains of the sixth NMOS transistor M ₂₃ and the seventh PMOS transistor M ₂₄ Commonly connected to the gate of M ₃₀ ; the gate of the seventh PMOS transistor M ₂₄ is connected to the fourth bias voltage V _b4 ; the drains of the seventh NMOS transistor M ₃₀ and the eighth PMOS transistor M ₃₁ are commonly connected to the output terminal V _OUT ; the resistor Ra One end is commonly connected to the gate of the seventh NMOS transistor _M30 ; the other end of the resistor Ra is connected to one end of the second compensation capacitor Ca, and the other end of the second compensation capacitor Ca is grounded to GND; the external load capacitor C _L is connected to V _OUT .