CN1046040C - Memory direct access structure matching the number of bus bits - Google Patents

Abstract

A direct access structure of memory matched with bus digit number is used in computer system and is connected with microprocessor unit, memory device and input/output device by bus, and is characterized by that it uses a memory direct access controller with first digit number to receive request signal and produce command signal according to the basic address and basic count of a data to make the data be directly transferred between memory device and input/output device by bus with second digit number, in which the first digit number is equal to the second digit number.

Description

Memory direct access structure matching the number of bus bits

The present invention relates to a memory direct storage structure of a microcomputer (microcomputer) system, in particular to a memory direct access (DMA, Direct Memory Access) structure matching the bus number.

In microcomputer systems, direct memory access (DMA) is an important structure. It takes over the data and address bus originally controlled by the microprocessor (microprocessor) in an instant, so that peripheral equipment, such as disk drives and other input/output devices, can directly exchange and transmit data with memory devices via the bus, improving Data flow efficiency.

Please refer to FIG. 1, which is a schematic block diagram depicting a DMA structure in a microcomputer system. When the control signal line 8 makes the microprocessor unit (microprocessor unit) 1 hand over control of the bus 6, 7, DMA starts. At this time, the DMA control unit (DMA control unit) 3 controls the operation: it accepts the request signal (request) on the one hand, and arranges an appropriate data transmission channel (channel) for arbitration, and generates information about the data to be transmitted in the memory device 2 on the one hand. Related information such as address and number of bytes are used to transmit data directly between the memory device 2 and the input/output device 5 via the buses 6 and 7 .

However, the traditional DMA structure utilizes a lower number of digits, a DMA controller, and a b-bit page register (page register) to jointly form a so-called n-bit DMA control unit with a larger number of digits, wherein n=a+b.

In a 486 personal computer system, according to the above DMA structure, in order to provide 32-bit DMA, the following actions must be performed first:

1. Plan the base address (base address) register of a bit;

2. Plan the page address (page address) register of b bits;

3. Plan the basic count (base count) register of a bit;

4. planning control register;

5. Clear the mask register; and

6. Issue a DMA request (request).

Among them, steps 1 and 2 are used as the basic address of n bits to determine the address where the data starts to be transmitted; step 3 is to determine how many bytes of data to be transmitted, step 4 is to determine its control mode, and steps 5 and 6 are to start DMA action.

According to the above DMA structure, because the address register is only 8 bits, a 32-bit DMA needs to plan 6 registers in total, including 2 basic address registers, 2 page registers and 2 basic count registers. At the same time, when it handles the data address mode, it is limited by the page register, which can only provide two kinds of 8-bit and 16-bit, which cannot match the number of bits of the bus, so that it cannot handle the address alignment of double word (double word) ( alignment).

With the gradual increase in the ability of the microprocessor to process data, the number of data calculation bits it has continues to increase, and the demand for a large amount of data exchange environment on which today's multimedia systems rely, all make the above-mentioned known DMA structure gradually become embarrassing. . Its complex planning registers, inflexible address modes, and limited address alignment functions cannot meet the needs.

The main purpose of the present invention is to propose a memory direct access structure that matches the number of bits of the bus, which can increase the number of bits of the basic address register, reduce the number of times of register planning, and improve efficiency.

Another object of the present invention is to propose a memory direct access structure that matches the number of bits of the bus, which can increase address modes, can handle alignment of addresses with higher numbers of bits, and enhances functions.

The present invention is a memory direct access structure matched with the number of bits of the bus. The first technical scheme of the present invention uses a memory direct access controller with the first number of digits, based on a data base The address and the basic count receive the request signal and generate the command signal so that the data is directly transmitted between the memory device and the input/output device through the bus with the second digit. Among them, the first digit is equivalent to the second digit. The above-mentioned memory direct access structure can greatly improve the transmission performance with double-word address alignment capability, and accelerate the memory direct access operation with the least number of register planning times. It includes:

a base address register, having said first bit, coupled to the bus to store the base address of the data;

a base count memory, having said first number of bits, coupled to the bus to store a base count of data;

A memory direct access controller, having said first digit, by means of the basic address of the data provided by said basic address register and the basic count of data provided by said basic count register, in cooperation with input/output devices and storage The request and command signal of the memory device executes the memory direct access control action.

The second technical solution of the present invention includes a first alignment controller, a second alignment controller, a first multiplexer, a second multiplexer, a basic address register, and a basic counting register 1. A memory direct access controller, using the register direct access controller with the first number of digits to enter the first alignment controller through the first or second alignment controller according to a slave bus respectively. Or the number of bytes of the first type of data of the second multiplexer, address, page value and a basic address and basic count of the second type of data directly entering the first or second multiplexer by the bus collection , and accept the request signal, generate a command signal, so that the input/output device can directly exchange data with the memory device via the bus with the second number of digits, the second number of digits is the same as the first number of digits Quite; Wherein, described storage direct access control structure comprises:

A first alignment controller, coupled to the bus, for obtaining the address and page value of the first type of data, sorting and aligning to form a basic address;

A second alignment controller, coupled to the bus, used to obtain the number of bytes and page values of the first type of data, sort and align to form a basic count;

A first multiplexer, having two selection input terminals, respectively coupled to the bus to obtain the basic address of the second type of data, and coupled to the first alignment controller to obtain the basic address of the first type of data , and receiving a start signal control, providing an output of one of the basic address of the first type of data or the basic address of the second type of data;

a second multiplexer, having two selection input terminals, respectively coupled to the bus to obtain the basic count of the second type of data, and coupled to the second alignment controller to obtain the basic count of the first type of data , and is controlled by a start signal, and provides an output of one of the basic count of the first type of data or the basic count of the second type of data;

A basic address register, having the first number of digits, coupled to the first multiplexer, for storing the basic address;

a base count register, having said first number of bits, coupled to said second multiplexer, for storing base counts; and

A memory direct access controller, having the first digit, coupling the basic address register and the basic count register, reading the basic address and the basic count, and according to the basic address and the basic count, cooperate with the input/ The request and command signal of the output device and the memory device executes the memory direct access control action; the memory direct access controller generates an activation signal to control the first alignment controller, the a second alignment controller, the first multiplexer, and the second multiplexer, for

(1) When transmitting the first type of data, start the actions of the first alignment controller and the second alignment controller, and close the first multiplexer and the second multiplexer a channel coupled to the bus, so that the base address and base count of the first type of data are passed to the base address register and the base count register; and

(2) When transmitting the second type of data, stop the actions of the first alignment controller and the second alignment controller, close the first multiplexer to couple the first alignment controller The channel of the second multiplexer coupled with the second alignment controller is closed, so that the basic address and basic count of the second type of data can be directly transmitted to the register through the bus.

In order to further illustrate the purpose and characteristics of the present invention, a preferred embodiment is cited in this paper, and in conjunction with the accompanying drawings, the detailed description is as follows:

Brief description of the drawings:

Fig. 1 is a schematic block diagram showing that the memory direct access control structure is located in a microcomputer system;

Fig. 2 is a schematic block diagram of a preferred embodiment of the present invention;

Fig. 3 is a schematic block diagram of the internal block of the memory direct access controller in Fig. 2;

FIG. 4 is a schematic diagram of an internal block of the alignment controller in FIG. 2 .

At first, with reference to Fig. 2, the memory direct access structure of the present invention is to be connected with the bus 6,7 with the second number of digits by the DMA control structure 3 with the first number of digits, to provide memory device and I/O devices exchange data directly, where the first digit is equivalent to the second digit.

Include in above-mentioned DMA control unit 3:

The first alignment controller 15 obtains the address and page value of the data from the buses 6 and 7, uses a register sequence group, sorts and aligns them to become the basic address, and outputs it later.

The second alignment controller 16 also obtains the byte number and page value of data from the bus 6, 7 to form a basic count, and its operation will be further described below.

The first multiplexer 13 has two selection inputs connected to the buses 6, 7 and the aforementioned first alignment controller respectively. When the system transmits DMA information in the well-known page register mode, the multiplexer obtains the basic address through the first alignment controller 15 of the previous stage, otherwise, directly obtains the basic address from the bus 6,7. The second multiplexer 14 also operates as the first multiplexer 13 to obtain the base count. Please note that the settings of the aforementioned first alignment controller 15 , second alignment controller 16 , first multiplexer 13 , and second multiplexer are all for compatibility with known systems.

The basic address register 11 has the first number of digits, accepts and stores the basic address provided by the first multiplexer 13, which is the address at which data transmission starts.

The basic count register 12 has a first number of digits, which is stored by receiving the basic count provided by the second multiplexer 14, which is the number of bytes of data to be transmitted.

And memory direct access controller 10, has the first digit, does basic address data access action according to basic address register 11, does basic counting data access action according to basic counting register 12, cooperates memory device and input /Output the request of the device to perform the action of controlling the DMA.

In order to understand the action of the direct memory access controller, please refer to FIG. 3 , which is composed of several mode registers 22 , an arbiter 24 , a controller 26 and an address generator 28 . The mode register 22 exchanges data with the aforementioned basic address register 11 and basic count register 12 to generate various control modes, such as address mode and other related read/write actions, so as to plan the DMA action mode. The arbiter 24 arbitrates the service request 20 of the DMA according to the aforementioned mode, and determines the priority, so as to maintain the order of the data transmission channel. The controller 26 sends a control signal to control the input/output device 4 and the memory device 2 to complete their respective necessary actions, and controls the aforementioned first alignment controller, second alignment controller, The first multiplexer and the second multiplexer are used to determine whether to perform DMA operation according to the data address mode of the present invention or to operate compatible with the known DMA structure. The address generator 28 generates the reading position of the required memory device according to the address control mode for reading and transmitting data.

The above-mentioned memory direct access controller must also control the number of transmission bits of the first and last data by the address generator 28, so that the address of each transmission must be located at the edge position of 2 ^m , wherein m is a natural number, And 2 ^m is less than or equal to the first digit, so as to meet the requirements of address alignment.

The compatibility requirement of knowing the starting position and quantity of the planned transmission data is processed in the alignment controllers 15 and 16 , please refer to FIG. 4 . After the alignment controllers 15 and 16 obtain data from the buses 6 and 7, they select appropriate registers to be placed in the register sequence group 34 by the address comparator 32 according to the instruction of the start signal of the DMA controller. In this way, the driver program (driver) originally applied to the traditional structure can be used in this structure without modification.

According to the above DMA structure, for example, in a 486 personal computer system, the first digit is 32 bits. When performing DMA operations, only two registers need to be planned, that is, a 32-bit basic address register and a 32-bit basic count register. , so the number of times the microprocessor plans the DMA control unit can be greatly reduced, and due to the aligned address, a full 32-bit address can be used at one time, without being limited to the page register of the traditional DMA structure. These advantages are even more important in the current situation where the local bus protocol (local bus protocol) is prevalent and the demand for multimedia systems is ardent.

Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims (5)

1. A memory direct access structure matching the number of bus bits, used in computer systems, connected to micro-processing units, memory devices and input and output devices through the bus, including a basic address register, a basic The counting register and a memory direct access controller are based on the memory direct access controller having the first digit, according to the basic address and basic count of a piece of data, receiving the request signal and generating the command signal, enables data to be directly transferred between a memory device and an input/output device via a bus having a second number of bits corresponding to said first number of bits; said memory direct access Control structures include: a base address register, having said first bit, coupled to the bus to store the base address of the data; a base count memory, having said first number of bits, coupled to the bus to store a base count of data; A memory direct access controller, having said first digit, by means of the basic address of the data provided by said basic address register and the basic count of data provided by said basic count register, in cooperation with input/output devices and storage The request and command signal of the memory device executes the memory direct access control action. 2. A memory direct access structure matching the bus number, comprising a first alignment controller, a second alignment controller, a first multiplexer, a second multiplexer, A basic address register, a basic counting register, and a memory direct access controller, with the memory direct access controller having the first digit, respectively according to a slave bus acquisition via the first or The second alignment controller enters the number of bytes of the first type of data of the first or second multiplexer, the address, the page value, and one collected by the bus and directly enters the first or second multiplexer The basic address and basic count of the second type of data, and accept the request signal, generate a command signal, so that the input/output device can directly exchange data with the memory device via the bus with the second number of digits, the first The two-digit number is equivalent to the first number; wherein, the storage direct access control structure includes: A first alignment controller, coupled to the bus, for obtaining the address and page value of the first type of data, sorting and aligning to form a basic address; A second alignment controller, coupled to the bus, used to obtain the number of bytes and page values of the first type of data, sort and align to form a basic count; A first multiplexer, having two selection input terminals, respectively coupled to the bus to obtain the basic address of the second type of data, and coupled to the first alignment controller to obtain the basic address of the first type of data , and receiving a start signal control, providing an output of one of the basic address of the first type of data or the basic address of the second type of data; a second multiplexer, having two selection input terminals, respectively coupled to the bus to obtain the basic count of the second type of data, and coupled to the second alignment controller to obtain the basic count of the first type of data , and is controlled by a start signal, and provides an output of one of the basic count of the first type of data or the basic count of the second type of data; A basic address register, having the first number of digits, coupled to the first multiplexer, for storing the basic address; a base count register, having said first number of bits, coupled to said second multiplexer, for storing base counts; and A memory direct access controller, having the first digit, coupling the basic address register and the basic count register, reading the basic address and the basic count, and according to the basic address and the basic count, cooperate with the input/ request and command signals of the output device and the memory device, and perform a memory direct access control action; the memory direct access controller generates an activation signal to control the first alignment controller, the a second alignment controller, the first multiplexer, and the second multiplexer, for (1) When transmitting the first type of data, start the actions of the first alignment controller and the second alignment controller, and close the first multiplexer and the second multiplexer a channel coupled to the bus, so that the base address and base count of the first type of data are passed to the base address register and the base count register; and (2) When transmitting the second type of data, stop the actions of the first alignment controller and the second alignment controller, close the first multiplexer to couple the first alignment controller The channel of the second multiplexer coupled with the second alignment controller is closed, so that the basic address and basic count of the second type of data can be directly transmitted to the register through the bus. 3. The alignment controller according to claim 2, wherein the first alignment comparator and the second alignment comparator respectively comprise: An address comparator, controlled by the start signal, generates a control signal according to the page value of the data; and A plurality of registers form a register sequence group, the number of registers is the first digit, and the address or the number of bytes of the appropriate register is selected according to the control signal of the address comparator to form a sequence of registers by sorting and aligning Base address or base count. 4. A memory direct access structure matching the number of bus bits as claimed in claim 1, 2 or 3, wherein said memory direct access controller comprises: At least one mode register, coupled to the basic address register and the basic count register, to plan the control mode of direct access to the memory, and send a mode control signal; An arbiter, accepting the control of the mode control signal, raising a confirmation signal according to the arbitration request signal, and maintaining the order of data transmission according to the priority relationship; A controller is controlled by said mode control signal and generates a command signal to control the input/output device and the memory device; and An address generator is controlled by the mode control signal to generate data addresses. 5. A memory direct access structure matching the number of bus bits as claimed in claim 4, wherein said memory direct access controller also controls the first and last data transmission bit groups Number, so that the address of each transmission can be located at the edge of 2 ^m , where m is a natural number, and 2 ^m is less than or equal to the first digit.

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