CN104467909B - A kind of transmission circuit of configurable pci bus based on FPGA technology - Google Patents
A kind of transmission circuit of configurable pci bus based on FPGA technology Download PDFInfo
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- CN104467909B CN104467909B CN201410807931.2A CN201410807931A CN104467909B CN 104467909 B CN104467909 B CN 104467909B CN 201410807931 A CN201410807931 A CN 201410807931A CN 104467909 B CN104467909 B CN 104467909B
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Abstract
The present invention relates to the transmission circuit of a kind of configurable pci bus based on FPGA technology.This circuit includes FPGA device, PCI top-level module is included inside FPGA device, PCI top-level module includes ALTERA PCI IP kernel, rear end match circuit, peripheral circuit control module and the memory circuitry control module of instantiation, and whole modules are encapsulated as an entirety by PCI top-level module.The function realized by special chip moves in FPGA device, saves board area, reduces cost；Portable strong, according to being actually needed of board, device and pin can be modified, and facilitate the extension of peripheral circuit and memorizer；Employing PLD realizes, simple in construction, and computing is rapid, and reliability is high.
Description
Technical field
The present invention relates to digital communication system, particularly to the transmission circuit of a kind of configurable pci bus based on FPGA technology.
Background technology
PCI is the abbreviation of Peripheral Component Interconnect (Peripheral Component Interconnect standard), and the main purpose formulating pci bus standard is the high-speed communication in order to realize peripheral equipment and processor.Pci bus slot is currently used widest interface, can extend various functional cards convenient for computer.Realize pci bus traditionally to transmit based on special chip, such as chip PCI9054 etc..This transmission means exists that chip area footprints is bigger, relatively costly, portable strong and the defect such as application more inconvenience.
Summary of the invention
The defect existed in view of prior art and deficiency, the present invention provides the transmission circuit of a kind of configurable pci bus based on FPGA technology.
The present invention adopts the technical scheme that: the transmission circuit of a kind of configurable pci bus based on FPGA technology, it is characterized in that: this transmission circuit includes FPGA device, PCI top-level module is included inside FPGA device, PCI top-level module includes ALTERA PCI IP kernel, rear end match circuit, peripheral circuit control module and the memory circuitry control module of instantiation, and wherein the ALTERA PCI IP kernel of instantiation is connected with rear end match circuit；Rear end match circuit is connected with peripheral circuit control module and memory circuitry control module respectively；The ALTERA PCI IP kernel of instantiation is connected with golden finger by pci bus；Peripheral circuit control module is connected with the peripheral circuit on board；Memory circuitry control module is connected with the peripheral memory on board；All module is encapsulated as an entirety by PCI top-level module.
Peripheral circuit control module of the present invention includes that LCDs controls submodule, toggle switch controls submodule, LED light controls submodule and temperature sensor controls submodule；LCDs control module, toggle switch control submodule, LED light controls submodule and is connected with the rear end match circuit in PCI top-level module respectively with temperature sensor control submodule, and PCI clock signal and reset signal in pci bus signal are respectively connected to LCDs control submodule, toggle switch controls submodule, LED light controls submodule and temperature sensor controls submodule.
The feature of the present invention and providing the benefit that: 1, the function that special chip realizes is moved in FPGA device, save board area, reduce cost.2, portable strong, according to being actually needed of board, device and pin can be modified, and facilitate the extension of peripheral circuit and memorizer；3, using PLD to realize, simple in construction, computing is rapid, and reliability is high.
Accompanying drawing explanation
Fig. 1 is integrated circuit theory diagram；
Fig. 2 is the PCI IP kernel module map after instantiation；
Fig. 3 is that in Fig. 1, rear end match circuit is schemed by finite state machine status transfer；
Fig. 4 is peripheral circuit module theory diagram；
Fig. 5 is memory circuitry control module theory diagram.
Detailed description of the invention
Below in conjunction with accompanying drawing, the invention will be further described:
As shown in Figure 1, the transmission circuit of the configurable pci bus of a kind of FPGA technology includes FPGA(FPGA) device, PCI top-level module is included inside FPGA device, PCI top-level module includes ALTERA PCI IP kernel, rear end match circuit, peripheral circuit control module and the memory circuitry control module of instantiation, and wherein the ALTERA PCI IP kernel of instantiation is connected with rear end match circuit；Rear end match circuit is connected with peripheral circuit control module and memory circuitry control module respectively；The ALTERA PCI IP kernel of instantiation is connected with golden finger by pci bus；Peripheral circuit control module is connected with the peripheral circuit on board；Memory circuitry control module is connected with the peripheral memory on board；All module is encapsulated as an entirety by PCI top-level module.
The ALTERA PCI IP kernel of instantiation has two parts of signals, pci bus holding wire is connected with the golden finger of board by the relevant I/O mouth of FPGA, as the medium with compunication, after pci bus signal is converted to local side bus signals by PCI IP kernel, it is connected with rear end match circuit.Rear end match circuit is by the interpretation to local bus signal, determine the working method of this communication transaction, and the sensing position of address space, when pointing to I/O space, rear module is by the holding wire transmission control command being connected with peripheral circuit control module and data, and carries out relevant action by the peripheral circuit on the I/O port Control card of FPGA；And the data that peripheral circuit is replied can be fed back to IP kernel by the 32 of local side bidirectional data signal line.When pointing to storage space, rear end match circuit carries out two-way communication by the extended menory in the holding wire transmission control command being connected with memory control module and data, with board.All above functional module is packaged with PCI top-level module.
As in figure 2 it is shown, the ALTERA PCI MegaCore of the present invention is an IP kernel meeting PCI specification, through strict timing optimization, parameter configuration can be carried out as requested, the mutual conversion being used between pci bus agreement and local side bus.According to FPGA master-slave role in pci bus and the data bit width of transmission, this IP kernel can support four kinds of patterns: pci_mt64, pci_t64, pci_mt32, pci_t32.This transmission circuit is to transmit 32 bit data between computer and PCI board card by pci interface, the driving generated by windriver and upper computer software carry out Control card work, operating frequency 33MHz, so IP kernel is set to 32 from pattern pci_t32, PCI agreement supports I/O space, storage space and three kinds of address spaces of configuration space, and configuration space comprises some intrinsic informations of device PCI, can arrange the value of related register in IP kernel arranges interface, arrange as follows, Device
ID=0x0082, Vendor ID=0x1172, Revision_ID=0x01, remaining keeps default setting.Arranging interface at base address register, BAR0 is set to storage space, capacity 128KB, BAR1 are set to I/O space, and capacity 16B, BAR2 ~ BAR5 do not use, and remaining keeps default setting, completes the configuration of IP kernel.
As shown in Figure 3, the rear end match circuit of the present invention is according to control command interpretation mode of operation, by to order interpretation with finite state machine by the way of realize, 6 kinds of mode of operations supported altogether by this rear end match circuit, it is respectively monocycle memorizer read mode, monocycle memorizer WriteMode, IO read mode, IO WriteMode, burst memory read mode and burst memory WriteMode, its read-write sequence flow process is: the original state of the finite state machine of rear end match circuit is idle condition idle, the 5th rising edge clock at pci_clk detects that local side signal lt_framen is pulled low, finite state machine starts action, jump to decoded state decode；According to the decoding result to local side control signal, finite state machine is operated the selection of pattern, when for reading transaction, finite state machine is according to result, three kinds of read states, respectively memorizer monocycle read states single_rd, memory burst read states burst_rd, IO read states io_rd is jumped directly at the 6th rising edge clock；When for write operation, to jump to write waiting state wait_1clk at the 6th rising edge clock, postpone a pci_clk clock cycle, at the 7th rising edge clock further according to decoding result, jump to corresponding three kinds of write state, respectively memorizer monocycle write state single_wr, memory burst write state burst_wr, IO write state io_wr；After memory burst write state, last address write operation state last_wr is jumped to according to timing requirements, after completing read-write operation, two waiting states are jumped to: local waiting state 1 local_wait1 and local waiting state 2 local_wait2 detects concerned control command in the two state according to timing requirements, when meeting the requirements, return to idle condition idle, complete this time once to read and write transaction.
As shown in Figure 4, the peripheral circuit control module of the present invention includes that LCDs controls submodule, toggle switch controls submodule, LED light controls submodule and temperature sensor controls submodule；LCDs control module, toggle switch control submodule, LED light controls submodule and is connected with the rear end match circuit in PCI top-level module respectively with temperature sensor control submodule, and PCI clock signal and reset signal in pci bus signal are respectively connected to LCDs control submodule, toggle switch controls submodule, LED light controls submodule and temperature sensor controls submodule.
The reset of each submodule and clock signal all use clock and the reset signal of pci bus, each submodule address is controlled by the l_adro of PCI local side bus, related command according to pci bus, rear end match circuit enters IO read-write state, read-write sequence is given in the match circuit of rear end, each submodule that peripheral circuit controls is under read-write sequence control, by the address of l_daro, receive the data from rear end match circuit and order, it is translated into the control signal of relevant sub-module, and the data that oneself state or needs collect are returned to rear end match circuit, upper computer software is finally returned back to by relevant treatment by back-end circuit.
As it is shown in figure 5, the memory circuitry control module of the present invention extends out SRAM on Control card, model is IS61LV25616.Its operation principle is similar with peripheral circuit control module, it resets and clock signal is also to be provided by pci bus, to keep synchronizing, related command according to pci bus, rear end match circuit enters memory read/write state, the various enable signals of the peripheral memory that the order that rear end match circuit transmits is converted on Control card by memory control module, the peripheral memory work on Control card；According to the sequential in the match circuit of rear end, on board, SRAM write enters data or reads number from board in SRAM.The read-write sequence of SRAM meets the timing requirements in chip datasheet, realizes with finite state machine.
Claims (1)
1. the transmission circuit of a configurable pci bus based on FPGA technology, it is characterized in that: this transmission circuit includes FPGA device, PCI top-level module is included inside FPGA device, PCI top-level module includes ALTERA PCI IP kernel, rear end match circuit, peripheral circuit control module and the memory circuitry control module of instantiation, and wherein the ALTERA PCI IP kernel of instantiation is connected with rear end match circuit；Rear end match circuit is connected with peripheral circuit control module and memory circuitry control module respectively；The ALTERA PCI IP kernel of instantiation is connected with golden finger by pci bus；Peripheral circuit control module is connected with the peripheral circuit on board；Memory circuitry control module is connected with the peripheral memory on board；All module is encapsulated as an entirety by PCI top-level module；
Described rear end match circuit is according to control command interpretation mode of operation, by to order interpretation with finite state machine by the way of realize, its read-write sequence flow process is: the original state of the finite state machine of rear end match circuit is idle condition idle, the 5th rising edge clock at pci_clk detects that local side signal lt_framen is pulled low, finite state machine starts action, jumps to decoded state decode；According to the decoding result to local side control signal, finite state machine is operated the selection of pattern, when for reading transaction, finite state machine is according to result, three kinds of read states, respectively memorizer monocycle read states single_rd, memory burst read states burst_rd, IO read states io_rd is jumped directly at the 6th rising edge clock；When for write operation, to jump to write waiting state wait_1clock at the 6th rising edge clock, postpone a pci_clk clock cycle, at the 7th rising edge clock further according to decoding result, jump to corresponding three kinds of write state, respectively memorizer monocycle write state single_wr, memory burst write state burst_wr, IO write state io_wr；After memory burst write state, last address write operation state last_wr is jumped to according to timing requirements, after completing read-write operation, two waiting states are jumped to: local waiting state 1 local_wait1 and local waiting state 2 local_wait2 detects concerned control command in the two state according to timing requirements, when meeting the requirements, return to idle condition idle, complete this time once to read and write transaction；
Described peripheral circuit control module includes that LCDs controls submodule, toggle switch controls submodule, LED light controls submodule and temperature sensor controls submodule；LCDs control module, toggle switch control submodule, LED light controls submodule and is connected with the rear end match circuit in PCI top-level module respectively with temperature sensor control submodule, and PCI clock signal and reset signal in pci bus signal are respectively connected to LCDs control submodule, toggle switch controls submodule, LED light controls submodule and temperature sensor controls submodule.
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| CN201410807931.2A CN104467909B (en) | 2014-12-23 | 2014-12-23 | A kind of transmission circuit of configurable pci bus based on FPGA technology |
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| CN104467909B true CN104467909B (en) | 2016-11-30 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110196824B (en) * | 2018-05-31 | 2022-12-09 | 腾讯科技（深圳）有限公司 | Method and device for realizing data transmission and electronic equipment |
| CN111240252B (en) * | 2020-03-25 | 2021-04-20 | 武汉迈信电气技术有限公司 | Multi-encoder data interaction system and method based on FPGA |
| CN111488301B (en) * | 2020-05-28 | 2024-12-31 | 深圳开立生物医疗科技股份有限公司 | Blood cell analyzer and control system, method, electronic device, and medium thereof |
| CN112559402B (en) * | 2020-12-23 | 2021-11-26 | 广东高云半导体科技股份有限公司 | PCI slave interface control circuit based on FPGA and FPGA |
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| US20080262984A1 (en) * | 2007-04-19 | 2008-10-23 | Microsoft Corporation | Field-Programmable Gate Array Based Accelerator System |
| CN102096783A (en) * | 2011-02-09 | 2011-06-15 | 浪潮电子信息产业股份有限公司 | FPGA (Field Programmable Gate Array)-based algorithm encryption card specially for tax control |
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| CN1609862A (en) * | 2004-11-19 | 2005-04-27 | 华南理工大学 | PCI bus-based IP core simulation verification platform and its verification method |
| CN100498806C (en) * | 2007-09-19 | 2009-06-10 | 中国科学院上海技术物理研究所 | Device and method for outputting signal of emulation infrared detector |
| CN103729165A (en) * | 2014-01-16 | 2014-04-16 | 哈尔滨工业大学 | PCI (peripheral component interconnect) slave unit core control module applied to high-speed motion control system |
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| US20080262984A1 (en) * | 2007-04-19 | 2008-10-23 | Microsoft Corporation | Field-Programmable Gate Array Based Accelerator System |
| CN102096783A (en) * | 2011-02-09 | 2011-06-15 | 浪潮电子信息产业股份有限公司 | FPGA (Field Programmable Gate Array)-based algorithm encryption card specially for tax control |
Non-Patent Citations (1)
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| 基于FPGA的PCI软核模块的研究与实现;周雷;《中国优秀硕士学位论文全文数据库》;20100115(第01期);正文第二章-第四章 * |
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