CN104465417A - Method for encapsulating semiconductor structure through encapsulating module - Google Patents
Method for encapsulating semiconductor structure through encapsulating module Download PDFInfo
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- CN104465417A CN104465417A CN201410780793.3A CN201410780793A CN104465417A CN 104465417 A CN104465417 A CN 104465417A CN 201410780793 A CN201410780793 A CN 201410780793A CN 104465417 A CN104465417 A CN 104465417A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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Abstract
一种用封装模块封装半导体结构的方法，属于把芯片封装在基片上形成半导体器件的技术领域。这种用封装模块封装半导体结构的方法采用上封装模块和下封装模块，封装模块具有一个合模面、平滑面和型腔。平滑面是一个与合模面相切的曲面并置于型腔的开口处，当封装模块与携带芯片的完整基片连接时，合模面接触并压基片。平滑面和合模面连接形成一条切线，平滑面和合模面相互连接的截面切在0.78-1.85毫米之间的距离被分隔。型腔内填充一种把芯片封装在基片上的密封胶。该封装模块通过合模面加压基片表面时，基片接触到的是光滑的合模面，从而降低基片承载压力，不会对半导体封装结构。
A method for packaging a semiconductor structure with a packaging module belongs to the technical field of packaging chips on substrates to form semiconductor devices. The method of packaging a semiconductor structure with an encapsulation module employs an upper encapsulation module and a lower encapsulation module, the encapsulation module having a mating surface, a smooth surface and a mold cavity. The smooth surface is a curved surface tangent to the mating surface and placed at the opening of the cavity. When the packaging module is connected to the complete substrate carrying the chip, the mating surface contacts and presses the substrate. The smooth surface and the mating surface are connected to form a tangent, and the cross-sectional cuts where the smooth surface and the mating surface are connected to each other are separated at a distance of 0.78-1.85 mm. The cavity is filled with a sealant that encapsulates the chip on the substrate. When the encapsulation module presses the surface of the substrate through the mold clamping surface, the substrate contacts the smooth mold clamping surface, thereby reducing the bearing pressure of the substrate and preventing the semiconductor packaging structure from being affected.
Description
技术领域 technical field
本发明涉及一种用封装模块封装半导体结构的方法，属于把芯片封装在基片上形成半导体器件的技术领域。 The invention relates to a method for packaging a semiconductor structure with a packaging module, and belongs to the technical field of packaging chips on substrates to form semiconductor devices.
背景技术 Background technique
封装模块被使用在正常的封装基片过程中，封装模块有一个型腔和一个合模面。在合模面与基片接触以后加压，型腔充满密封胶。密封胶被冷却并凝固，固定于基片。 The encapsulation module is used in the normal process of encapsulating the substrate. The encapsulation module has a cavity and a mating surface. After the mold surface is in contact with the substrate, pressure is applied, and the cavity is filled with sealant. The sealant is cooled and solidified, fixing it to the substrate.
通常封装模具的模块封装基片的过程中，封装模具的模块用力压实基片的表面，充分与基片表面接触后,往模块中注入密封胶。密封胶、冷却和凝固固定在基片上。然而,如果有模具的模块遇到有较大变形的基片表面，模块再用力压实基片将会出现许多问题。例如,接触的形状是一个锐角，将出现许多缺点: Usually, during the process of encapsulating the substrate with the module of the encapsulation mold, the module of the encapsulation mold compacts the surface of the substrate with force, and after fully contacting with the surface of the substrate, the sealant is injected into the module. The sealant, cools and solidifies to secure the substrate. However, if the module with the mold encounters a substrate surface with a large deformation, many problems will arise when the module is forced to compact the substrate. For example, where the shape of the contact is an acute angle, a number of disadvantages will arise:
第一、当封装模具模块用力下压接触基片,接触已经变形严重的基片表面。模块表面合模面部分快速的下压变形基片,如果模块的型腔边是一个锐角。锋利的锐角和基片接触的部位产生巨大的压力，压进基片的变形位置。此压力会导致基片表面被封装的芯片、金线与基片连接点受到较大的损伤。 First, when the encapsulation mold module is pressed down hard to contact the substrate, it contacts the severely deformed substrate surface. The mating surface portion of the module surface rapidly presses down to deform the substrate if the cavity side of the module is at an acute angle. The sharp acute angle and the contact part of the substrate generate huge pressure, pressing into the deformed position of the substrate. This pressure will cause great damage to the packaged chip on the surface of the substrate, the connection point between the gold wire and the substrate.
第二、如果接触部分基片有一个较大的变形,与锋利的型腔锐角接触,柔软的基片表面处理层受强大压力作用下，内部线层可能会膨胀和剥离表面处理层。 Second, if the contact part of the substrate has a large deformation, it is in contact with the sharp cavity at an acute angle, and the soft substrate surface treatment layer is under strong pressure, the inner line layer may swell and peel off the surface treatment layer.
第三、模具模块方面型腔中填充的密封胶在冷却和凝固过程中，密封胶对模具型腔锋利的锐角成型部分造成较大的冲击，可能因此缩短模具的寿命。 Third, during the cooling and solidification process of the sealant filled in the cavity of the mold module, the sealant will cause a greater impact on the sharp-edged part of the mold cavity, which may shorten the life of the mold.
第四、如果模具模块锐角成型区域发生损坏，将严重影响半导体封装结构的质量。 Fourth, if the sharp-angle forming area of the mold module is damaged, it will seriously affect the quality of the semiconductor packaging structure.
发明内容 Contents of the invention
为了克服现有技术中存在的问题，本发明提供一种用封装模块封装半导体结构的方法，该封装模块通过合模面加压基片表面，型腔具有平滑面与其合模表面连接。当模块合模面接触基片加压时，基片接触到的是光滑的合模面，从而降低基片承载压力，不会对半导体封装结构造成不良影响。 In order to overcome the problems existing in the prior art, the present invention provides a method of packaging a semiconductor structure with a packaging module, the packaging module presses the surface of the substrate through the clamping surface, and the cavity has a smooth surface connected to the clamping surface. When the mold clamping surface of the module contacts the substrate and is pressurized, the substrate contacts the smooth mold clamping surface, thereby reducing the bearing pressure of the substrate and not causing adverse effects on the semiconductor packaging structure.
本发明采用的技术方案是：一种用封装模块封装半导体结构的方法，封装模块把芯片封装在基片，形成一个完整的半导体器件，所述封装模块包括上封装模块和下封装模块，封装模块具有一个合模面、平滑面和型腔，平滑面是一个与合模面相切的曲面并置于型腔的开口处，当封装模块与携带芯片的完整基片连接时，合模面接触并压基片；所述型腔内部的壁顶面与壁侧面连接，型腔（110）内部的壁顶面在基片对面，型腔内部的壁侧面与平滑面连接，型腔内部的壁顶面和壁侧面相互连接形成一夹角，平滑面和合模面与一个切点相连，相互连接的切点在0.78 -1.85 毫米之间的距离被分隔；所述型腔内填充一种把芯片封装在基片上的密封胶。 The technical scheme adopted in the present invention is: a method for packaging a semiconductor structure with a packaging module. The packaging module packages the chip on the substrate to form a complete semiconductor device. The packaging module includes an upper packaging module and a lower packaging module. The packaging module It has a mating surface, a smooth surface and a cavity. The smooth surface is a curved surface tangent to the mating surface and placed at the opening of the cavity. When the packaging module is connected to the complete substrate carrying the chip, the mating surface contacts and Press the substrate; the wall top inside the cavity is connected to the wall side, the wall top inside the cavity (110) is opposite to the substrate, the wall side inside the cavity is connected to the smooth surface, the wall top inside the cavity The surface and the wall side are connected to each other to form an included angle, the smooth surface and the clamping surface are connected with a tangent point, and the tangent point of mutual connection is separated at a distance of 0.78-1.85 mm; the cavity is filled with a chip package Sealants on substrates.
所述平滑面采用第一平滑面，或采用第一平滑面、第二平滑面和第三平滑面连续过渡的组合结构。 The smooth surface adopts the first smooth surface, or adopts the combined structure of the continuous transition of the first smooth surface, the second smooth surface and the third smooth surface.
所述第一平滑面采用圆表面的一部分时，第二平滑面和第三平滑面-也采用圆表面的一部分，圆表面的曲率半径范围从0.1-2.0 毫米。 When the first smooth surface adopts a part of a circular surface, the second smooth surface and the third smooth surface also adopt a part of a circular surface, and the radius of curvature of the circular surface ranges from 0.1 to 2.0 mm.
所述第一平滑面采用椭圆表面的一部分时，第二平滑面和第三平滑面也采用椭圆表面的一部分，椭圆的主轴范围从0.1-1.17 毫米，短袖范围从0.1-1.0 毫米。 When the first smooth surface adopts a part of the elliptical surface, the second smooth surface and the third smooth surface also adopt a part of the elliptical surface, the main axis of the ellipse ranges from 0.1-1.17 mm, and the short sleeve ranges from 0.1-1.0 mm.
本发明的有益效果是：这种用封装模块封装半导体结构的方法采用上封装模块和下封装模块，封装模块具有一个合模面、平滑面和型腔。平滑面是一个与合模面相切的曲面并置于型腔的开口处，当封装模块与携带芯片的完整基片连接时，合模面接触并压基片。平滑面和合模面与一个切点相连，相互连接的切在0.78-1.85 毫米之间的距离被分隔。型腔内填充一种把芯片封装在基片上的密封胶。该封装模块通过合模面加压基片表面时，基片接触到的是光滑的合模面，从而降低基片承载压力，不会对半导体封装结构造成不良影响。 The beneficial effects of the present invention are: the method for packaging a semiconductor structure with a packaging module adopts an upper packaging module and a lower packaging module, and the packaging module has a mold clamping surface, a smooth surface and a mold cavity. The smooth surface is a curved surface tangent to the mating surface and placed at the opening of the cavity. When the packaging module is connected to the complete substrate carrying the chip, the mating surface contacts and presses the substrate. The smooth and mating surfaces are connected with a tangent point, and the interconnected tangents are separated by a distance between 0.78-1.85 mm. The cavity is filled with a sealant that encapsulates the chip on the substrate. When the encapsulation module presses the surface of the substrate through the mold clamping surface, the substrate contacts the smooth mold clamping surface, thereby reducing the bearing pressure of the substrate and causing no adverse effect on the semiconductor packaging structure.
附图说明： Description of drawings :
图1 是通常已知的带锋利锐角的封装模块。 Figure 1 is a commonly known packaged module with sharp corners.
图2是一种用封装模块封装半导体的结构。 FIG. 2 is a structure for packaging semiconductors with packaging modules.
图3是一个封装半导体成型图。 Fig. 3 is a molding diagram of a packaged semiconductor.
图4是图2 中的A 放大图（第一方案）。 Figure 4 is an enlarged view of A in Figure 2 (the first scheme).
图5是图2 中的A 放大图（第二方案）。 Figure 5 is an enlarged view of A in Figure 2 (the second scheme).
图6是图3中的B放大图。 FIG. 6 is an enlarged view of B in FIG. 3 .
图中：100、上封装模块，102、芯片，104、基片，108、合模面，110、型腔，112、密封胶，114、第一平滑面，116、密封胶侧面，118、第二平滑面，120、填充空间，122、下封装模块，124、金线，126、半导体封装结构底面，132、第三平滑面，134、壁顶面，136、壁侧面，138、夹角，140、密封胶顶面，142、密封胶夹角，T1、T2、T3、T4、T5、T6、切点。 Among the figure: 100, upper packaging module, 102, chip, 104, substrate, 108, mold clamping surface, 110, cavity, 112, sealant, 114, first smooth surface, 116, sealant side, 118, the first Two smooth surfaces, 120, filling space, 122, lower packaging module, 124, gold wire, 126, bottom surface of semiconductor packaging structure, 132, third smooth surface, 134, wall top surface, 136, wall side, 138, included angle, 140, sealant top surface, 142, sealant angle, T1, T2, T3, T4, T5, T6, tangent point.
具体实施方式 Detailed ways
图1 是通常已知的带锋利锐角的封装模块。一般的半导体封装模块在型腔侧具有一个锐角P1，锐角P1与变形的基片表面接触,基片结构承受较大压力，导致基片表面被封装的芯片、金线与基片连接受到较大的损伤,如芯片与金线焊点脱落，或从基片上损坏或剥落。 Figure 1 is a commonly known packaged module with sharp corners. A general semiconductor packaging module has an acute angle P1 on the side of the cavity, and the acute angle P1 is in contact with the deformed substrate surface, and the substrate structure is under greater pressure, resulting in a greater impact on the connection between the packaged chip and the gold wire on the substrate surface. Damage, such as chip and gold wire solder joints falling off, or damage or peeling from the substrate.
图2是一种用封装模块封装半导体的结构。图3是一个封装半导体成型图。封装模块包括一个上封装模块100 和下封装模块122 。下封装模块122 用于承载基片104 。上封装模块100 具有一个合模面108 和一个型腔110 。上封装模块100 和下封装模块122 可保持基片104 固定在上封装模块100和下封装模块122之间。此外，当上封装模块100 和下封装模块122 被连接时，合模面108 接触并加压基片104 ，以便基片104 在上封装模块100与下封装模块122之间被压紧。型腔110 用于填充一种密封胶112 (如图3所示)，以便密封胶112 设置在基片104上，用于保护封装芯片102与金线124。 FIG. 2 is a structure for packaging semiconductors with packaging modules. Fig. 3 is a molding diagram of a packaged semiconductor. The encapsulation module includes an upper encapsulation module 100 and a lower encapsulation module 122 . The lower packaging module 122 is used to carry the substrate 104 . The upper packaging module 100 has a mold surface 108 and a cavity 110 . The upper packaging module 100 and the lower packaging module 122 can hold the substrate 104 fixed between the upper packaging module 100 and the lower packaging module 122. In addition, when the upper packaging module 100 and the lower packaging module 122 are connected, the mold surface 108 contacts and presses the substrate 104 so that the substrate 104 is compressed between the upper packaging module 100 and the lower packaging module 122. The cavity 110 is used to fill a sealant 112 (as shown in FIG. 3 ), so that the sealant 112 is disposed on the substrate 104 to protect the packaged chip 102 and the gold wire 124.
图4是图2 中的A 放大图（第一方案）。如图4 所示，上封装模块100 具有接触型腔110 的第一平滑面114 。第一平滑面114 是合模面108 的切面。当第一平滑面114 与合模面108 相切时，上封装模块100 接触并加压基片104，接触基片104 的是第一平滑面114 的边界，其是合模面108 的切面而不是在通常公知技术的一个锋利形状 (如图1所示的锐角P1)。第一平滑面114 不损害表面处理层（金线124的焊接点）和被置于基片104 上的金属结构（芯片102）。第一平滑面114 具有一个平滑外表，避免表面处理层被损伤并剥离。 Figure 4 is an enlarged view of A in Figure 2 (the first scheme). As shown in FIG. 4 , the upper packaging module 100 has a first smooth surface 114 that contacts the cavity 110 . The first smooth surface 114 is a tangent surface of the mating surface 108. When the first smooth surface 114 was tangent to the mold-mold surface 108 , the upper package module 100 contacted and pressed the substrate 104 , and what contacted the substrate 104 was the boundary of the first smooth surface 114 , which was the cut surface of the mold-mold surface 108 and Not a sharp shape (acute angle P1 as shown in Figure 1) in the usual known art. The first smooth surface 114 does not damage the surface treatment layer (the soldering point of the gold wire 124) and the metal structure (chip 102) placed on the substrate 104. The first smooth surface 114 has a smooth appearance to prevent the surface treatment layer from being damaged and peeled off.
当型腔110 (如图2所示)充满熔化的密封胶112时，熔化的密封胶填充在基片104与第一平滑面114 之间，填充空间120 并接触第一平滑面114 ，以便在熔化的密封胶和上封装模块100 之间的接触面积被增加。因而，填充空间120 的密封胶被上封装模块100 延伸到基片104 上，减少基片104 承担压力，以及压力延伸到被置于表面处理层和被封装的基片104 的金属结构上，以便表面处理层和金属结构将不被过多的压力所损害。 When the mold cavity 110 (as shown in Figure 2) was full of the sealant 112 of melting, the sealant of melting was filled between the substrate 104 and the first smooth surface 114, filled the space 120 and contacted the first smooth surface 114, so that The contact area between the melted sealant and the upper package module 100 is increased. Thus, the sealant filling the space 120 is extended to the substrate 104 by the upper packaging module 100, reducing the pressure on the substrate 104, and the pressure extends to the metal structure placed on the surface treatment layer and the encapsulated substrate 104, so that Surface treatments and metal structures will not be damaged by excessive pressure.
型腔110 内部的壁顶面134 与型腔110 内部的壁侧面136 连接。内部的壁顶面134 在基片104 对面。内部的壁侧面136 为第一平滑面114 的切面。在内部的壁顶面134 与内部的壁侧面136 之间相互连接形成的夹角138顶点和第一平滑面114 与合模面108相切的切线（图中为切点T1）之间具有一个预定距离D1，D1范围为0.78 -1.85 毫米。 Wall top 134 inside cavity 110 is connected to wall side 136 inside cavity 110 . The inner wall top surface 134 is opposite the substrate 104 . The inner wall side 136 is a tangent to the first smooth surface 114 . Between the inner wall top surface 134 and the inner wall side surface 136 , there is a tangent between the vertex of the angle 138 formed by the connection between the inner wall top surface 134 and the first smooth surface 114 and the mold surface 108 (tangent point T1 in the figure). The predetermined distance D1 is in the range of 0.78-1.85 mm.
图5是图2 中的A 放大图（第二方案）。当上封装模块100 和下封装模具块122 被连接时，第一平滑面114 也能通过第一平滑面114 的一部分接触基片104 。以图5中第一平滑面114 以一范围在为例切点T3 和切点T4 。当上封装模块100 和下封装模块122 (如图2所示)被连接时，上封装模块100延伸的压力过大，基材表面124 可能稍微被压成锯齿状。当第一平滑面114 接触基材表面124 通过第三平滑面132 而不是通过一个锐角时，基片104 不会承担一个太大的压力并且变得进一步锯齿状。此外，密封胶填充空间120 (如图4所示)，上封装模块100 延伸产生的压力是微小的，这有助于维持在基片104 上完整的表面处理层和金属结构。 Figure 5 is an enlarged view of A in Figure 2 (the second scheme). When the upper packaging module 100 and the lower packaging mold block 122 are connected, the first smooth surface 114 can also contact the substrate 104 through a part of the first smooth surface 114 . Taking the first smooth surface 114 in Fig. 5 as an example, the tangent point T3 and the tangent point T4 are in a range. When the upper encapsulation module 100 and the lower encapsulation module 122 (as shown in FIG. 2 ) are connected, the upper encapsulation module 100 is stretched with excessive pressure, and the substrate surface 124 may be slightly jagged. When the first smooth surface 114 contacts the substrate surface 124 through the third smooth surface 132 rather than through an acute angle, the substrate 104 does not take too much pressure and become further jagged. In addition, the sealant fills the space 120 (as shown in FIG. 4 ), and the pressure generated by the extension of the upper packaging module 100 is slight, which helps to maintain the integrity of the surface treatment layer and metal structure on the substrate 104 .
当基片104具有一次平滑外表时，其与第三平滑面132 相对应，很少会发生通常公知技术图1 的锐角P1 的压力集中现象。 When the substrate 104 has a primary smooth surface, which corresponds to the third smooth surface 132, the pressure concentration phenomenon of the acute angle P1 of the conventional known technology Fig. 1 rarely occurs.
当长的第一平滑面114是平滑时，第一平滑面114 和一部分的相交线连续和可微分。例如，第一平滑面114 可成为一个圆的表面的一部分，其曲率半径范围从0.1-2.0 毫米，优选为0.6 毫米。第一平滑面114 可成为其主轴范围从0.1-1.17 毫米的一个椭圆面的一部分，短袖范围从0.1-1.0 毫米。 When the long first smooth surface 114 is smooth, the intersection line of the first smooth surface 114 and a portion is continuous and differentiable. For example, the first smooth surface 114 can be part of a round surface with a radius of curvature ranging from 0.1-2.0 mm, preferably 0.6 mm. The first smooth surface 114 may be part of an ellipse whose major axis ranges from 0.1-1.17 mm, and the short sleeve ranges from 0.1-1.0 mm.
图6是图3中的B放大图。密封胶112 设置在半导体器件的基片104上，第一平滑面114与密封胶112 、基片表面124 和密封胶侧面116 连接。其中第二个平滑面118 对应于第一平滑面114 并以切点T2 和切点T6 间的范围为例。 FIG. 6 is an enlarged view of B in FIG. 3 . The sealant 112 is arranged on the substrate 104 of the semiconductor device, and the first smooth surface 114 is connected with the sealant 112 , the substrate surface 124 and the sealant side 116 . Wherein the second smooth surface 118 corresponds to the first smooth surface 114 and takes the range between the tangent point T2 and the tangent point T6 as an example.
在密封胶112 形成以后，密封胶112 的外部的侧面116 与密封胶112 的一个密封胶顶面140 连接。在第二个平滑面118 和基片表面124 之间的切点T2 和在密封胶顶面140 和密封胶侧面116 之间的相互连接密封胶夹角142 被一个预定距离D2 分隔，其中预定距离D2 从0.78-1.85 毫米对预定距离D1范围是一样的。 After the sealant 112 is formed, the outer side 116 of the sealant 112 is joined to a sealant top surface 140 of the sealant 112 . The tangent point T2 between the second smooth surface 118 and the substrate surface 124 and the interconnecting sealant angle 142 between the sealant top surface 140 and the sealant side 116 are separated by a predetermined distance D2, wherein the predetermined distance D2 is the same for the predetermined distance D1 range from 0.78-1.85 mm.
此外，如果第一平滑面114 是一个圆的表面的一部分，然后第二个平滑面118 是一个相应的圆的表面，如果第一平滑面114 是一个椭圆面的一部分，然后第二个平滑面118 也是一个相应的椭圆面。第二个平滑面118 的尺寸相应地对应于第一平滑面114 的。 Furthermore, if the first smooth surface 114 is part of a round surface, then the second smooth surface 118 is a corresponding round surface, and if the first smooth surface 114 is part of an elliptical surface, then the second smooth surface 118 is also a corresponding ellipse. The dimensions of the second smooth surface 118 correspond accordingly to those of the first smooth surface 114.
在本发明的实施例中谈及的半导体封装结构可成为一个球阵列封装(BGA)封装结构，其有一些焊球(不说明)被置于图3 的半导体器件的底面126 的。不过，以上所述例子不是限制用于本发明，适用制造任何封装结构。其在本发明实施例中谈及半导体封装结构，是使用在以上所述被公布实施例中的封装模块。 The semiconductor package structure mentioned in the embodiment of the present invention can be a ball array package (BGA) package structure, which has some solder balls (not illustrated) placed on the bottom surface 126 of the semiconductor device in FIG. 3 . However, the above examples are not limited to the present invention, and are applicable to manufacture any package structure. It refers to the semiconductor packaging structure in the embodiment of the present invention, which is the packaging module used in the above-mentioned disclosed embodiments.
半导体封装结构，封装模块用于相同成型，在以上所述被公布实施例中的封装模块，许多优点将被验证证明。 The semiconductor packaging structure, the packaging module is used for the same molding, the packaging module in the above disclosed embodiments, many advantages will be verified.
第一、在封装过程期间，当合模面接触和加压基片，第一平滑面接触基片或部分第一平滑面合模面接触的切线基片，以便减少基片承担的压力，使表面处理层和金属结构维持完整。 First, during the encapsulation process, when the mating surface contacts and pressurizes the substrate, the first smooth surface contacts the substrate or part of the tangent substrate of the first smooth surface mating surface contact, so as to reduce the pressure borne by the substrate, so that The surface treatment and metal structure remain intact.
第二、第一平滑面的平滑或部分第一平滑面合模面接触的切线，是被置于基片的柔软的表面处理层，使得基片上的柔软的表面处理层将不被过压，进而柔软的表面处理层将不被压力损伤并且剥离。 Second, the smoothness of the first smooth surface or the tangent of part of the first smooth surface mating surface contact is placed on the soft surface treatment layer of the substrate so that the soft surface treatment layer on the substrate will not be overstressed, In turn the soft surface treatment will not be damaged by pressure and will peel off. the
第三、型腔通过一部分第一平滑面接触合模面，其具有一个平滑外表，是部分第一平滑面和合模面的切线而不是一个锐角。因而，封装模具在密封胶冷却固化过程期间有更好的热传导性，这有助于保证并延长寿命封装模具寿命。 Third, the mold cavity contacts the mold-mating surface through a part of the first smooth surface, which has a smooth appearance and is a tangent between the part of the first smooth surface and the mold-mating surface instead of an acute angle. Thus, the packaging mold has better thermal conductivity during the cooling and curing process of the sealant, which helps to ensure and prolong the lifetime of the packaging mold.
第四、在封装模块的合模面与型腔相互连接之间形成空腔部位，此部位在制造封装结构上没有留下过多的压力，因而更好的保证了半导体封装结构的质量。 Fourthly, a cavity is formed between the jointing surface of the packaging module and the mold cavity. This part does not leave too much pressure on the manufacturing packaging structure, thus better ensuring the quality of the semiconductor packaging structure.
同时本发明依据描述一个实施实例举例来说明，可以说明本发明向那里不被限制。反之，其用意是本发明可覆盖不同的封装模块和相似的封装结构，所附的权利要求的范围应当给予广泛的解释包含所有封装模块和类似的封装结构。 While the present invention is illustrated by describing an embodiment example, it can be explained that the present invention is not limited thereto. Rather, it is intended that the present invention may cover different packaging modules and similar packaging structures, and the scope of the appended claims should be given a broad interpretation to include all packaging modules and similar packaging structures.
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| US20050186711A1 (en) * | 2004-02-20 | 2005-08-25 | Yee Richard M.L. | Mould for encapsulating a leadframe package and method of making the same |
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