CN104409564B - N-type nanometer black silicon manufacturing method and solar cell manufacturing method - Google Patents

Abstract

The invention discloses an N-type nanometer black silicon manufacturing method and a solar cell manufacturing method. The N-type nanometer black silicon manufacturing method comprises steps that: (1), silicon chips after cleaning react in mixed solution of KOH and isopropanol for 0.5-2 hours, and the reaction temperature is 60-100 DEG C; and (2), the N-type silicon chips treated in the step (1) are put in a silver nanometer particle solution for 20-30 minutes in a standing mode, after drying, corrosion treatment on the treated N-type silicon chips is carried out to acquire the N-type nanometer black silicon. For manufacturing a solar cell, an N+ layer, a silicon nitride layer and an electrode layer are sequentially formed at the front surface of the manufactured N-type nanometer black silicon, after sintering, the N-type nanometer black silicon solar cell is manufactured. The manufactured N-type nanometer black silicon solar cell has properties of low reflectivity and high carrier service life and has the conversion efficiency 2.2% higher than that of a cell manufactured through a routine method.

Description

A kind of preparation method of N-type nano black silicon and the preparation method of solar cell

technical field

The invention relates to the field of photovoltaic technology, in particular to a method for preparing N-type nano black silicon and a method for preparing solar cells.

Background technique

Optical loss is a major factor hindering the improvement of solar cell efficiency, and reducing the optical loss of solar cells is an important and effective way to improve cell efficiency. At present, crystalline silicon mainly adopts "pyramid" texture anti-reflection structure on the surface of silicon wafer to reduce the reflectivity, but its average reflectivity in the visible light band is above 10%, and the reflection loss of light is still relatively large, which restricts the efficiency of solar cells. Further improve.

The nanoporous black silicon structure can effectively reduce the reflectivity of the anti-reflection structure. It can be prepared by electrochemical methods and metal-assisted catalysis. Metal-assisted catalysis has received more and more attention because of its relatively simple preparation process, good antireflection effect on both single crystal and polycrystal, and potential industrial application value.

The nanoporous black silicon structure prepared on the pyramid texture by metal-assisted catalysis can obtain very low reflectivity, but because the porous structure greatly increases the specific surface area of the silicon wafer, the carrier recombination is very serious, which leads to the short circuit of the battery The current is relatively low, making the cell efficiency not as high as that of commercial solar cells. Jihun Oh*, Hao-Chih Yuan and Howard M.Branz. An 18.2%-efficient black-silicon solar cell achieved through control of carrier recombination innanostructures.Nature Nano technology, 2012 , 7:743-748) by using tetramethylammonium hydroxide (tetramethylammonium hydroxide, TMAH) to etch the prepared nano-light trapping structure, effectively reducing the specific surface area and pore density of the silicon wafer surface, thus preparing a high-efficiency black silicon cells. However, the high cost of TMAH has caused obstacles to industrial application. Therefore, seeking an etchant with low cost and good etching effect has become the goal of everyone's exploration.

In addition, most nanoporous black silicon structures are currently prepared on P-type silicon wafers, and compared with P-type silicon wafers, the minority carrier lifetime of N-type silicon wafers with the same resistivity is higher than that of P-type silicon wafers. , which is mainly related to the fact that more boron-oxygen pairs in boron-doped P-type silicon wafers act as recombination centers, and the tolerance of N-type silicon wafers to metal contamination is higher than that of P-type silicon wafers. It will be more advantageous for the preparation of nano black silicon structure by catalytic corrosion of silver nanoparticles. Therefore, compared with the P-type silicon wafer, the nanoporous silicon wafer prepared on the N-type silicon wafer will have a higher minority carrier lifetime, which will help to improve the short-circuit current of the battery.

Contents of the invention

The purpose of the present invention is to prepare a nano-light trapping structure on the surface of an N-type Czochralski single crystal silicon wafer, and at the same time reduce the specific surface area of the silicon wafer surface by alkali etching, reduce carrier recombination, and increase the minority carrier lifetime, thereby effectively improving battery efficiency. , and finally the silicon wafer is prepared according to the current P-type black silicon solar cell production process to obtain a high-efficiency N+NP back-junction solar cell.

The preparation method of black silicon of the present invention comprises the following steps:

(1) React the cleaned silicon chip in a mixed solution of KOH and isopropanol for 0.5-2 hours at a reaction temperature of 60-100° C., and a pyramid structure of uniform size is formed on the surface of the silicon chip.

The cleaning method is as follows: put the N-type silicon chip in KOH solution to clean it, and remove the surface damage of the silicon chip;

The cleaning time is related to the concentration of KOH solution, usually 10-20 minutes. Preferably, the concentration of the KOH solution is 15-30mt% (mt% means mole percentage), so as to remove the surface damage of the silicon wafer. More optimally, the concentration of the KOH solution is 20mt%.

Preferably, the mass concentration of KOH in the mixed solution of KOH and isopropanol is 3%, and the volume concentration of isopropanol is 7%.

Further preferably, the reaction temperature of the reaction is 80° C., and the corresponding reaction time is 60 minutes.

(2) Put the N-type silicon chip treated in the step (1) into the silver nanoparticle solution and let it stand for 20min to 30min, dry it and perform corrosion treatment to obtain N-type nano black silicon.

The silicon wafer will form a layer of oxide layer in the air. The surface of silicon oxide is hydrophilic, so the silver nanoparticles in the solution can form a good contact with the surface of the silicon wafer. During the standing process, the silver nanoparticles will be deposited on the silicon wafer. surface as a catalyst for subsequent reactions.

Preferably, the size (particle diameter) of the silver nanoparticles in the silver nanoparticle solution of the present invention is 50-100 nm, and the size distribution is uniform.

In the present invention, the silver nanoparticle solution prepared by the following method is actually an aqueous solution of silver nanoparticles, and the concentration can be set according to actual application needs, usually 0.02～0.1mol/L, preferably 0.05mol/L. The following method is used to prepare silver nanoparticles, and then the obtained silver nanoparticles are configured into a silver nanoparticle solution of required concentration. Wherein, the preparation method of silver nanoparticles is as follows:

At 35°C, add 37vol% CH ₂ O to the 0.1mol/L AgNO ₃ solution, use polyvinylpyrrolidone (PVP) K-30 with a mass concentration of 0.75% to 3% as a surfactant, and then add 28vol% Ammonia promotes the reaction, stirring and mixing for 30 minutes, and then adding alcohol and centrifuging four times to obtain silver nanoparticles with a size of about 50-100 nm.

The size of silver nanoparticles can be controlled by adjusting the amount of polyvinylpyrrolidone PVP K-30, so that the size of silver particles can be controlled within the range of 50-100nm. The temperature is controlled at 35°C, because the reducing ability of formaldehyde is closely related to the temperature, and the higher the temperature, the faster the reaction. The growth temperature may also affect the agglomeration of Ag particles. In agglomerated growth, the growth rate of silver particles accelerates as the temperature increases. In the late stage of the intermediate stage, the surface potential of Ag particles decreases with increasing temperature. At low temperatures, the rate of agglomeration is low due to electrostatic repulsion. As the temperature increases, the surface potential decreases, resulting in weak repulsive forces and high growth rates.

The N-type silicon chip formed in the pyramidal structure in the step (2) is subjected to etching treatment. As preferably, the corrosion process is specifically as follows:

The N-type silicon wafer treated in step (2) is placed in an etching solution for etching reaction under a light-shielding environment, and the etching solution is a mixed solution of HF, H ₂ O ₂ and deionized water.

Preferably, the volume ratio of HF, H ₂ O ₂ and deionized water in the corrosion solution is 1:(4-6):(8-12). Further, the volume ratio of HF, H ₂ O ₂ and deionized water in the corrosion solution is 1:5:10.

The corrosion reaction can be carried out at room temperature. Preferably, the reaction time of the corrosion reaction is 3 minutes to 6 minutes.

Because H ₂ O ₂ is easy to decompose when exposed to light, the reaction needs to be carried out in a light-shielding container. In the present invention, the corrosion reaction can be carried out in a light-shielding environment by using a light-shielding reaction container to store the corrosion solution.

A uniform nanoporous structure can be obtained on the surface of the silicon wafer by etching, and this structure has a strong light-trapping effect, that is, as a light-trapping structure.

Usually, the etched silicon wafer has become black silicon. In order to further enhance the light-trapping effect, it is further preferable to perform etching correction on the etched N-type silicon wafer (in fact, the most etched light-trapping structure continues to be etched) fix).

After etching correction, the corrosion depth in the nanoporous light-trapping structure will become shallower, the pore size will increase, the specific surface area of the silicon wafer surface will decrease, and the surface recombination will also decrease.

As preferably, during etching correction, the N-type silicon chip after the etching treatment is directly reacted in the etching correction solution, and the etching correction solution is an alkaline solution, such as TMAH, NaOH, etc., and may also be an acidic solution, such as H ₂ O ₂ and HNO ₃ mixture.

Considering cost and effect, preferably, the etching correction solution is a NaOH solution with a concentration of 1-5 wt% (wt% represents mass percentage), and the reaction time is 2-4 minutes. Optimally, the concentration of NaOH solution used during etching is 2 wt %, and the reaction time is 3 min.

There will be silver nanoparticles on the surface of the silicon wafer after the corrosion reaction, and these silver nanoparticles will affect the subsequent application effect. Into the silicon chip to form a carrier recombination center, reducing the lifetime of minority carriers, thereby affecting battery performance.

Excessively high alkali concentration and long time will lead to violent reaction, and it is easy to etch all the prepared nano-light trapping structure (ie, light-trapping structure). If the concentration is too low, the reaction will be slow, and a longer reaction time is required.

After alkali etching, there will be sodium ions on the surface of the silicon wafer, which need to be removed with hydrochloric acid. Sodium ions remain on the N-type silicon wafer after etching. Therefore, the etched and corrected N-type silicon wafer is further placed in 10 vol% hydrochloric acid for 2-5 minutes, and then cleaned and dried to obtain the final nanometer black silicon. Usually rinse with deionized water and blow dry with nitrogen.

Preferably, the step (2) further includes performing residue removal treatment on the etched N-type silicon wafer to remove residual silver nanoparticles. In the present invention, the etched N-type silicon wafer is placed in a 65wt% HNO ₃ solution for 1 min to remove residual silver nanoparticles.

The present invention also provides a method for preparing an N-type black silicon solar cell. First, N-type nano-black silicon is prepared, and then an N+ layer, a silicon nitride layer and an electrode layer are sequentially formed on the front surface of the prepared N-type nano-black silicon. , and finally sintering to obtain an N-type black silicon solar cell, and the N-type nano black silicon is prepared through the above steps (1) to (3).

In the present invention, according to the existing P-type solar cell production process, gaseous diffusion and phosphorus expansion are carried out to form an N+ layer on the front surface, and the silicon nitride layer is prepared by PECVD. The electrode layer is prepared by a screen printing method, and this adopts an all-aluminum back screen printing method.

On the one hand, the present invention places silver nanoparticles with controllable size on the surface of a silicon chip, and prepares a nano light-trapping structure with very low reflectivity through silver catalytic corrosion at room temperature, and then passes alkali Etching reduces surface recombination and increases the lifetime of minority carriers, thereby effectively improving the short-circuit current and open-circuit voltage of the battery. Although the reflectivity will increase in this process, it is still lower than 5.5%. Compared with the reflectivity of the existing industrial anti-reflection structure of more than 10%, it is already a relatively large drop, and the battery efficiency is compared to that of the non-reflective structure. Alkali-etched cells will increase by 2.2%. On the other hand, the present invention adopts the higher N-type silicon chip of metal impurity tolerance, because the minority carrier lifetime of the N-type silicon chip of the same resistivity is higher than that of the P-type silicon chip, so the N-type silicon chip has more It is beneficial to reduce the impact caused by the serious surface recombination of the nano-black silicon structure.

There is no special description in the present invention. The N-type silicon wafer is an N-type Czochralski monocrystalline silicon wafer. The size of the N-type silicon wafer is based on the actual situation, and the resistivity is 1-10Ω·cm.

Compared with the prior art, the invention has the following advantages:

(a) The present invention uses size-controllable silver nanoparticles to catalyze and prepare a nano-light trapping structure on an N-type Czochralski single crystal silicon wafer. This structure is prepared on the basis of a silicon wafer pyramid structure, and the reflectivity can be reduced to 2.4%. the following. Afterwards, a low-concentration sodium hydroxide solution is used to etch the structure. By reducing the etching depth of the light-trapping structure and enlarging the pore size, the specific surface area of the silicon wafer surface is reduced, the surface recombination is reduced, and the minority carriers are increased. The reflectance of silicon wafer after etching correction will also increase accordingly, but it is still lower than 5.5%. The conversion efficiency of this battery is 2.2% higher than that of conventional methods;

(b) The manufacturing process of the present invention is simple and fast, and the preparation process is compatible with the preparation method of P-type silicon solar cells. It does not need to purchase any large-scale equipment, and the cost of raw materials involved is relatively low, and it can be compared with the existing industrial production process. Very well compatible, the surface reflectance of the treated silicon wafer is low, the minority carrier life is high, and the cell efficiency can reach 17.8%.

Description of drawings

Fig. 1 is the SEM figure of the N-type silicon chip surface of corrosion 0min among the embodiment 1;

Fig. 2 is the SEM figure of the N-type silicon chip surface of corrosion 4min among the embodiment 1;

Fig. 3 is the reflectance figure of the silicon chip when etching 3,4,5,6min in embodiment 1;

FIG. 4 is a reflectance diagram of the N-type silicon wafer surface obtained by etching for 0 min and 4 min in embodiment 1 and embodiment 2. FIG.

detailed description

The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments.

Example 1

The preparation method of the N-type nano black silicon of the present embodiment comprises the steps:

(1) 1.5g polyvinylpyrrolidone (PVP K-30) is dissolved in water, forms 50g base liquid, and the mass concentration of formaldehyde is 0.74% in the base liquid, and the mass concentration of polyvinylpyrrolidone in the base liquid is 3%, to base liquid Add dropwise silver nitrate aqueous solution mass concentration in the liquid to be 1.7%, rapidly inject ammonia water (mass fraction is 0.6ml of the solution of 28%), react 30min under 35 ℃, obtain the solution of silver nanoparticles, then add alcohol and centrifuge four times, obtain silver Nanoparticles, the silver nanoparticles are spherical, and the size (particle diameter) of the silver nanoparticles is 50nm-100nm.

(2) Put an N-type silicon wafer (N-type Czochralski single-crystal native silicon wafer) with a size of 156mm×156mm into 20mt% KOH solution, react at 80°C for 2min, and remove the damaged layer on the surface of the silicon wafer.

(3) Put the silicon chip after cleaning into the mixed solution of KOH and isopropanol, wherein the mass concentration of KOH is 3%, and the volume concentration of isopropanol is 7%, react 60min under the condition of 80 ℃, in silicon The sheet surface forms a pyramid structure of uniform size.

(4) Put the silicon chip with pyramid structure in step (3) into the silver nanoparticle solution and let it stand for 20 minutes, then dry it. The surface structure of the obtained N-type silicon chip is shown in Figure 1.

The minority carrier lifetime of the N-type silicon wafer at this time is 10.18 μs measured by the minority carrier lifetime tester. The reflectance test was further carried out, and the obtained reflectance is shown as curve a in FIG. 4 , and the reflectance was 13.4%.

(5) Put the silicon chip of step (4) into a light-shielding reaction container equipped with etching solution, and react at room temperature for 3, 4, 5, and 6 minutes respectively. The etching solution is HF, H ₂ O ₂ and deionized water. Mixed solution, the solution ratio is 1:5:10 (volume ratio), forming a nano-light trapping structure on the surface of the pyramid, that is, obtaining a monocrystalline silicon solar cell texture with low surface reflectivity, that is, N-type nano-black silicon.

Fig. 2 is a scanning electron microscope (SEM) picture of the surface of the silicon wafer after being etched for 4 minutes. Comparing Figure 2 with Figure 1, it can be seen that after 4 minutes of catalytic corrosion, the porous structure evenly covers the surface of the N-type silicon wafer, forming a nano-light trapping structure.

Fig. 3 is the reflectance spectrum of the silicon wafer under different catalytic etching time, it can be seen that the average reflectance in the wavelength range of 300-1100nm is reduced to below 2.4%. Among them, the reflectivity corresponding to corrosion for 3, 4, 5, and 6 minutes is 2.2%, 1.9%, 2.0%, and 2.3%, respectively.

The minority carrier lifetime of the N-type nano-black silicon obtained by etching for 4 minutes is 2.73 μs after being tested by a minority carrier lifetime tester.

(6) Put the silicon chip of step (5) into 65wt% HNO3 solution and place it for 1 min to remove residual silver nanoparticles.

In this embodiment, gaseous diffusion of phosphorus to form an N+ layer on the front surface, PECVD silicon nitride plating, screen printing and sintering are also carried out according to the existing P-type solar cell production process. However, screen printing should use all-aluminum back printing.

The solar cell obtained in this embodiment is the nanometer black silicon N+NP solar cell. Under the light intensity of AM 1.5, the electrical properties of the battery were tested by using the cell efficiency sorter, and the test results are shown in Table 1. Among them, Voc is the open circuit voltage, Isc is the short circuit current, FF is the fill factor, η is the conversion efficiency, and τ is the minority carrier lifetime of the silicon wafer after texturing.

For the convenience of comparison, Table 1 also lists the electrical performance and minority carrier lifetime of existing N+NP solar cells (ie, prior art) under light intensity of AM 1.5. The existing N+NP solar cell refers to an N+NP solar cell with no nano light-trapping structure but only a pyramidal structure on the surface (that is, an N-type silicon wafer etched for 0 min).

Table 1

Example 2

Same as Example 1, the difference is that the etching time in step (5) is 4min, and the N-type silicon wafer after step (5) is processed by the following process between step (6) and step (7) Make etch corrections:

Put the N-type silicon chip treated in step (6) into 2wt% NaOH solution and react for 3 minutes, so as to perform etching correction on the nano light-trapping structure obtained in step (5). Then put the silicon chip into 10vol% hydrochloric acid for 2 minutes to remove sodium ions, then clean the silicon chip with deionized water, and then dry it with nitrogen gas.

The nanometer black silicon N+NP solar cell prepared in Example 2 was tested for various electrical properties of the cell by using a cell efficiency sorter under the light intensity of AM 1.5, and the results are shown in Table 1.

The minority carrier lifetime of the N-type nano black silicon prepared in this embodiment is 5.19 μs, and the corresponding reflectivity is shown in curve c in FIG. 4 , and the reflectivity is 5.4%. For ease of comparison, the reflectance curve of the N-type silicon wafer etched for 4 minutes in Example 1 is also shown in FIG. 4 , as shown in curve b.

Comparing the test parameters of the above-mentioned embodiments, it is found that although the reflectance of the silicon wafer after the etching correction will increase correspondingly, it is still lower than 5.5%, and the conversion efficiency of the solar cell after the etching correction is higher than that in the embodiment only. The conversion efficiency of the solar cell corresponding to 4min is 2.2% higher.

The above-mentioned specific embodiments have described the technical solutions and beneficial effects of the present invention in detail. It should be understood that the above-mentioned are only the most preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, supplements and equivalent replacements made within the scope shall be included in the protection scope of the present invention.

Claims (8)

1. a preparation method of solar cell, it is characterized in that, prepare N-type nano-black silicon, then form N+ layer, silicon nitride layer and electrode layer successively on the front surface of the N-type nano-black silicon that prepares and carry out sintering Obtain an N-type nano-black silicon solar cell; the electrode layer is prepared by an all-aluminum back printing method; The preparation method of N-type nanometer black silicon comprises the following steps: (1) Reacting the cleaned N-type silicon chip in a mixed solution of KOH and isopropanol for 0.5 to 2 hours, the reaction temperature is 60 to 100° C.; (2) Put the N-type silicon chip treated in the step (1) into the silver nanoparticle solution and let it stand for 20min to 30min, dry it and perform corrosion treatment to obtain N-type nano black silicon. 2 . The method for preparing a solar cell according to claim 1 , wherein the step (2) further comprises performing etching correction on the etched N-type silicon wafer. 3 . 3 . The method for preparing a solar cell according to claim 2 , wherein, during etching correction, the etched N-type silicon wafer is reacted in an etching correction solution. 4 . 4. The method for preparing a solar cell according to claim 3, wherein the etching correction solution is a NaOH solution with a concentration of 1-5 wt%. 5 . The method for preparing a solar cell according to claim 4 , wherein the reaction time for etching correction is 2-4 minutes. 6 . 6. The method for preparing a solar cell according to any one of claims 2 to 5, wherein before the etching correction, it also includes performing a residue removal treatment on the etched N-type silicon wafer to remove residues. of silver nanoparticles. 7. the preparation method of solar cell as claimed in claim 6 is characterized in that, in described step (2), the N-type silicon chip after drying is reacted in etching solution for 3min～6min to finish etching treatment, and described The corrosion solution is a mixture of HF, H ₂ O ₂ and deionized water. 8. The method for preparing a solar cell according to claim 7, wherein the volume ratio of HF, H ₂ O ₂ and deionized water in the corrosive solution is 1:(4～6):(8～12 ).