CN104409516A - Thin film transistor and manufacturing method thereof, array substrate and manufacturing method thereof and display device - Google Patents
Thin film transistor and manufacturing method thereof, array substrate and manufacturing method thereof and display device Download PDFInfo
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- CN104409516A CN104409516A CN201410713290.4A CN201410713290A CN104409516A CN 104409516 A CN104409516 A CN 104409516A CN 201410713290 A CN201410713290 A CN 201410713290A CN 104409516 A CN104409516 A CN 104409516A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
- H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
- H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
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- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
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- H10D64/60—Electrodes characterised by their materials
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- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/01—Manufacture or treatment
- H10D86/021—Manufacture or treatment of multiple TFTs
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- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
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- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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Abstract
本发明属于显示技术领域，具体涉及一种薄膜晶体管及制备方法、阵列基板及制备方法以及显示装置。该薄膜晶体管，包括栅极、源极和漏极；所述栅极的上方和/或下方设置有栅钝化层；所述源极和漏极的上方和/或下方设置有源漏钝化层；其中，所述栅钝化层和源漏钝化层采用铝钝化形成。该薄膜晶体管以及相应的阵列基板，采用具有较低电阻率的金属材料形成电极，且采用铝钝化形成隔离钝化层，在保持较高导电性的同时，能改善电极与相邻层的附着性，并防止形成电极或引线的材料中金属离子的扩散。
The invention belongs to the field of display technology, and in particular relates to a thin film transistor, a preparation method, an array substrate, a preparation method, and a display device. The thin film transistor includes a gate, a source and a drain; a gate passivation layer is provided above and/or below the gate; a source-drain passivation is provided above and/or below the source and drain layer; wherein, the gate passivation layer and the source-drain passivation layer are formed by aluminum passivation. The thin film transistor and the corresponding array substrate use metal materials with low resistivity to form electrodes, and use aluminum passivation to form an isolation passivation layer, which can improve the adhesion between electrodes and adjacent layers while maintaining high conductivity properties, and prevent the diffusion of metal ions in the materials forming the electrodes or leads.
Description
Technical Field
The invention belongs to the technical field of display, and particularly relates to a thin film transistor and a preparation method thereof, an array substrate and a preparation method thereof, and a display device.
Background
With the development of display technology, people have increasingly growing demands for display image quality, and the demands for flat panel display devices with high image quality and high resolution are more and more common and more paid more and more attention by display panel manufacturers. A Thin Film Transistor (TFT) is a main driving device of a flat panel display panel, and is directly related to the development direction of a high performance flat panel display device.
In recent years, a copper thin film having a low resistivity has been used for electrodes and wirings of thin film transistors in semiconductor integrated circuits and flat panel display panels, and since the on resistance is low, the transmission speed of digital signals can be increased and the amount of electric power can be reduced. However, the adhesion between the copper thin film and the semiconductor active layer is poor, and copper atoms in the copper thin film diffuse into the semiconductor active layer in contact therewith, affecting the characteristics of the semiconductor active layer. In addition, the adhesion between the copper thin film and the substrate and the insulating layer is also poor, and the copper thin film is easy to fall off in the actual use process, thereby reducing the service life of the product.
As described above, when a low-resistance thin film is used as an electrode of a conventional thin film transistor, the reliability of the thin film transistor is lowered.
Disclosure of Invention
The invention provides a thin film transistor, a preparation method thereof, an array substrate, a preparation method thereof and a display device, aiming at the defects in the prior art. According to the thin film transistor and the corresponding array substrate, the electrode is formed by adopting a metal material with lower resistivity, the isolation passivation layer is formed by adopting aluminum passivation, the adhesion between the electrode and an adjacent layer can be improved while higher conductivity is kept, and the diffusion of metal ions in the material for forming the electrode or a lead wire is prevented.
The technical scheme adopted for solving the technical problem is that the thin film transistor comprises a grid electrode, a source electrode and a drain electrode, wherein a grid passivation layer is arranged above and/or below the grid electrode; a source drain passivation layer is arranged above and/or below the source electrode and the drain electrode; the gate passivation layer and the source drain passivation layer are formed by aluminum passivation.
Preferably, the gate electrode, the source electrode and the drain electrode are formed using any one of molybdenum, molybdenum-niobium alloy, aluminum-neodymium alloy, titanium and copper.
It is further preferred that the gate, source and drain are all formed of copper.
Preferably, the gate passivation layer disposed above the gate electrode at least completely covers the gate electrode, and the gate passivation layer disposed below the gate electrode at least corresponds to an orthographic projection area of the gate electrode on the substrate; the source and drain passivation layers arranged above the source electrode and the drain electrode at least completely cover the source electrode and the drain electrode, and the source and drain passivation layers arranged below the source electrode and the drain electrode at least correspond to orthographic projection areas of the source electrode and the drain electrode on the substrate.
A preparation method of a thin film transistor comprises the steps of forming a grid electrode, a source electrode and a drain electrode, forming a grid passivation layer above and/or below the grid electrode, and forming a source drain passivation layer above and/or below the source electrode and the drain electrode; the gate passivation layer and the source and drain passivation layer are formed by aluminum passivation.
Preferably, the step of forming the gate passivation layer and the source drain passivation layer includes:
forming a metal aluminum film on a substrate by a sputtering technique;
and passivating the substrate with the metal aluminum film by a solution passivation method.
It is further preferable that the solvent in the solution used in the solution passivation method is any one of chromate, zirconate, and permanganate.
It is further preferred that the concentration of the solution used in the solution passivation method is in the range of 1 to 15g/L, the temperature is in the range of 20 to 80 ℃, and the pH is in the range of 1 to 4.
It is further preferred that the time of passivation is 10 to 80 s.
Preferably, the step of forming the gate passivation layer and the source drain passivation layer includes:
forming a metal aluminum film on a substrate by a sputtering technique;
and passivating the substrate on which the metallic aluminum film is formed by an oxygen ion passivation method.
Further preferably, the passivating the substrate on which the metallic aluminum thin film is formed by an oxygen ion passivation method specifically includes:
bombarding the surface of the metallic aluminum film by oxygen plasma, wherein the power range is set to be 200-800W, the pressure range is set to be 50-200mT, the gas flow range is 10-500sccm, the temperature range is 20-300 ℃, and the time range is 5-30 s.
An array substrate comprises the thin film transistor.
The preparation method of the array substrate comprises the step of forming the thin film transistor, wherein the thin film transistor is formed by adopting the preparation method of the thin film transistor.
A display device comprises the array substrate.
The invention has the beneficial effects that: in the thin film transistor and the corresponding array substrate, copper is preferably adopted as an electrode or lead material, correspondingly, an isolation passivation layer formed by aluminum passivation is adopted as an isolation buffer layer (barrier and buffer) material between the electrode or lead and an adjacent layer, and the high conductivity is kept, so that the adhesion between the copper and the substrate is improved and the falling off is prevented; on the other hand, the diffusion of copper ions to the silicon-containing film layer can be prevented, and the switching characteristic of the thin film transistor is ensured. Accordingly, the display effect of the display device is improved.
Drawings
Fig. 1 is a cross-sectional view of a thin film transistor in embodiment 1 of the present invention;
fig. 2 is a cross-sectional view of an array substrate in embodiment 1 of the present invention;
fig. 3 is a cross-sectional view of an array substrate in embodiment 2 of the present invention;
fig. 4 is a cross-sectional view of an array substrate in embodiment 3 of the present invention;
fig. 5 is a cross-sectional view of an array substrate in embodiment 4 of the present invention;
reference numerals:
1-substrate, 21-bottom gate passivation layer, 22-top gate passivation layer, 3-gate, 4-gate insulating layer, 5-semiconductor layer, 6-ohmic contact layer, 71-bottom source drain passivation layer, 72-top source drain passivation layer, 81-source, 82-drain, 9-passivation layer and 10-pixel electrode.
Detailed Description
In order to make the technical solutions of the present invention better understood, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
A thin film transistor comprises a grid electrode, a source electrode and a drain electrode, wherein a grid passivation layer is arranged above and/or below the grid electrode, a source drain passivation layer is arranged above and/or below the source electrode and the drain electrode, and the grid passivation layer and the source drain passivation layer are formed by aluminum passivation.
An array substrate comprises the thin film transistor.
A display device comprises the array substrate.
A preparation method of a thin film transistor comprises the steps of forming a grid electrode, a source electrode and a drain electrode, forming a grid passivation layer above and/or below the grid electrode, and forming a source drain passivation layer above and/or below the source electrode and the drain electrode; the gate passivation layer and the source and drain passivation layer are formed by aluminum passivation.
Example 1:
the embodiment provides a thin film transistor which comprises a grid electrode, a source electrode and a drain electrode, wherein a grid passivation layer is arranged below the grid electrode, a source drain passivation layer is arranged below the source electrode and the drain electrode, and the grid passivation layer and the source drain passivation layer are formed by aluminum passivation.
As shown in fig. 1, in the present embodiment, the gate passivation layer is a bottom gate passivation layer 21; the source drain passivation layer is a bottom source drain passivation layer 71. In the thin film transistor of the present embodiment, a bottom gate passivation layer 21 is disposed above the substrate 1, and a gate electrode 3 is disposed above the bottom gate passivation layer 21; a gate insulating layer 4 is arranged above the gate electrode 3, a semiconductor layer 5 is arranged above the gate insulating layer 4, and an ohmic contact layer 6 is arranged above the semiconductor layer 5; a bottom source-drain passivation layer 71 is disposed above the ohmic contact layer 6, and a source electrode 81 and a drain electrode 82 are disposed above the bottom source-drain passivation layer 71.
In this embodiment, the gate electrode 3, the source electrode 81, and the drain electrode 82 are formed of at least one material selected from molybdenum, a molybdenum-niobium alloy, aluminum, an aluminum-neodymium alloy, titanium, and copper, wherein molybdenum, a molybdenum-niobium alloy, an aluminum-neodymium alloy, or titanium has only weak oxidation property, aluminum is less likely to be oxidized, and copper is most likely to be oxidized. However, in view of resistivity, it is more preferable that the gate electrode 3, the source electrode 81, and the drain electrode 82 are formed of copper.
The substrate 1 is generally made of glass or quartz material containing silicon, as shown in fig. 1, the bottom gate passivation layer 21 disposed below the gate 3 at least corresponds to an orthographic projection area of the gate 3 on the bottom surface of the gate 3, so that the bottom gate passivation layer 21 can perform a better isolation buffer effect on the gate 3 and the substrate 1, and can increase adhesion with the substrate 1; the bottom source-drain passivation layer 71 disposed below the source electrode 81 and the drain electrode 82 at least corresponds to an orthographic projection area of the source electrode 81 and the drain electrode 82 on the bottom surfaces of the source electrode 81 and the drain electrode 82, so that the bottom source-drain passivation layer 71 can play a better role in isolating and buffering the source electrode 81 and the drain electrode 82 from the semiconductor layer 5/ohmic contact layer 6, and prevent copper ions from diffusing to the silicon-containing semiconductor layer 5/ohmic contact layer 6.
The preparation method of the thin film transistor comprises the step of forming a grid electrode, a source electrode and a drain electrode, wherein a grid passivation layer is formed below the grid electrode, a source drain passivation layer is formed below the source electrode and the drain electrode, and the grid passivation layer and the source drain passivation layer are formed by aluminum passivation.
In the invention, the patterning process may only comprise a photolithography process, or may comprise a photolithography process and an etching step, and may also comprise other processes for forming a predetermined pattern, such as printing, ink jetting, etc.; the photolithography process refers to a process of forming a pattern by using a photoresist, a mask plate, an exposure machine, and the like, including processes of film formation, exposure, development, and the like. The corresponding patterning process may be selected according to the structure formed in the present invention.
In this embodiment, the gate passivation layer and the source drain passivation layer may be formed by forming a gate passivation film layer and a source drain passivation film layer in the following two ways:
1. firstly, a layer of metal aluminum (Al) film is deposited on a glass substrate by utilizing a sputtering technology, the thickness of the film can be regulated and controlled according to needs, then the metal aluminum film is treated by utilizing a solution passivation method, the passivation solution is any one of chromate, zirconate and permanganate, and other corresponding components can be adopted. Taking chromate as an example, the specific implementation mode is as follows: the concentration range of chromate is preferably 1-15g/L, the adjusting temperature range is preferably 20-80 ℃, the pH value range is preferably 1-4, and the control time range is preferably 10-80s to passivate the metal aluminum film so as to form a gate passivation film layer and a source drain passivation film layer.
2. Firstly, a layer of metal aluminum (Al) film is deposited on a glass substrate by utilizing a sputtering technology, the thickness of the film can be regulated and controlled according to the requirement, and then the metal aluminum film is processed by utilizing an oxygen ion passivation method, wherein the specific implementation mode is as follows: and bombarding the surface of the metal aluminum film by using oxygen plasma, wherein the set power range is preferably 200-.
The present embodiment further provides an array substrate, as shown in fig. 2, the array substrate includes the thin film transistor.
In the array substrate, a grid line is arranged on the same layer as the grid 3 and is electrically connected with the grid 3, and the grid line and the grid 3 are made of the same material and are formed in the same composition process; also disposed on the same layer as the source electrode 81 is a data line electrically connected to the source electrode 81, and the data line and the source electrode 81 are formed of the same material and in the same patterning process. Further, a passivation layer 9 is further disposed over the source and drain electrodes 81 and 82, and a pixel electrode 10 is further disposed over the passivation layer 9.
A preparation method of the array substrate comprises the preparation method for forming the thin film transistor.
Specifically, taking a 5mask process as an example, the method for manufacturing the array substrate specifically includes the following steps (wherein step S1-step S3 are steps of forming the thin film transistor of fig. 1):
step 1, a graph comprising a bottom gate passivation layer 21 and a grid electrode 3 is formed on a substrate 1 by adopting a one-step composition process.
In this step, initial cleaning → bottom gate passivation film layer deposition (aluminum passivation formation) → gate film layer deposition (Cu: copper) → photoresist coating → gate film layer pattern exposure, development, post-baking → gate film layer pattern etching → photoresist stripping.
The two ways of forming the bottom gate passivation film layer and the source and drain passivation film layers are as described above, and are not described in detail herein.
And 2, forming a pattern comprising the gate insulating layer 4, the semiconductor layer 5 and the ohmic contact layer 6 by adopting a one-step composition process.
In the step, cleaning before film forming → gate insulating layer deposition (SixNy or SixOy: silicon nitride or silicon oxide) → semiconductor film layer and ohmic contact film layer deposition (Pure a-Si and Impurity a-Si: amorphous silicon and N + amorphous silicon) → photoresist coating → semiconductor film layer and ohmic contact film layer pattern exposure and development, post-baking → semiconductor film layer and ohmic contact film layer dry etching → photoresist stripping.
And 3, forming a graph comprising a bottom source drain passivation layer, a source electrode and a drain electrode by adopting a one-time composition process.
In this step, bottom source and drain passivation film layer deposition (aluminum passivation formation) → source and drain film layer deposition (Cu: copper) → photoresist coating → source and drain film layer pattern exposure development, post-baking → source and drain film layer etching → ohmic contact film layer dry etching → photoresist stripping.
And in the step, the deposition process of the bottom source drain passivation film layer is the same as that of the bottom gate passivation film layer in the step 1.
Thus, the thin film transistor is manufactured, and the gate line and the data line are formed in advance to facilitate the wiring of the array substrate.
And 4, forming a pattern comprising the passivation layer and the electrode contact through hole thereof by adopting a one-step composition process.
In this step, a passivation film layer is deposited (SixNy or SixOy: silicon nitride or silicon oxide) → photoresist coating → electrode contact via pattern exposure, development, post-baking → electrode contact via etching → photoresist stripping.
And 5, forming a pattern comprising the pixel electrode by adopting a one-time composition process.
In this step, the deposition of the pixel electrode film layer (ITO or IZO: indium tin oxide or indium zinc oxide) → photoresist coating → pixel electrode film layer pattern exposure development, post-baking → pixel electrode film layer etching → photoresist stripping → annealing.
In this embodiment, the pattern of the specific structure of the array substrate may refer to a pattern of a corresponding structure prepared by the array substrate in the prior art, and the specific process in the array substrate preparation method may refer to a corresponding process in the array substrate preparation method in the prior art, which is not described herein again.
Example 2:
the embodiment provides a thin film transistor and an array substrate including the same.
The thin film transistor comprises a grid electrode, a source electrode and a drain electrode, wherein a grid passivation layer is arranged below the grid electrode, source and drain passivation layers are respectively arranged above and below the source electrode and the drain electrode, and the grid passivation layer and the source and drain passivation layers are formed by aluminum passivation.
As shown in fig. 3, in the array substrate of the present embodiment, the gate passivation layer is a bottom gate passivation layer 21; the source and drain passivation layers are a bottom source and drain passivation layer 71 and a top source and drain passivation layer 72. In the thin film transistor of the present embodiment, a bottom gate passivation layer 21 is disposed above the substrate 1, and a gate electrode 3 is disposed above the bottom gate passivation layer 21; a gate insulating layer 4 is arranged above the gate electrode 3, a semiconductor layer 5 is arranged above the gate insulating layer 4, and an ohmic contact layer 6 is arranged above the semiconductor layer 5; a bottom source drain passivation layer 71 is disposed above the ohmic contact layer 6, a source electrode 81 and a drain electrode 82 are disposed above the bottom source drain passivation layer 71, and a Top source drain passivation layer 72(Top barrier) is further disposed above the source electrode 81 and the drain electrode 82. The array substrate is also provided with a passivation layer 9 above the thin film transistor, and a pixel electrode 10 above the passivation layer 9.
As shown in fig. 3, the bottom gate passivation layer 21 disposed below the gate electrode at least corresponds to an orthographic projection area of the gate electrode 3 on the bottom surface of the gate electrode 3, so that the bottom gate passivation layer 21 can perform a better isolation buffer effect on the gate electrode 3 and the substrate 1, and can increase adhesion with the substrate 1; the bottom source-drain passivation layer 71 arranged below the source electrode and the drain electrode at least corresponds to the orthographic projection areas of the source electrode 81 and the drain electrode 82 on the bottom surfaces of the source electrode 81 and the drain electrode 82, so that the bottom source-drain passivation layer 71 can play a better role in isolating and buffering the source electrode 81 and the drain electrode 82 and the semiconductor layer 5/ohmic contact layer 6, and prevent copper ions from diffusing to the silicon-containing semiconductor layer 5/ohmic contact layer 6; the passivation layer 9 is generally formed by a silicon nitride or silicon oxide material containing silicon, and the top source drain passivation layer 72 disposed above the source electrode 81 and the drain electrode 82 at least completely covers the source electrode 81 and the drain electrode 82, so that the top source drain passivation layer 72 can perform a better isolation buffer effect on the source electrode 81 and the drain electrode 82 from the passivation layer 9, and prevent copper ions from diffusing into the silicon-containing passivation layer 9.
The method for manufacturing the array substrate in this embodiment specifically includes the following steps (step S1-step S3 is a step of forming a thin film transistor):
step 1, a graph comprising a bottom gate passivation layer 21 and a grid electrode 3 is formed on a substrate 1 by adopting a one-step composition process.
In this step, initial cleaning → bottom gate passivation film layer deposition (aluminum passivation formation) → gate film layer deposition (Cu: copper) → photoresist coating → gate film layer pattern exposure, development, post-baking → gate film layer pattern etching → photoresist stripping.
The deposition process of the bottom gate passivation film layer is the same as that of the bottom gate passivation film layer in example 1, and is not described herein again.
And 2, forming a pattern comprising the gate insulating layer 4, the semiconductor layer 5 and the ohmic contact layer 6 by adopting a one-step composition process.
In the step, cleaning before film forming → gate insulating layer deposition (SixNy or SixOy: silicon nitride or silicon oxide) → semiconductor film layer and ohmic contact film layer deposition (Pure a-Si and Impurity a-Si: amorphous silicon and N + amorphous silicon) → photoresist coating → semiconductor film layer and ohmic contact film layer pattern exposure and development, post-baking → semiconductor film layer and ohmic contact film layer dry etching → photoresist stripping.
And 3, forming a graph comprising a bottom source drain passivation layer, a source electrode, a drain electrode and a top source drain passivation layer by adopting a one-step composition process.
In the step, bottom source and drain passivation film layer deposition (aluminum passivation formation) → source and drain film layer deposition (Cu: copper) → top source and drain passivation film layer deposition (aluminum passivation formation) → photoresist coating → source and drain film layer pattern exposure development, post-baking → source and drain film layer etching → ohmic contact film layer dry etching → photoresist stripping.
The deposition process of the bottom source-drain passivation film layer and the top source-drain passivation film layer is the same as that of the bottom gate passivation film layer in embodiment 1, and details are not repeated here.
Thus, the thin film transistor is manufactured, and the gate line and the data line are formed in advance to facilitate the wiring of the array substrate.
And 4, forming a pattern comprising the passivation layer and the electrode contact through hole thereof by adopting a one-step composition process.
In the step, passivation film layer deposition → photoresist coating → electrode contact via pattern exposure, development, post-baking → electrode contact via etching → photoresist stripping.
And 5, forming a pattern comprising the pixel electrode by adopting a one-time composition process.
In this step, the deposition of the pixel electrode film layer (ITO or IZO: indium tin oxide or indium zinc oxide) → photoresist coating → pixel electrode film layer pattern exposure development, post-baking → pixel electrode film layer etching → photoresist stripping → annealing.
In this embodiment, the pattern of the specific structure of the array substrate may refer to the pattern of the corresponding structure prepared by the array substrate in embodiment 1, and the specific process in the array substrate preparation method may refer to the corresponding process in the array substrate preparation method in embodiment 1, which is not described herein again.
Example 3:
the embodiment provides a thin film transistor and an array substrate including the same.
The thin film transistor comprises a grid electrode, a source electrode and a drain electrode, wherein grid passivation layers are respectively arranged above and below the grid electrode, source and drain passivation layers are arranged below the source electrode and the drain electrode, and the grid passivation layers and the source and drain passivation layers are formed by aluminum passivation.
As shown in fig. 4, in the array substrate of this embodiment, the gate passivation layers are a bottom gate passivation layer 21 and a top gate passivation layer 22; the source drain passivation layer is a bottom source drain passivation layer 71. In the thin film transistor of the present embodiment, a bottom gate passivation layer 21 is disposed above the substrate 1, a gate electrode 3 is disposed above the bottom gate passivation layer 21, and a TOP gate passivation layer 22(TOP barrier) is disposed above the gate electrode 3; a gate insulating layer 4 is arranged above the top gate passivation layer 22, a semiconductor layer 5 is arranged above the gate insulating layer 4, and an ohmic contact layer 6 is arranged above the semiconductor layer 5; a bottom source-drain passivation layer 71 is disposed above the ohmic contact layer 6, and a source electrode 81 and a drain electrode 82 are disposed above the bottom source-drain passivation layer 71. The array substrate is also provided with a passivation layer 9 above the thin film transistor, and a pixel electrode 10 above the passivation layer 9.
As shown in fig. 4, the bottom gate passivation layer 21 disposed below the gate electrode at least corresponds to an orthographic projection area of the gate electrode 3 on the bottom surface of the gate electrode 3, so that the bottom gate passivation layer 21 can perform a better isolation buffer effect on the gate electrode 3 and the substrate 1, and can increase adhesion with the substrate 1; the gate insulating layer 4 is generally formed by silicon nitride or silicon oxide material containing silicon, and the top gate passivation layer 22 arranged above the gate electrode 3 at least completely covers the gate electrode 2, so that the top gate passivation layer 22 can play a better role in isolating and buffering the gate electrode 3 and the gate insulating layer 4, and prevent copper ions from diffusing to the silicon-containing gate insulating layer 4; the bottom source-drain passivation layer 71 disposed below the source electrode 81 and the drain electrode 82 at least corresponds to an orthographic projection area of the source electrode 81 and the drain electrode 82 on the bottom surfaces of the source electrode 81 and the drain electrode 82, so that the bottom source-drain passivation layer 71 can play a better role in isolating and buffering the source electrode 81 and the drain electrode 82 from the ohmic contact layer 6, and prevent copper ions from diffusing to the silicon-containing semiconductor layer 5/ohmic contact layer 6.
The method for manufacturing the array substrate in this embodiment specifically includes the following steps (step S1-step S3 is a step of forming a thin film transistor):
step 1, forming a graph comprising a bottom gate passivation layer 21, a gate electrode 3 and a top gate passivation layer 22 on a substrate 1 by adopting a one-step patterning process.
In this step, initial cleaning → bottom gate passivation film layer deposition (aluminum passivation formation) → gate film layer deposition (Cu: copper) → top gate passivation film layer deposition (aluminum passivation formation) → photoresist coating → gate film layer pattern exposure, development, post-baking → gate film layer pattern etching → photoresist stripping.
The deposition process of the bottom gate passivation film layer and the top gate passivation film layer is the same as that of the bottom gate passivation film layer in example 1, and details are not repeated here.
It should be understood that the top-gate passivation film layer may also be formed by aluminum passivation to ensure the conductivity of the gate electrode (in this case, the thickness of the molybdenum material forming the top-gate passivation film layer is not limited).
And 2, forming a pattern comprising the gate insulating layer 4, the semiconductor layer 5 and the ohmic contact layer 6 by adopting a one-step composition process.
In the step, cleaning before film forming → gate insulating layer deposition → semiconductor film layer and ohmic contact film layer deposition → photoresist coating → semiconductor film layer and ohmic contact film layer pattern exposure and development, post-baking → semiconductor film layer and ohmic contact film layer dry etching → photoresist stripping.
And 3, forming a graph comprising a bottom source drain passivation layer, a source electrode and a drain electrode by adopting a one-time composition process.
In this step, bottom source and drain passivation film layer deposition (aluminum passivation formation) → source and drain film layer deposition (Cu: copper) → photoresist coating → source and drain film layer pattern exposure development, post-baking → source and drain film layer etching → ohmic contact film layer dry etching → photoresist stripping.
The deposition process of the bottom source-drain passivation film layer is the same as that of the bottom gate passivation film layer, and is not described herein again.
Thus, the thin film transistor is manufactured, and the gate line and the data line are formed in advance to facilitate the wiring of the array substrate.
And 4, forming a pattern comprising the passivation layer and the electrode contact through hole thereof by adopting a one-step composition process.
In the step, passivation film layer deposition → photoresist coating → electrode contact via pattern exposure, development, post-baking → electrode contact via etching → photoresist stripping.
And 5, forming a pattern comprising the pixel electrode by adopting a one-time composition process.
In this step, the deposition of the pixel electrode film layer (ITO or IZO: indium tin oxide or indium zinc oxide) → photoresist coating → pixel electrode film layer pattern exposure development, post-baking → pixel electrode film layer etching → photoresist stripping → annealing.
In this embodiment, the pattern of the specific structure of the array substrate may refer to the pattern of the corresponding structure prepared by the array substrate in embodiment 1, and the specific process in the array substrate preparation method may refer to the corresponding process in the array substrate preparation method in embodiment 1, which is not described herein again.
Example 4:
the embodiment provides a thin film transistor and an array substrate including the same.
The thin film transistor comprises a grid electrode, a source electrode and a drain electrode, wherein grid passivation layers are arranged above and below the grid electrode, source drain passivation layers are arranged above and below the source electrode and the drain electrode, and the grid passivation layers and the source drain passivation layers are formed by aluminum passivation.
As shown in fig. 5, in the array substrate of this embodiment, the gate passivation layers are a bottom gate passivation layer 21 and a top gate passivation layer 22; the source and drain passivation layers are a bottom source and drain passivation layer 71 and a top source and drain passivation layer 72. In the thin film transistor of the present embodiment, a bottom gate passivation layer 21 is disposed above the substrate 1, a gate electrode 3 is disposed above the bottom gate passivation layer 21, and a top gate passivation layer 22 is disposed above the gate electrode 3; a gate insulating layer 4 is arranged above the top gate passivation layer 22, a semiconductor layer 5 is arranged above the gate insulating layer 4, and an ohmic contact layer 6 is arranged above the semiconductor layer 5; a bottom source-drain passivation layer 71 is disposed above the ohmic contact layer 6, a source electrode 81 and a drain electrode 82 are disposed above the bottom source-drain passivation layer 71, and a top source-drain passivation layer 72 is disposed above the source electrode 81 and the drain electrode 82. The array substrate is also provided with a passivation layer 9 above the thin film transistor, and a pixel electrode 10 above the passivation layer 9.
As shown in fig. 5, the bottom gate passivation layer 21 disposed below the gate electrode at least corresponds to an orthographic projection area of the gate electrode 3 on the bottom surface of the gate electrode 3, so that the bottom gate passivation layer 21 can perform a better isolation buffer effect on the gate electrode 3 and the substrate 1, and can increase adhesion with the substrate 1; the top gate passivation layer 22 arranged above the gate electrode 3 at least completely covers the gate electrode 2, so that the top gate passivation layer 22 can play a better role in isolating and buffering the gate electrode 3 and the gate insulating layer 4 and prevent copper ions from diffusing to the silicon-containing gate insulating layer 4; the bottom source-drain passivation layer 71 arranged below the source electrode 81 and the drain electrode 82 at least corresponds to the orthographic projection areas of the source electrode 81 and the drain electrode 82 on the bottom surfaces of the source electrode 81 and the drain electrode 82, so that the bottom source-drain passivation layer 71 and the top source-drain passivation layer 72 can play a better role in isolating and buffering the source electrode 81 and the drain electrode 82 and the semiconductor layer 5/ohmic contact layer 6, and copper ions are prevented from diffusing to the silicon-containing semiconductor layer 5/ohmic contact layer 6; the top source-drain passivation layer 72 disposed above the source electrode 81 and the drain electrode 82 at least completely covers the gate electrode 2, so that the top source-drain passivation layer 72 can perform a better isolation buffer function on the source electrode 81, the drain electrode 82 and the passivation layer 9, and prevent copper ions from diffusing to the passivation layer 9 containing silicon.
The method for manufacturing the array substrate in this embodiment specifically includes the following steps (step S1-step S3 is a step of forming a thin film transistor):
step 1, forming a graph comprising a bottom gate passivation layer 21, a gate electrode 3 and a top gate passivation layer 22 on a substrate 1 by adopting a one-step patterning process.
In this step, initial cleaning → bottom gate passivation film layer deposition (aluminum passivation formation) → gate film layer deposition (Cu: copper) → top gate passivation film layer deposition (aluminum passivation formation) → photoresist coating → gate film layer pattern exposure, development, post-baking → gate film layer pattern etching → photoresist stripping.
The deposition process of the bottom gate passivation film layer and the top gate passivation film layer is the same as that of the bottom gate passivation film layer in example 1, and details are not repeated here.
And 2, forming a pattern comprising the gate insulating layer 4, the semiconductor layer 5 and the ohmic contact layer 6 by adopting a one-step composition process.
In the step, cleaning before film forming → gate insulating layer deposition → semiconductor film layer and ohmic contact film layer deposition → photoresist coating → semiconductor film layer and ohmic contact film layer pattern exposure and development, post-baking → semiconductor film layer and ohmic contact film layer dry etching → photoresist stripping.
And 3, forming a graph comprising a bottom source drain passivation layer, a source electrode, a drain electrode and a top source drain passivation layer by adopting a one-step composition process.
In the step, bottom source and drain passivation film layer deposition (aluminum passivation formation) → source and drain film layer deposition (Cu: copper) → top source and drain passivation film layer deposition (aluminum passivation formation) → photoresist coating → source and drain film layer pattern exposure development, post-baking → source and drain film layer etching → ohmic contact film layer dry etching → photoresist stripping.
The deposition process of the bottom source-drain passivation film layer is the same as that of the bottom gate passivation film layer, and is not described herein again.
Thus, the thin film transistor is manufactured, and the gate line and the data line are formed in advance to facilitate the wiring of the array substrate.
And 4, forming a pattern comprising the passivation layer and the electrode contact through hole thereof by adopting a one-step composition process.
In the step, passivation film layer deposition → photoresist coating → electrode contact via pattern exposure, development, post-baking → electrode contact via etching → photoresist stripping.
And 5, forming a pattern comprising the pixel electrode by adopting a one-time composition process.
In this step, the deposition of the pixel electrode film layer (ITO or IZO: indium tin oxide or indium zinc oxide) → photoresist coating → pixel electrode film layer pattern exposure development, post-baking → pixel electrode film layer etching → photoresist stripping → annealing.
In this embodiment, the pattern of the specific structure of the array substrate may refer to the pattern of the corresponding structure prepared by the array substrate in embodiment 1, and the specific process in the array substrate preparation method may refer to the corresponding process in the array substrate preparation method in embodiment 1, which is not described herein again.
In the thin film transistors in embodiments 1 to 4, the semiconductor layers are all made of amorphous silicon (a-Si) as an example, but it should be understood that the semiconductor layers may also be formed of an oxide or a low-temperature polysilicon material, and the specific structure and the manufacturing process are the same as those of the semiconductor layers in embodiments 1 to 4, and are not described herein again.
In the thin film transistors and the corresponding array substrates of embodiments 1 to 4, preferably, copper is used as an electrode or lead material, and a passivation layer formed by aluminum passivation is correspondingly used as an isolation passivation layer material between the electrode or lead and an adjacent layer, so that while higher conductivity is maintained, the adhesion between copper and the substrate is improved, and the falling off is prevented; on the other hand, the diffusion of copper ions to the silicon-containing film layer can be prevented, and the switching characteristic of the thin film transistor is ensured. Therefore, the process difficulty of applying the existing pure copper electrode to the array substrate can be effectively improved, and the problem that the existing array substrate cannot adopt the pure copper electrode material for mass production is solved.
Example 5:
a display device comprising the array substrate as exemplified in any of embodiments 1 to 4.
The display device may be: the display device comprises any product or component with a display function, such as a liquid crystal panel, electronic paper, an OLED panel, a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
The thin film transistor in the array substrate has good switching property, so that the display device has good display quality.
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.
Claims (14)
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