CN104409502A - Power transistor and manufacturing method thereof - Google Patents

Abstract

The present invention provides a power transistor and a manufacturing method thereof, by adding a first epitaxial layer that runs through the entire first conductivity type and extends deep into the second epitaxial layer of the first conductivity type in the middle of the drift region of the first conductivity type. groove structure, and filling the polysilicon layer in the deep groove structure, the drain terminal potential of the conventional LDMOS can be directly led to the back of the entire structure, and formed between the second epitaxial layer of the first conductivity type and the polysilicon layer An equipotential body; Compared with the existing planar LDMOS, the power transistor of the present invention not only has the advantages of wide frequency range, good linearity, good durability and high breakdown voltage of the traditional planar LDMOS, but also Various performances of the device are further improved, such as reducing the on-resistance of the device, etc.; the overall size of the transistor is small and does not occupy additional valuable space of the semiconductor wafer.

Description

Power transistor and manufacturing method thereof

technical field

The invention relates to the field of semiconductor process manufacturing, in particular to a power transistor and a manufacturing method thereof.

Background technique

Due to the advantages of LDMOS (Lateral Diffused MOS, laterally diffused MOS) transistors, which can provide a wide frequency range, high efficiency, good durability and high breakdown voltage, they have been widely used in high-voltage transistors, switching regulators and other fields.

An existing LDMOS transistor is shown in FIG. 1 , and FIG. 1 is a schematic diagram of a vertical cross-sectional structure of an LDMOS transistor in the prior art. It can be seen from FIG. 1 that the LDMOS transistor at least includes: an epitaxial layer 10 of a first conductivity type located on a semiconductor substrate (not shown); a LOCOS (Local Oxidation ofSilicon, local silicon oxidation isolation region) 14; the gate 15 located on the LOCOS 14 and the epitaxial layer 10 of the first conductivity type; the drain region 11 located between the LOCOS 14; the LOCOS 14 located away from the drain The body region 12 of the second conductivity type in the epitaxial layer 10 of the first conductivity type on the side of the region 11; the body region lead-out region 13 and the source region 19 located in the body region 12 of the second conductivity type, so The body region lead-out region 13 is short-circuited with the source region 19; the dielectric layer 16 covering the body region lead-out region 13, source region 19, gate 15, LOCOS14 and drain region 11; through the dielectric layer 16 The metal wire 17 connected to the lead-out region 13 of the body region, and the source electrode 18 located on the dielectric layer 16 and connected to the metal wire 17 . The LDMOS transistor has a planar structure, the source region 19 and the drain region 11 are located near the same surface of the epitaxial layer 10 of the first conductivity type, and the current in the LDMOS transistor is almost conducted along the lateral dimension. The first conductivity type is N type, and the second conductivity type is P type; the first conductivity type is P type, and the second conductivity type is N type.

In the LDMOS transistor in the prior art, in order to improve the source-drain breakdown voltage BVdss (the highest voltage that the drain can withstand), the LDMOS transistor is provided with the LOCOS14, and the source-drain breakdown The higher the voltage BVdss is, the greater the maximum rated operating voltage of the LDMOS is. However, after the LOCOS 14 is introduced, while the source-drain breakdown voltage BVdss is increased, the on-resistance (Ron) between the source-drain is also increased. On-resistance is a parameter that represents the driving current capability per unit area, and for LDMOS transistors, its value should be as small as possible.

In an alternative design, the LDMOS transistor has a drain contact along the backside of the semiconductor substrate. The LDMOS transistor with a drain contact on the backside of the semiconductor substrate has a sequence structure of a horizontally arranged source, a polysilicon gate, a lightly doped drain (LDD) and a sinker region. On the drain side of the transistor, the LDD region typically extends laterally for high voltages, which results in a larger overall size of the device. In addition, the sinker region needs to be sufficiently diffused to reach the backside drain, and such deep diffusion tends to take up valuable space in additional semiconductor wafers due to side diffusion and misalignment.

Therefore, it is very necessary to provide an improved LDMOS transistor.

Contents of the invention

In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a power transistor and its manufacturing method, which is used to solve the problem of the increase in the on-resistance of the transistor caused by the introduction of LOCOS in the prior art of the planar LDMOS transistor and On the drain side of the existing vertical power transistor, the LDD region extends laterally to obtain a high voltage, resulting in a larger overall size of the device; the sinker region needs to be sufficiently diffused to reach the back drain, due to side diffusion and misalignment, and The resulting problem easily consumes additional semiconductor area.

To achieve the above object and other related objects, the present invention provides a power transistor, the power transistor at least includes: a first epitaxial layer of the first conductivity type as the drain region of the power transistor; a second epitaxial layer of the first conductivity type The epitaxial layer is located on the first epitaxial layer of the first conductivity type; the drift region of the first conductivity type is located in the second epitaxial layer of the first conductivity type; the deep groove structure is connected with the first conductivity type The drift region is laterally adjacent, the deep trench structure runs through the entire second epitaxial layer of the first conductivity type and extends to the inside of the first epitaxial layer of the first conductivity type; the deep trench structure is filled with polysilicon layer; a source region located in the second epitaxial layer of the first conductivity type and separated from the drift region of the first conductivity type and the deep trench structure.

Preferably, the shape of the longitudinal section of the deep groove structure is a right-angled U-shape or a U-shape with chamfered corners.

Preferably, the first epitaxial layer of the first conductivity type is a heavily doped epitaxial layer; the second epitaxial layer of the first conductivity type is a lightly doped epitaxial layer; the drift region of the first conductivity type is lightly doped doping drift region; the polysilicon layer is heavily doped polysilicon layer.

Preferably, the power transistor further includes a lightly doped body region of the second conductivity type, the lightly doped body region of the second conductivity type is located in the second epitaxial layer of the first conductivity type, and is connected to the The drift region of the first conductivity type is separated from the deep trench structure; the source region is located in the lightly doped body region of the second conductivity type.

Preferably, the power transistor further includes a gate and LOCOS, the LOCOS is located on the second epitaxial layer of the first conductivity type between the deep trench structure and the source region, and the gate At least one part is located on the LOCOS, and another part is directly located on the second epitaxial layer of the first conductivity type.

The present invention also provides a power device, which includes at least two mirror-symmetrically arranged cells in the horizontal direction, and each cell includes a power transistor as described in the above solution.

Preferably, two adjacent cells share the deep groove structure, and the respective drift regions of the two cells are respectively located on both sides of the deep groove structure.

The present invention provides a method for manufacturing a power transistor, and the method for manufacturing the power transistor includes the following steps:

providing a wafer comprising a first epitaxial layer of a first conductivity type and a second epitaxial layer of the first conductivity type on the first epitaxial layer of the first conductivity type;

A deep groove is formed in the first epitaxial layer of the first conductivity type and the second epitaxial layer of the first conductivity type, and the deep groove runs through the entire second epitaxial layer of the first conductivity type and extends to the In the first epitaxial layer of the first conductivity type;

Filling the deep trench with a polysilicon layer;

forming a drift region of a first conductivity type in the second epitaxial layer of one conductivity type next to the deep trench, and the drift region of the first conductivity type is laterally adjacent to the deep trench;

A body region of a second conductivity type is formed, a source region is formed in the body region of the second conductivity type, and the body region is separated from the drift region of the first conductivity type and the deep trench.

Preferably, the manufacturing method of the power transistor further includes:

forming LOCOS with a certain interval on the second epitaxial layer of the first conductivity type; the LOCOS is located on both sides of the deep groove;

forming a gate on the LOCOS and the second epitaxial layer of the first conductivity type, at least a part of the gate is located on the LOCOS, and another part is directly located on the second epitaxial layer of the first conductivity type .

Preferably, after the polysilicon layer is filled in the deep groove, it further includes planarizing the filled polysilicon layer, so that the upper surface of the polysilicon layer and the upper surface of the second epitaxial layer of the first conductivity type The step of leveling the surface and the step of ion doping the polysilicon layer so that the polysilicon layer becomes a heavily doped polysilicon layer.

Preferably, the first epitaxial layer of the first conductivity type is a heavily doped epitaxial layer; the second epitaxial layer of the first conductivity type is a lightly doped epitaxial layer; the drift region of the first conductivity type is lightly doped Doping the drift region; the body region is a lightly doped body region.

As mentioned above, the power transistor of the present invention has the following beneficial effects: the power transistor of the present invention adds a first epitaxial layer that runs through the entire first conductivity type in the middle of the drift region of the first conductivity type and extends to the first conductivity type. The deep groove structure in the second epitaxial layer, and fill the polysilicon layer in the deep groove structure, can directly lead the drain terminal potential of the conventional power transistor to the back of the whole structure, in the second conductivity type An equipotential body is formed between the two epitaxial layers and the polysilicon layer; the power transistor of the present invention is a vertical power transistor device. Compared with the existing planar LDMOS, the vertical power transistor of the present invention not only has the frequency range of the traditional planar LDMOS The advantages of wide, good linearity, good durability and high breakdown voltage have further improved the performance of the device, such as reducing the on-resistance (Ron) of the device; the overall size of the transistor is small, And it will not occupy extra valuable space of the semiconductor chip.

Description of drawings

FIG. 1 is a schematic diagram of a vertical cross-sectional structure of a power transistor in the prior art.

FIG. 2 is a schematic diagram of a vertical cross-sectional structure of a power transistor provided in Embodiment 1 of the present invention.

FIG. 3 shows a flow chart of a method for manufacturing a power transistor provided in Embodiment 3 of the present invention.

FIG. 4 to FIG. 8 are schematic longitudinal cross-sectional structural diagrams in each step of the manufacturing method of the power transistor provided in the third embodiment of the present invention.

Component designation description

10 The epitaxial layer of the first conductivity type

11 Drain area

12 Body region of the second conductivity type

13 Body region lead-out region

14 LOCOS

15 grid

16 dielectric layer

17 metal wire

18 source electrode

19 source area

200 The first epitaxial layer of the first conductivity type

201 The second epitaxial layer of the first conductivity type

202 Drift region of the first conductivity type

203 deep groove

204 polysilicon layer

205 Body region lead-out region

206 LOCOS

207 Body region of the second conductivity type

208 grid

209 medium layer

210 metal wire

211 source electrode

212 source area

Detailed ways

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

See Figures 2 through 8. It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic concept of the present invention, although only the components related to the present invention are shown in the diagrams rather than the number, shape and Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the component layout type may also be more complicated. The term "adjacent" means that there is direct contact between at least a portion of the outer surfaces of two structures.

Embodiment one

Please refer to FIG. 2 , the present invention provides a power transistor, the power transistor at least includes: a first epitaxial layer 200 of the first conductivity type as the drain region of the power transistor; a second epitaxial layer of the first conductivity type 201, located on the first epitaxial layer 200 of the first conductivity type; a drift region 202 of the first conductivity type, located in the second epitaxial layer 201 of the first conductivity type; a deep trench structure (not shown), Adjacent to the drift region 202 of the first conductivity type laterally, the deep trench structure runs through the entire second epitaxial layer 201 of the first conductivity type and extends to the inside of the first epitaxial layer 200 of the first conductivity type The polysilicon layer 204 is filled in the deep trench structure; the body region lead-out region 205 and the source region 212 are located in the second epitaxial layer 201 of the first conductivity type, and are connected to the drift region 202 of the first conductivity type separated from the deep groove structure.

Specifically, the deep groove structure is a vertical groove, and the shape of the longitudinal section of the deep groove structure may be a right-angled U-shape or a U-shape with chamfered corners.

Specifically, the deep trench structure is located in the middle of the drift region 202 of the first conductivity type.

Specifically, the sidewall of the polysilicon layer 204 is in direct and sufficient contact with the drift region 202 of the first conductivity type, and the upper surface of the polysilicon layer 204 is in contact with the upper surface of the second epitaxial layer 201 of the first conductivity type. flush.

Specifically, the first epitaxial layer 200 of the first conductivity type is a heavily doped epitaxial layer; the second epitaxial layer 201 of the first conductivity type is a lightly doped epitaxial layer; the drift region of the first conductivity type 202 is a lightly doped drift region; the polysilicon layer 204 is a heavily doped polysilicon layer. The heavy doping refers to doping with an ion doping dose greater than 1×10 ¹⁷ atom/cm ² ; the low doping refers to doping with an ion doping dose less than 1×10 ¹⁵ atom/cm ² .

Specifically, the power transistor further includes a lightly doped body region 207 of the second conductivity type, the lightly doped body region 207 of the second conductivity type is located in the second epitaxial layer 201 of the first conductivity type, and It is separated from the drift region 202 of the first conductivity type and the deep trench structure; the body region lead-out region 205 and the source region 212 are located in the lightly doped body region 207 of the second conductivity type.

Specifically, the power transistor further includes a gate 208 and a LOCOS 206, and the LOCO, 206 is located on the second epitaxial layer 201 of the first conductivity type between the deep trench structure and the source region 212, so At least a part of the gate 208 is located on the LOCOS 206 , and another part is directly located on the second epitaxial layer 201 of the first conductivity type.

Specifically, the body lead-out region 205 is short-circuited with the source region 212 of the power transistor. The body lead-out region 205 is located on a side of the source region 212 away from the LOCOS 206 . Such a design structure can lead out the source region 212 and the body region 207 of the second conductivity type at the same time.

Specifically, the power transistor further includes a dielectric layer 209 covering the body lead-out region 205, the source region 212, the gate 208, the LOCOS 206 and the drift region 202 of the first conductivity type, and the dielectric layer 209 simultaneously contacts Covering the top of the polysilicon layer 204; the metal wiring 210 penetrating through the dielectric layer 209 is formed in the dielectric layer 209, and the metal wiring 210 is connected to the body region lead-out region 205; the dielectric layer 209 A source electrode 211 is formed on it, and the source electrode 211 is connected to the metal wiring 210 to lead out the body region lead-out region 205 and the source region 212 .

By adding a deep trench structure in the middle of the drift region 202 of the first conductivity type that runs through the entire first epitaxial layer 200 of the first conductivity type and extends into the second epitaxial layer 201 of the first conductivity type, and in the deep trench The polysilicon layer 204 is filled in the structure, and the sidewall of the polysilicon layer 204 is in direct contact with the drift region 202 of the first conductivity type, so that the drain terminal potential of a conventional power transistor can be directly led to the back of the entire structure. An equipotential body is formed between the second epitaxial layer 201 of the first conductivity type and the polysilicon layer 204; the power transistor of the present invention is a vertical power transistor device, compared with the existing planar LDMOS, the vertical power transistor of the present invention It not only has the advantages of wide frequency range, good linearity, good durability and high breakdown voltage of traditional planar LDMOS, but also further improves the performance of the device, such as reducing the on-resistance (Ron) of the device, etc.; The overall size of the transistors is small and does not take up valuable additional space on the semiconductor wafer.

Specifically, the first conductivity type may be N type, and at this time the second conductivity type is P type.

Specifically, the first conductivity type may be P-type, and at this time, the second conductivity type is N-type.

It should be noted that, the above-mentioned power transistor is formed on the front side of the semiconductor substrate (not shown), and the drain electrode (not shown) of the power transistor is also formed on the back side of the semiconductor substrate.

Embodiment two

The present invention also provides a power device, which includes at least two mirror-symmetrically arranged cells in the horizontal direction, and each cell includes a power transistor as described in Embodiment 1.

Specifically, two adjacent cells share the deep groove structure, and the respective drift regions of the two cells are respectively located on both sides of the deep groove structure.

Embodiment Three

Referring to FIG. 3 to FIG. 8, the present invention also provides a method for manufacturing a power transistor, the method for manufacturing a power transistor at least includes the following steps:

providing a wafer comprising a first epitaxial layer 200 of a first conductivity type and a second epitaxial layer 201 of a first conductivity type located on the first epitaxial layer 200 of a first conductivity type;

A deep groove 203 is formed in the first epitaxial layer 200 of the first conductivity type and the second epitaxial layer 201 of the first conductivity type, and the deep groove 203 runs through the entire second epitaxial layer of the first conductivity type 201, extending into the first epitaxial layer 200 of the first conductivity type;

filling the polysilicon layer 204 in the deep groove 203;

A drift region 202 of the first conductivity type is formed in the second epitaxial layer 201 of the first conductivity type next to the deep trench 203, and the drift region 202 of the first conductivity type is laterally adjacent to the deep trench 203 .

A body region 207 of the second conductivity type is formed, and a body region lead-out region 205 and a source region 212 are formed in the body region 207 of the second conductivity type, and the body region 207 and the drift region of the first conductivity type 202 and the deep groove 203 are separated.

Execute step S1, please refer to step S1 in FIG. 3 and FIG. 4, provide a wafer, the wafer includes the first epitaxial layer 200 of the first conductivity type and the epitaxial layer on the first epitaxial layer 200 of the first conductivity type A second epitaxial layer 201 of the first conductivity type.

Specifically, the wafer further includes a substrate of the first conductivity type, and the first epitaxial layer 200 of the first conductivity type is formed on the substrate of the first conductivity type.

Specifically, the first epitaxial layer 200 of the first conductivity type is a heavily doped epitaxial layer; the second epitaxial layer 201 of the first conductivity type is a lightly doped epitaxial layer.

Execute step S2, please refer to step S2 in FIG. 3 and FIG. 5 to FIG. 6, forming deep grooves 203 in the first epitaxial layer 200 of the first conductivity type and the second epitaxial layer 201 of the first conductivity type , the deep groove 203 runs through the entire second epitaxial layer 201 of the first conductivity type, and extends into the first epitaxial layer 200 of the first conductivity type.

The specific steps of forming the deep groove 203 are as follows: firstly, a photoresist layer having an opening is formed on the surface of the second epitaxial layer 201 of the first conductivity type, and the opening corresponds to the region of the deep groove 203 ; Next, use a dry etching process, a wet etching process, or a combination of dry etching and wet etching on the second epitaxial layer 201 of the first conductivity type and the second epitaxial layer 201 of the first conductivity type. The deep groove 203 is formed in an epitaxial layer 200; finally, the photoresist layer is removed.

Specifically, the shape of the longitudinal section of the formed deep groove 203 may be a right-angled U-shape or a U-shape with chamfered corners.

It should be noted that, before forming the deep trench 203, a step of forming LOCOS 206 with a certain interval on the second epitaxial layer 201 of the first conductivity type is also included; the LOCOS 206 is located in the deep trench 206 sides. The process flow of forming the LOCOS 206 on the second epitaxial layer 201 of the first conductivity type is as follows: First, a thin silicon oxide layer is formed on the surface of the second epitaxial layer 201 of the first conductivity type as a pad oxide layer , and deposit a silicon nitride layer; secondly, protect the active area with photoresist; thirdly, dry etch the silicon nitride without photoresist protection area, the pad oxide layer and the first conductivity type at a certain depth the second epitaxial layer 201 to form a trench; fourth, the structure is sent into a hot furnace tube to oxidize silicon into silicon oxide to form a field oxide layer (Field Oxide, referred to as FOX), that is, to form a local silicon oxidation isolation region (LOCOS); finally, wet etching to remove the pad oxide layer and the silicon nitride layer on the surface of the second epitaxial layer 201 of the first conductivity type.

Step S3 is executed, please refer to step S3 in FIG. 3 and FIG. 7 , and the polysilicon layer 204 is filled in the deep trench 203 .

Specifically, the polysilicon layer 204 can be grown in the deep groove 203 , or the polysilicon layer 204 can be deposited in the deep groove 203 by physical vapor deposition or chemical vapor deposition.

Specifically, after filling the polysilicon layer 204 in the deep groove 203, it also includes performing planarization treatment on the filled polysilicon layer 204, so that the upper surface of the polysilicon layer 204 and the first conductivity type The step of leveling the upper surface of the second epitaxial layer 201 and the step of ion doping the polysilicon layer 204 so that the polysilicon layer 204 becomes a heavily doped polysilicon layer.

Execute step S4, please refer to step S4 in FIG. A drift region 202 of the type adjoins said deep trench 203 laterally.

Specifically, the drift region 202 of the first conductivity type surrounds the deep trench 203 filled with the polysilicon layer 204, and makes the deep trench 203 filled with the polysilicon layer 204 located in the first conductivity type the middle of the drift region 202 .

Specifically, the drift region of the first conductivity type is a lightly doped drift region.

Specifically, the polysilicon layer 204 fills the entire deep trench 203 , and the sidewall of the polysilicon layer 204 is in direct and full contact with the drift region 202 of the first conductivity type.

Execute step S5, please refer to step S5 of FIG. 3 and FIG. 8, form a body region 207 of the second conductivity type, and form a body region lead-out region 205 and a source region 212 in the body region 207 of the second conductivity type, and The body region 207 is separated from the drift region 202 of the first conductivity type and the deep trench 203 .

Specifically, the body lead-out region 205 is short-circuited with the source region 212 of the power transistor.

Specifically, a step of forming a gate 208 on the LOCOS 206 and the second epitaxial layer 201 of the first conductivity type is also included. At least a part of the gate 208 is located on the LOCOS 206 , and another part is directly located on the second epitaxial layer 201 of the first conductivity type.

Specifically, it also includes forming a dielectric layer 209 on the body region lead-out region 205, the source region 212, the gate 208, the LOCOS 206 and the drift region 202 of the first conductivity type, and the dielectric layer 209 corresponds to the Forming a through hole at the position of the lead-out region 205 of the body region, filling the through hole with a metal wire 210, depositing a metal layer connected to the metal wire 210 on the dielectric layer 209 to form a source electrode 211 ; The dielectric layer 209 contacts and covers the top of the polysilicon layer 204 at the same time.

Specifically, the body region 207 of the second conductivity type is a lightly doped body region.

Specifically, the heavy doping mentioned above refers to the doping with an ion doping dose greater than 1×10 ¹⁸ atom/cm ³ ; the high doping refers to the doping with an ion doping dose less than 1×10 ¹⁶ atom/cm ³ doping.

Specifically, the first conductivity type may be N type, and at this time the second conductivity type is P type.

Specifically, the first conductivity type may be P-type, and at this time, the second conductivity type is N-type.

It should be noted that the manufacturing method of the power transistor further includes thinning the wafer and depositing a metal layer on the back of the wafer to form the drain electrode (not shown) of the power transistor. Step, the material of the drain electrode is one or more of Ti, Ni and Ag.

To sum up, the present invention provides a power transistor and its manufacturing method, by adding a first epitaxial layer that runs through the entire first conductivity type in the middle of the drift region of the first conductivity type and extends to the second epitaxial layer of the first conductivity type. The deep trench structure in the epitaxial layer, and filling the polysilicon layer in the deep trench structure can directly lead the drain terminal potential of the conventional LDMOS to the back of the entire structure, and the second epitaxial layer of the first conductivity type and the An equipotential body is formed between the polysilicon layers; compared with the existing planar LDMOS, the power transistor of the present invention not only has a wide frequency range, good linearity, improved durability and breakdown of the traditional planar LDMOS The advantage of increasing the voltage further improves the performance of the device, such as reducing the on-resistance (Ron) of the device; the overall size of the transistor is small, and does not occupy additional valuable space on the semiconductor wafer.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention shall still be covered by the claims of the present invention.

Claims (11)

1. a power transistor, is characterized in that: described power transistor comprises:

First epitaxial loayer of the first conduction type, as the drain region of described power transistor;

Second epitaxial loayer of the first conduction type, is positioned on the first epitaxial loayer of described first conduction type;

The drift region of the first conduction type, is positioned at the second epitaxial loayer of described first conduction type;

Deep groove structure, laterally adjacent with the drift region of described first conduction type, described deep groove structure runs through the second epitaxial loayer of whole described first conduction type and extends to the inside of the first epitaxial loayer of described first conduction type; Polysilicon layer is filled with in described deep groove structure;

Source region, is positioned at the second epitaxial loayer of described first conduction type, and separates with the drift region of described first conduction type and described deep groove structure.

2. power transistor according to claim 1, is characterized in that: the shape of described deep groove structure longitudinal section is that right angle is U-shaped or have the U-shaped of chamfering.

3. power transistor according to claim 1, is characterized in that: the first epitaxial loayer of described first conduction type is attached most importance to doped epitaxial layer; Second epitaxial loayer of described first conduction type is light dope epitaxial loayer; The drift region of described first conduction type is light dope drift region; Described polysilicon layer is heavily doped polysilicon layer.

4. power transistor according to claim 1, it is characterized in that: described power transistor also comprises the light dope tagma of the second conduction type, the light dope tagma of described second conduction type is positioned at the second epitaxial loayer of described first conduction type, and separates with the drift region of described first conduction type and described deep groove structure; Described source region is positioned at the light dope tagma of described second conduction type.

5. power transistor according to claim 1, it is characterized in that: described power transistor also comprises grid and LOCOS, on second epitaxial loayer of described first conduction type of described LOCOS between described deep groove structure and described source region, described grid be positioned on described LOCOS at least partially, another part is located immediately on the second epitaxial loayer of described first conduction type.

6. a power device, is characterized in that, described power device comprises the cellular of at least two Mirror Symmetry arrangements in the horizontal direction, and each described cellular comprises a power transistor as described in any one of claim 1 to 5.

7. power device according to claim 6, is characterized in that: adjacent two described cellulars share described deep groove structure, and two described cellular drift regions separately lay respectively at described deep groove structure both sides.

8. a manufacture method for power transistor, is characterized in that, the manufacture method of described power transistor comprises the following steps:

There is provided a wafer, described wafer comprises the first epitaxial loayer of the first conduction type and is positioned at the second epitaxial loayer of the first conduction type on the first epitaxial loayer of described first conduction type;

In the first epitaxial loayer of described first conduction type and the second epitaxial loayer of described first conduction type, form deep trouth, described deep trouth runs through the second epitaxial loayer of whole described first conduction type, extends in the first epitaxial loayer of described first conduction type;

Polysilicon layer is filled in described deep trouth;

In the second epitaxial loayer of described first conduction type on described deep trouth side, form the drift region with the first conduction type, the drift region of described first conduction type and described deep trouth are laterally adjacent;

Form the tagma of the second conduction type, and form source region in the tagma of described second conduction type, and the drift region of described tagma and described first conduction type and described deep trouth separate.

9. power transistor manufacture method according to claim 8, is characterized in that: the manufacture method of described power transistor also comprises:

Second epitaxial loayer of described first conduction type is formed the LOCOS with certain intervals; Described LOCOS is positioned at the both sides of described deep trouth;

Second epitaxial loayer of described LOCOS and described first conduction type forms grid, described grid be positioned on described LOCOS at least partially, another part is located immediately on the second epitaxial loayer of described first conduction type.

10. the manufacture method of power transistor according to claim 8, it is characterized in that: fill polysilicon layer in described deep trouth after, the described polysilicon layer also comprised filling carries out planarization, make the upper surface of the described polysilicon layer step concordant with the upper surface of the second epitaxial loayer of described first conduction type and ion doping is carried out to described polysilicon layer, making described polysilicon layer become the step of heavily doped polysilicon layer.

The manufacture method of 11. power transistors according to claim 8, is characterized in that: the first epitaxial loayer of described first conduction type is attached most importance to doped epitaxial layer; Second epitaxial loayer of described first conduction type is light dope epitaxial loayer; The drift region of described first conduction type is light dope drift region; Described tagma is light dope tagma.