CN104409436B - It is formed at and trim unit on wafer - Google Patents
It is formed at and trim unit on wafer Download PDFInfo
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- CN104409436B CN104409436B CN201410691729.8A CN201410691729A CN104409436B CN 104409436 B CN104409436 B CN 104409436B CN 201410691729 A CN201410691729 A CN 201410691729A CN 104409436 B CN104409436 B CN 104409436B
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- pad
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- gasket construction
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- 238000010276 construction Methods 0.000 claims abstract description 40
- 239000000463 material Substances 0.000 claims abstract description 11
- 238000009413 insulation Methods 0.000 claims abstract description 7
- 239000002184 metal Substances 0.000 claims description 26
- 229910052751 metal Inorganic materials 0.000 claims description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 24
- 229920005591 polysilicon Polymers 0.000 claims description 23
- 239000013078 crystal Substances 0.000 claims description 13
- 239000000523 sample Substances 0.000 claims description 8
- 239000000758 substrate Substances 0.000 abstract description 10
- 230000004888 barrier function Effects 0.000 abstract description 8
- 238000009966 trimming Methods 0.000 abstract description 7
- 101100123053 Arabidopsis thaliana GSH1 gene Proteins 0.000 description 11
- 101100298888 Arabidopsis thaliana PAD2 gene Proteins 0.000 description 11
- 101150092599 Padi2 gene Proteins 0.000 description 11
- 102100035735 Protein-arginine deiminase type-2 Human genes 0.000 description 11
- 101000590281 Homo sapiens 26S proteasome non-ATPase regulatory subunit 14 Proteins 0.000 description 8
- 101001114059 Homo sapiens Protein-arginine deiminase type-1 Proteins 0.000 description 8
- 102100023222 Protein-arginine deiminase type-1 Human genes 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910002056 binary alloy Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The present invention provide a kind of be formed on wafer trim unit, it includes：First pad；Second pad；It is connected to the fuse body between the first pad and the second pad, described fuse body includes the first guidance part being connected with the first pad, the second guidance part being connected with the second pad and the fuse part being connected between the first guidance part and the second guidance part, the width of each guidance part is become narrow gradually to fuse part by pad, and the width of fuse part is less than or equal to the width of described guidance part narrowest part；Gasket construction area below described fuse part, this gasket construction area includes the multiple floor being formed at differing heights on wafer, each floor in gasket construction area includes the grid area at multiple intervals and is filled in insulation layer between grid area, and the material in the grid area of the different layers in gasket construction area is different.This gasket construction area contributes to forming barrier layer in substrate and the fuse part trimming unit between, so can prevent from trimming the substrate short circuit of unit and wafer, improve the yield of chip.
Description
【Technical field】
The present invention relates to technical field of semiconductors, particularly to a kind of be formed on wafer trim unit.
【Background technology】
At present through frequently with metal fuse as trimming unit.By its unblown and next numeral logic of fusing
" 0 " and logical one.Each trims unit and represents a binary data, and multiple units that trim can represent multidigit binary system
Data.Some analog quantitys of analog circuit can be changed using these binary data.For example, before being trimmed by measurement
Reference voltage magnitude of voltage, can calculate needs to fuse those to trim unit accurate to realize reference voltage.Typically pass through
Fuse two ends making alive produces larger current come the fuse that to fuse.Because added electric current is generally very big, exceed hundreds of milliampere, fuse vapour
Easily crack the insulating barrier of fuse bottom during change, lead to and substrate short circuit, such chip may lose efficacy.This reason can lead to necessarily
Yield loss, be necessary existing metal fuse wire structure is improved to improve chip yield, reduce fraction defective.
It is thus desirable to proposing a kind of improvement project to overcome problems of the prior art.
【Content of the invention】
It is an object of the invention to provide one kind trims unit, it is not easy the substrate short circuit with wafer when being blown,
Improve the yield of chip.
In order to solve the above problems, the present invention provide a kind of be formed on wafer trim unit, it includes：First pad
Piece；Second pad；It is connected to the fuse body between the first pad and the second pad, described fuse body includes being connected with the first pad
The first guidance part, the second guidance part being connected with the second pad and be connected to molten between the first guidance part and the second guidance part
Silk portion, the width of each guidance part is become narrow gradually to fuse part by pad, and the width of fuse part is less than or equal to described guiding
The width of portion narrowest part；Gasket construction area below described fuse part, this gasket construction area includes being formed on wafer
In multiple layers of differing heights, each floor in gasket construction area include multiple intervals grid area and be filled in grid area it
Between insulation layer, the material in the grid area of the different layers in gasket construction area is different.
Further, the first pad, the second pad, fuse body are formed by the metal level being located on wafer.
Further, each floor in gasket construction area be the first polysilicon layer, the second polysilicon layer, first pad be located gold
Belong to one of lower metal layer of layer, accordingly, the material in the grid area of each floor in gasket construction area is the first polysilicon,
One of second polysilicon, metal.
Further, the first pad place metal level is the top layer metallic layer on wafer, the difference in gasket construction area
Projection non-overlapping copies on described crystal column surface for the grid area in floor.
Further, projection of shape on described crystal column surface for the grid area of each floor in gasket construction area be square,
One of triangle, pentagon or hexagon.
Further, view field on described crystal column surface for the gasket construction area comprises described fuse part and part guides
View field on described crystal column surface for the portion.
Further, the current potential in each grid area of each floor in gasket construction area is to suspend.
Further, described trim unit and need to be blown when, first probe is contacted with the first pad, by second
Individual probe is contacted with the second pad, applies a predetermined voltage between two probes, and the electric current now being formed in fuse part makes
This fuse part fuses.First pad is connected with one of the power end on described wafer or device connection end, the second pad
Piece is connected with one of another power end on described wafer or another device connection end.Described device is resistance.
Compared with prior art, the unit that trims in the present invention has gasket construction area below described fuse part,
This gasket construction area contribute to formed barrier layer in substrate and the fuse part trimming unit between, so can prevent from trimming unit
With the substrate short circuit of wafer, improve the yield of chip.
【Brief description】
In order to be illustrated more clearly that the technical scheme of the embodiment of the present invention, below will be to required use in embodiment description
Accompanying drawing be briefly described it should be apparent that, drawings in the following description are only some embodiments of the present invention, for this
For the those of ordinary skill of field, without having to pay creative labor, other can also be obtained according to these accompanying drawings
Accompanying drawing.Wherein：
Fig. 1 be the present invention in trim unit structure chart in one embodiment；
Fig. 2 is that the vertical view partial enlargement trimming unit fuse body portion in one embodiment in the present invention is illustrated
Figure.
【Specific embodiment】
Understandable for enabling the above objects, features and advantages of the present invention to become apparent from, below in conjunction with the accompanying drawings and specifically real
The present invention is further detailed explanation to apply mode.
" embodiment " or " embodiment " referred to herein refers to may be included at least one implementation of the present invention
Special characteristic, structure or characteristic." in one embodiment " that different places occur in this manual not refers both to same
Individual embodiment, is not single or optionally mutually exclusive with other embodiment embodiment.Unless stated otherwise, herein
In connection, be connected, connect represent that the word being electrically connected with all represents and is directly or indirectly electrical connected.
Fig. 1 describes to trim unit 100 structure chart in one embodiment in the present invention.Described trim unit 100
It is formed on wafer, the described unit that trims includes the first pad PAD1, the second pad PAD2, is connected to the first pad PAD1 and
Fuse body between two pad PAD2.
Described fuse body include the first guidance part 11 being connected with the first pad PAD1, be connected with the second pad PAD2
Two guidance parts 12 and the fuse part 13 being connected between the first guidance part 11 and the second guidance part 12.The width of the first guidance part 11
Become narrow gradually to fuse 13 by the first pad PAD1, the width of the second guidance part 12 is by the second pad PAD2 to fuse part 13 gradually
Narrow, and the width of fuse part 13 is less than or equal to the width of described guidance part 11 and 12 narrowest parts.
In one embodiment, the first pad PAD1 is connected with one of the power end on described wafer or a device
End is connected, and the second pad PAD2 is connected with one of another power end on described wafer or another device connection end.
Described device can be resistance, now can adjust the size of resistance by trimming unit.
When needing to trim unit 100 described in fusing, first probe is contacted with the first pad PAD1, second is visited
Pin is contacted with the second pad PAD2, applies a predetermined voltage between two probes, and high current can converge on fuse part 13, its
Width is the narrowest, highest current density, so being blown.In the prior art, can vaporize after the fusing of this fuse part 13 and crack molten
Insulating barrier under silk portion 13, the substrate short circuit with wafer, this short circuit can lead to (normally work from pad P AD1 and PAD2
When have voltage signal) to substrate electric leakage, the quiescent dissipation of increasing circuit, the voltage letter of pad P AD1 and PAD2 can be led to simultaneously
Number exception.
In order to solve the above problems, as shown in Fig. 2 trim unit 100 in the present invention also including positioned at described fuse part 13
The gasket construction area 14 of lower section.This gasket construction area 14 includes the multiple floor being formed at differing heights on wafer, and this liner is tied
Each floor in structure area 14 includes the grid area at multiple intervals and is filled in the insulation layer between grid area.Gasket construction area 14
The grid area of different layers material different.
In one embodiment, the first pad PAD1, the second pad PAD2, fuse body are generally by positioned at the top on wafer
Layer metal level is formed naturally it is also possible to be that other metal levels are formed.Now, each floor in gasket construction area 14 can be more than first
One of crystal silicon layer, the second polysilicon layer, lower metal layer of fuse body place metal level, accordingly, gasket construction area 14
The grid area of each floor material be one of the first polysilicon, the second polysilicon, metal.For example, gasket construction
One floor in area 14 is to be formed by the first polysilicon layer, then the material in the grid area in this floor is exactly the first polysilicon；Lining
One floor in mat structure area 14 is to be formed by the second polysilicon layer, then the material in the grid area in this floor is exactly the second polycrystalline
Silicon；One floor in gasket construction area 14 is to be formed by the 2nd metal level, then the material in the grid area in this floor is exactly metal.
Wherein, the current potential in each grid area of each floor in gasket construction area 14 is to suspend.Gasket construction area 14 is in institute
State the view field on crystal column surface and comprise the throwing on described crystal column surface of all fuse parts 13 and part guidance part 11 and 12
Shadow zone domain.In one particular embodiment, the grid area in the different layers in gasket construction area 14 is on described crystal column surface
Projection non-overlapping copies.
As shown in Fig. 2 in this instance, fuse body is formed using the 3rd layer of metal, in gasket construction area 14, first kind side
Block (being filled with grid) is located at the first polysilicon layer, and they are to be formed by the first polysilicon, and the region of these squares is exactly the
The grid area of one polysilicon layer, other regions of this layer are filled with insulating barrier (not shown) to form insulation layer.Equations of The Second Kind side
Block (being filled with oblique line) is located at the second polysilicon layer, and they are to be formed by the second polysilicon, and the region of these squares is exactly the
The grid area of two polysilicon layers, other regions of this layer are filled with insulating barrier (not shown) to form insulation layer；3rd class side
Block (being not filled by) is located at the first metal layer, and they are to be formed by the first metal, and the region of these squares is exactly the first metal layer
Grid area, other regions of this layer are filled with insulating barrier (not shown) to form insulation layer.Common skill in art
Art personnel are it is well known that the first polysilicon layer, the second polysilicon layer and each metal level are in the difference on described wafer
The layer of height, Fig. 2 is the vertical view overlay chart of these different layers, in other words, first kind square in Fig. 2, Equations of The Second Kind square and
3rd class square is not belonging to same layer, and is belonging to the different layers of differing heights.
As shown in Fig. 2 during actual design, these levels can arbitrarily select, such as：First kind square can be more than second
Crystal silicon layer is formed, and Equations of The Second Kind square can be formed for the first metal layer, and the 3rd class square can be formed for the first polysilicon layer.Respectively
The electric potential floating of individual square, that is, be not connected to any current potential.
So, gasket construction area 14 contributes to forming barrier layer between the substrate and fuse part 13 of wafer, works as fuse part
13 when being blown, and even fuse part 13 is short with some blockages (the grid areas in the different layers in gasket construction area 14) downwards
Road, but because the blockage of unlike material is located at differing heights, adjacent blockage is difficult entirely to be electrically connected, so not being easily caused
Short circuit, two pad P AD1 in left and right and PAD2 situation about being still shorted after so can effectively preventing fuse part 13 to be blown.Separately
Outward, gasket construction area 14 prevents the substrate short circuit of metal level and wafer.
It should be noted that Fig. 2 is a kind of schematic diagram, the grid area shape of the different layers in gasket construction area of reality is not necessarily
For square, can be other any shapes, such as triangle, pentagon or hexagon etc., as long as each layer be divided into many
Individual fritter, prevents from fusing latter two pad PAD1 and PAD2 because residual metal is short-circuit by large stretch of conductor.
In the present invention, " connect ", " being connected ", " company ", " connecing " etc. represent the word being electrically connected with, if no special instructions,
Then represent direct or indirect electric connection.
It is pointed out that any change that one skilled in the art is done to the specific embodiment of the present invention
Scope all without departing from claims of the present invention.Correspondingly, the scope of the claim of the present invention is also not merely limited to
In previous embodiment.
Claims (10)
1. a kind of be formed on wafer trim unit it is characterised in that it includes：
First pad；
Second pad；
It is connected to the fuse body between the first pad and the second pad, what described fuse body included being connected with the first pad first leads
The second guidance part draw portion, being connected with the second pad and the fuse part being connected between the first guidance part and the second guidance part, often
The width of individual guidance part is become narrow gradually to fuse part by pad, and the width of fuse part is less than or equal to described guidance part narrow portion
The width dividing；
Gasket construction area below described fuse part, this gasket construction area includes being formed at the many of differing heights on wafer
Individual layer, each floor in gasket construction area includes the grid area at multiple intervals and is filled in insulation layer between grid area, lining
The material in the grid area of the different layers in mat structure area is different.
2. according to claim 1 be formed on wafer trim unit it is characterised in that the first pad, the second pad,
Fuse body is formed by the metal level being located on wafer.
3. according to claim 2 be formed on wafer trim unit it is characterised in that each floor in gasket construction area
For one of the first polysilicon layer, the second polysilicon layer, the lower metal layer of the first pad place metal level, accordingly, lining
The material in the grid area of each floor in mat structure area is one of the first polysilicon, the second polysilicon, metal.
4. according to claim 2 be formed on wafer trim unit it is characterised in that the first pad place metal level
It is the top layer metallic layer on wafer, projection on described crystal column surface for the grid area in the different layers in gasket construction area is mutual
Not overlapping.
5. according to claim 1-4 arbitrary described be formed on wafer trim unit it is characterised in that gasket construction area
Projection of shape on described crystal column surface for the grid area of each floor is one of square, triangle, pentagon or hexagon.
6. according to claim 1-4 arbitrary described be formed on wafer trim unit it is characterised in that gasket construction area exists
View field on described crystal column surface comprises the described fuse part and part guidance part view field on described crystal column surface.
7. according to claim 1-4 arbitrary described be formed on wafer trim unit it is characterised in that gasket construction area
The current potential in each grid area of each floor is to suspend.
8. according to claim 1-4 arbitrary described be formed on wafer trim unit it is characterised in that
Described trim unit and need to be blown when, first probe is contacted with the first pad, by second probe and second
Pad contacts, and applies a predetermined voltage between two probes, and the electric current now being formed in fuse part makes this fuse part fuse.
9. according to claim 1-4 arbitrary described be formed on wafer trim unit it is characterised in that the first pad and institute
State one of power end or a device on wafer connection end to be connected, another power supply on the second pad and described wafer
One of end or another device connection end is connected.
10. according to claim 9 be formed on wafer trim unit it is characterised in that described device be resistance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410691729.8A CN104409436B (en) | 2014-11-25 | 2014-11-25 | It is formed at and trim unit on wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410691729.8A CN104409436B (en) | 2014-11-25 | 2014-11-25 | It is formed at and trim unit on wafer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104409436A CN104409436A (en) | 2015-03-11 |
| CN104409436B true CN104409436B (en) | 2017-03-08 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410691729.8A Active CN104409436B (en) | 2014-11-25 | 2014-11-25 | It is formed at and trim unit on wafer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104409436B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6271574B1 (en) * | 1998-05-14 | 2001-08-07 | Stmicroelectronics S.A. | Integrated circuit fuse with localized fusing point |
| CN2904301Y (en) * | 2006-04-14 | 2007-05-23 | 苏州市华芯微电子有限公司 | High performance high reliable fuse regulating circuit |
| CN204216029U (en) * | 2014-11-25 | 2015-03-18 | 无锡中星微电子有限公司 | Be formed at and wafer trims unit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20130049394A (en) * | 2011-11-04 | 2013-05-14 | 에스케이하이닉스 주식회사 | Semiconductor device with fuse |
-
2014
- 2014-11-25 CN CN201410691729.8A patent/CN104409436B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6271574B1 (en) * | 1998-05-14 | 2001-08-07 | Stmicroelectronics S.A. | Integrated circuit fuse with localized fusing point |
| CN2904301Y (en) * | 2006-04-14 | 2007-05-23 | 苏州市华芯微电子有限公司 | High performance high reliable fuse regulating circuit |
| CN204216029U (en) * | 2014-11-25 | 2015-03-18 | 无锡中星微电子有限公司 | Be formed at and wafer trims unit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104409436A (en) | 2015-03-11 |
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Address after: 214028 Jiangsu Province, Wuxi City District Qingyuan Road No. 18 Taihu International Science Park sensor network university science and Technology Park 530 building A1001 Applicant after: WUXI ZHONGGAN MICROELECTRONIC CO., LTD. Address before: A 530 Taihu international science and Technology Park building 214028 Qingyuan Road in Jiangsu province Wuxi City District 10 layer Applicant before: Wuxi Vimicro Co., Ltd. |
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