CN104391821A - System level model building method of multiple core sharing SIMD coprocessor - Google Patents

Abstract

A system-level model building method for multi-core shared SIMD coprocessors, including a system-on-chip, said system-on-chip is provided with n cores and n vector coprocessors, wherein n is a positive even number, said n The vector coprocessor is connected to the n cores through a crossbar switch, and is also connected to the n cores, the n vector coprocessors and the crossbar switch for scheduling vectors through the crossbar switch A scheduler in which the coprocessor is connected to the core, wherein the scheduler schedules the vector coprocessor according to the current state of each vector coprocessor. The invention significantly improves the resource utilization rate of the SIMD vector coprocessor through the sharing mechanism, reduces system power consumption, and under the condition of certain resources, the efficiency of task completion will be higher.

Description

A system-level model building method for multi-core shared SIMD coprocessors

technical field

The invention relates to a system-level model of a processor. In particular, it involves a system-level model building method for multi-core shared SIMD coprocessors.

Background technique

SIMD (Single Instruction Multiple Data) is a data-level parallel technology that performs the same operation on multiple data. The key to SIMD technology is to perform multiple operations simultaneously in a single instruction to increase the throughput of the processor. This feature makes SIMD technology especially suitable for data-intensive operations such as multimedia applications. Now mainstream processors have their SIMD instruction subsets, such as MMX or SSE of X86, NEON instruction subset of ARM, Altivec instruction subset of PowerPC, etc. In modern multi-core processors, each core on the processor is usually equipped with a dedicated SIMD coprocessor, also known as Vector Coprocessor (VP). However, due to its proprietary nature, when one core executes a program that lacks data-level parallelism, the SIMD coprocessor is idle, while other cores may be executing programs that have data-level parallelism, but only using the The SIMD coprocessor of this core cannot use other idle SIMD coprocessors, resulting in a waste of resources and an increase in power consumption.

As shown in Figure 1, it is a traditional architecture, assuming that a system-on-chip has 4 cores and 4 VPs. In this structure, each VP is dedicated to a certain core and cannot be shared by other cores. When a certain core is not executing a data-intensive program, the VP is in an idle state, resulting in waste of resources and power consumption.

Contents of the invention

The technical problem to be solved by the present invention is to provide a system-level model that can improve the resource utilization rate of the vector coprocessor and reduce system power consumption and multi-core share the SIMD coprocessor.

The technical scheme adopted in the present invention is: a system-level model building method for multi-core shared SIMD coprocessors, including a system-on-chip, and the system-on-chip is provided with n cores and n vector coprocessors, wherein n is a positive even number, the n vector coprocessors are connected to the n cores through a crossbar switch, and are also provided with the n cores, the n vector coprocessors and the crossbar switch to be connected respectively The scheduler is used to schedule the vector coprocessor connected to the core through the crossbar switch, wherein the scheduler schedules the vector coprocessor according to the current state of each vector coprocessor.

Each of the vector coprocessors describes the current state through 3 state registers, wherein,

The first status register is used to describe which core in the n cores the vector coprocessor is currently using, or is not being used by any core. When the vector coprocessor is not currently being used by any core, set It is determined that the vector coprocessor is in an idle state and can be scheduled by a scheduler;

The second state register is used to describe whether the vector coprocessor is currently in the shared state or in the exclusive state. It is set that the vector coprocessor in the shared state can be scheduled by the scheduler, but the vector coprocessor in the exclusive state cannot be scheduled. Scheduled by the scheduler;

The third status register is used to describe the index of the vector coprocessor in all the vector coprocessors in the core.

When a core is currently using multiple vector coprocessors, only one vector coprocessor is in a dedicated state, and the other vector coprocessors are all in a shared state.

In the initial state of the SoC, each vector coprocessor is in a dedicated state, where the first vector coprocessor is dedicated to the first core, the second vector coprocessor is dedicated to the second core, and so on , the index of each vector coprocessor is 0; the condition for the vector coprocessor to change from the exclusive state to the shared state is: the core using the vector coprocessor actively gives up the use right of the vector coprocessor, Thereafter the vector coprocessor is scheduled by the scheduler.

When any one of the n cores requires more vector coprocessors to participate in operations due to the execution of programs with data-level parallelism, the core needs to apply for more vector coprocessors from the scheduler, and the scheduler Run a load balancing scheduling algorithm. If there is currently an idle vector coprocessor, the scheduler will assign the vector coprocessor to the core that is applying for it. If there is no idle vector coprocessor currently , but there is a vector coprocessor in a shared state, the scheduler redistributes the vector coprocessor resources according to the load balancing strategy according to the current situation.

A system-level model building method for a multi-core shared SIMD coprocessor of the present invention can significantly improve the resource utilization rate of the SIMD vector coprocessor through the sharing mechanism, reduce system power consumption, and achieve task completion efficiency under certain resources will be higher.

Description of drawings

Fig. 1 is a traditional system-on-chip structure;

Fig. 2 is a system-level model that adopts the method of the present invention to build a 4 cores to share 4 VPs by a crossbar;

Figure 3 is an example of scheduling.

in the picture

1: Core 2: Vector coprocessor

3: Crossbar 4: Scheduler

Detailed ways

A method for constructing a system-level model of a multi-core shared SIMD coprocessor of the present invention will be described in detail below in conjunction with the embodiments and the accompanying drawings.

A system-level model building method for a multi-core shared SIMD coprocessor of the present invention includes a system-on-chip, and the system-on-chip is provided with n cores and n vector coprocessors, wherein n is a positive even number, and the The n vector coprocessors are connected to the n cores through a crossbar switch, and are respectively connected to the n cores, n vector coprocessors and crossbar switches for passing through the crossbar A scheduler that switches and schedules the vector coprocessor in communication with the core, wherein the scheduler schedules the vector coprocessor according to the current state of each vector coprocessor.

Each of the vector coprocessors describes the current state through 3 state registers, wherein,

The first status register is used to describe which core of the n cores the vector coprocessor is currently using, which may be core 0, core 1 . . . core (n-1). Or it is not used by any core, when the vector coprocessor is not currently used by any core, it is set as the vector coprocessor is in an idle state and can be scheduled by the scheduler;

The second state register is used to describe whether the vector coprocessor is currently in a shared state or in an exclusive state. When a core is currently using multiple vector coprocessors, only one vector coprocessor is in a dedicated state, and the other vector coprocessors are all in a shared state. It is set that the vector coprocessor in the shared state can be scheduled by the scheduler, and the vector coprocessor in the exclusive state cannot be scheduled by the scheduler;

The third status register is used to describe the index of the vector coprocessor in all the vector coprocessors in the core.

A system-level model building method for multi-core shared SIMD coprocessors of the present invention, when the system on chip is in the initial state, each vector coprocessor is in a dedicated state, wherein the first vector coprocessor is exclusive to the first Core, the second vector coprocessor is dedicated to the second core, and so on, the index of each vector coprocessor is 0; the condition for the vector coprocessor to change from the exclusive state to the shared state is: use the vector The core of the coprocessor actively surrenders the right to use the vector coprocessor, and then the vector coprocessor is scheduled by the scheduler.

When any one of the n cores requires more vector coprocessors to participate in operations due to the execution of programs with data-level parallelism, the core needs to apply for more vector coprocessors from the scheduler, and the scheduler Run a load balancing scheduling algorithm. If there is currently an idle vector coprocessor, the scheduler will assign the vector coprocessor to the core that is applying for it. If there is no idle vector coprocessor currently , but there is a vector coprocessor in a shared state, the scheduler redistributes the vector coprocessor resources according to the load balancing strategy according to the current situation.

In order to make the object, technical solution and advantages of the present invention clearer, the implementation manner of the present invention will be further described in detail below in conjunction with the accompanying drawings.

Fig. 2 is a system-level model designed according to the system-level model construction method of multi-core shared SIMD coprocessor of the present invention, in which 4 cores share 4 VPs through a crossbar switch. The scheduler 4 communicates with 4 cores (Core) 1 and 4 vector coprocessors (VP) 2, and allocates resources of the vector coprocessor 2 and configures the crossbar switch 3 according to the application of the core 1.

In the initial state of the system, the four vector coprocessors 2 are respectively dedicated to the four cores 1 and cannot be scheduled by the scheduler 4 . When one of the cores 1 executes a program without data-level parallelism, it can apply to the scheduler 4 for the right to use the vector coprocessor 2. After that, the vector coprocessor 2 is managed by the scheduler 4, and its status Also changed from exclusive status to shared status. Due to the dynamic characteristics of the program itself, in a certain period of time, due to the scheduling of the operating system, the core 1 of the relinquished vector coprocessor 2 may execute a program with data-level parallelism. At this time, the core 1 needs to apply to the scheduler 4 for a certain amount of vector coprocessor 2 resources. If there is currently an idle vector coprocessor 2, the scheduler 4 will allocate a certain amount of vector coprocessor 2 to The core 1 changes the state of one of the vector coprocessors 2 from the shared state to the exclusive state, and the other vector coprocessors 2 assigned to the core are still in the shared state. In any case, if a core that gives up the right to use the vector coprocessor applies for vector coprocessor resources again, the core will apply for at least one vector coprocessor resource, which will ensure that each core will not be used "starve".

Figure 3 shows a scheduling example to illustrate how the sharing model of the present invention works. It is divided into two blocks, the left side is the time state, and the right side is 4 vector coprocessors (VP). In the initial state of the system, that is, the State 0 state, each of the four VPs belongs to one core. Each VP describes the current state through three parameters. Taking VP0 as an example, the three parameters are: C0/0/0. C0 means that VP0 is currently being used by core 0; if the second parameter is 0, it means that it is currently in an exclusive state, that is, it is exclusive to core 0 and cannot be scheduled by the scheduler; if it is 1, it is in a shared state and can be used by the scheduler Scheduling; the third parameter being 0 means that among all VPs belonging to core 0, the index of this VP is 0.

After the system is running, core 0, core 1, and core 2 actively apply to the scheduler to give up the right to use VP because they do not execute data-level parallelism programs, and enter the State 1 state at this time. In State 1, taking VP0 as an example, its three parameters are: s/1/2. The first parameter is s, which means that the VP is managed by the scheduler. The second parameter is 1, which means that the current VP0 is in a shared state. The third parameter is 2, which means that among all the VPs managed by the scheduler, VP0 is in it. The index is 2.

The system continues to run. For a certain period of time, core 3 actively applies for VP resources from the scheduler because it performs a large number of data-intensive tasks. Since the scheduler is managing 3 idle and shared VPs, it will These 3 VP resources are all allocated to core 3 and enter the State 1 state. In this state, all 4 VPs are used by core 3, 3 VPs (VP0-VP3) are still in the shared state, and one VP (VP3) is in the exclusive state, with indexes 0 to 3 respectively.

The system continues to run. In a certain period of time, due to the scheduling of the operating system, core 0 is scheduled into a program with data-level parallelism, so core 0 actively applies for VP resources from the scheduler, while core 3 is still running All VP resources are used. Since the scheduler is running a load balancing scheduling algorithm, two of the three VPs in the shared state used by core 3 will be assigned to core 0, and the status registers of these two VPs will be set at the same time. Set one of the two VPs from the shared state to the exclusive state, and the other is still in the shared state and enters the State 3 state. In State 3, core 0 and core 3 use two VP resources respectively, and one of the two VPs used by each core is in the exclusive state and the other is in the shared state. According to the operating conditions of the system, the VP resources in the shared state can still be scheduled by the scheduler, and the whole process has been a dynamic adjustment process.

Those skilled in the art can understand that the accompanying drawing is only a schematic diagram of a preferred embodiment, and the serial numbers of the above-mentioned embodiments of the present invention are for description only, and do not represent the advantages and disadvantages of the embodiments. The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection of the present invention. within range.

Claims (5)

1. A system-level model building method for multi-core shared SIMD coprocessors, including system-on-chip, said system-on-chip is provided with n cores and n vector coprocessors, wherein n is a positive even number, characterized in that , the n vector coprocessors are connected to the n cores through a crossbar switch, and are connected to the n cores, n vector coprocessors and crossbar switches respectively for passing through the crossbar switch The crossbar switch schedules a scheduler that communicates with the cores, wherein the scheduler schedules the vector coprocessors according to the current state of each vector coprocessor. 2. the system-level model building method of a kind of multi-core shared SIMD coprocessor according to claim 1, is characterized in that, described each vector coprocessor is to describe the current state by 3 state registers ,in, The first status register is used to describe which core in the n cores the vector coprocessor is currently using, or is not being used by any core. When the vector coprocessor is not currently being used by any core, set It is determined that the vector coprocessor is in an idle state and can be scheduled by a scheduler; The second state register is used to describe whether the vector coprocessor is currently in the shared state or in the exclusive state. It is set that the vector coprocessor in the shared state can be scheduled by the scheduler, but the vector coprocessor in the exclusive state cannot be scheduled. Scheduled by the scheduler; The third status register is used to describe the index of the vector coprocessor in all the vector coprocessors in the core. 3. The system-level model building method of a kind of multi-core shared SIMD coprocessor according to claim 2, wherein when a core is currently using a plurality of vector coprocessors, only one vector coprocessor is in Exclusive state, other vector coprocessors are in shared state. 4. the system-level model building method of a kind of multi-core shared SIMD coprocessor according to claim 2, is characterized in that, when system on chip is in initial state, each vector coprocessor is all in exclusive state, wherein the first The first vector coprocessor is dedicated to the first core, the second vector coprocessor is dedicated to the second core, and so on. The index of each vector coprocessor is 0; the vector coprocessor changes from the exclusive state to The condition for sharing the state is: the core using the vector coprocessor actively surrenders the right to use the vector coprocessor, and then the vector coprocessor is scheduled by the scheduler. 5. the system-level model building method of a kind of multi-core shared SIMD coprocessor according to claim 4, is characterized in that, when any core in n cores needs more because of carrying out the program that has data-level parallelism vector coprocessor to participate in the calculation, then the core needs to apply for more vector coprocessors from the scheduler, and the scheduler runs a load-balancing scheduling algorithm. If there are currently idle vector coprocessors, Then the scheduler assigns the vector coprocessor to the core that is applying. If there is no idle vector coprocessor but there is a vector coprocessor in a shared state, the scheduler will balance the load according to the current situation. Policy for reallocation of vector coprocessor resources.