CN104378818A - Clock synchronization method and device and base station subsystem - Google Patents
Clock synchronization method and device and base station subsystem Download PDFInfo
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- CN104378818A CN104378818A CN201310351739.2A CN201310351739A CN104378818A CN 104378818 A CN104378818 A CN 104378818A CN 201310351739 A CN201310351739 A CN 201310351739A CN 104378818 A CN104378818 A CN 104378818A
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Abstract
本发明提供了一种用于BTS的时钟同步方法及装置、基站子系统，该时钟同步方法包括：确定基准BTS和一个待同步处理的目标BTS；计算基准BTS和目标BTS之间的时钟差参数；根据时钟差参数得到时钟同步函数；根据时钟同步函数对目标BTS进行时钟同步处理。通过本发明的实施，在多个BTS中选择基准BTS及一个目标BTS，根据基准BTS与目标BTS之间的时钟差参数得到目标BTS的时钟同步函数，并利用该时钟同步函数对目标BTS进行时钟同步处理，使得目标BTS与基准BTS两者时钟一致，达到了BSS中所有BTS时钟与基准BTS时钟完全同步的效果，由于本发明不需增加设备，降低了实现BTS时钟同步的成本。
The invention provides a clock synchronization method and device for a BTS, and a base station subsystem. The clock synchronization method includes: determining a reference BTS and a target BTS to be synchronized; calculating a clock difference parameter between the reference BTS and the target BTS ; Obtain a clock synchronization function according to the clock difference parameter; perform clock synchronization processing on the target BTS according to the clock synchronization function. Through the implementation of the present invention, select a reference BTS and a target BTS in a plurality of BTSs, obtain the clock synchronization function of the target BTS according to the clock difference parameter between the reference BTS and the target BTS, and utilize this clock synchronization function to clock the target BTS The synchronous processing makes the clocks of the target BTS and the reference BTS consistent, and achieves the effect that all BTS clocks in the BSS are completely synchronized with the reference BTS clocks. Since the present invention does not need to increase equipment, the cost of realizing BTS clock synchronization is reduced.
Description
Technical Field
The present invention relates to the field of communications, and in particular, to a method and an apparatus for clock synchronization between base transceiver stations, and a base station subsystem.
Background
With the development of communication technology, the functions of communication networks are increasingly improved, such as communication functions of DFCA, IRC, SAIC, etc., but the realization of these functions depends on the stable operation of communication base stations. Taking the GSM system as an example, the GSM system includes a plurality of base station subsystems BSS, as can be seen from fig. 1, a base station controller BSC and more than two base transceiver stations BTS (for example, BTS1, BTS2, and BTS3 in fig. 1) are provided under each base station subsystem BSS;
due to the fact that crystal oscillators of the BTSs are different, after the BTSs are operated for a period of time, when clocks of the BTS1, the BTS2 and the BTS3 are inconsistent, random overlapping of communication data among different time slots is caused, unnecessary and unpredictable interference is brought, and the effect of some technologies is reduced remarkably (such as IRC and SAIC).
At present, the method for solving the difference of clocks of all BTSs is mainly to add GPS equipment in each BTS, correct the clock of each BTS according to each GPS clock and achieve the effect of clock synchronization among all BTSs by utilizing the consistency of the clocks among the GPS equipment; however, this solution requires the addition of a GPS device for each BTS, resulting in excessive cost of the work to implement the solution.
Therefore, it is an urgent technical problem to be solved by those skilled in the art to provide a method for clock synchronization between BTSs to solve the problem of excessive cost in the prior art.
Disclosure of Invention
The invention provides a clock synchronization method and device for BTSs (base transceiver stations) and a base station subsystem, which solve the problem of overlarge cost in the prior art when clock synchronization among the BTSs is realized.
The present invention provides a clock synchronization method for a BTS, which in one embodiment comprises: determining a reference base transceiver station and a target base transceiver station to be synchronously processed; calculating a clock difference parameter between the reference base transceiver station and the target base transceiver station; obtaining a clock synchronization function according to the clock difference parameter; and performing clock synchronization processing on the target base transceiver station according to the clock synchronization function.
Further, the clock synchronization function in the above embodiment is an n-th order linear function, where n ≧ 1.
Further, the clock difference parameter in the above embodiment includes: a reference base transceiver station to target base transceiver station direction clock difference parameter, and/or a target base transceiver station to reference base transceiver station direction clock difference parameter.
Further, the clock synchronization method in the above embodiment further includes, before performing linear regression processing on the clock difference parameter: and carrying out merging processing on the clock difference parameters and/or carrying out correction processing on the clock difference parameters.
Further, in the above embodiment, the step of performing linear regression on the clock difference parameter specifically includes: performing linear regression processing on the clock difference parameters and respective calculation time to obtain a clock synchronization function; the clock synchronization function is a first order linear function: y = a + b × t, where Y represents a clock adjustment value of the target base transceiver station, t represents a time parameter when the target base transceiver station is synchronized, a is an intercept parameter obtained from the clock difference parameter, and b is a slope parameter obtained from the clock difference parameter.
Further, the step of performing clock synchronization processing on the target base transceiver station according to the clock synchronization function in the foregoing embodiment includes: performing clock synchronization processing on an initial clock of a target base transceiver station, specifically, correcting a current time value of the target base transceiver station according to a clock adjustment value Y obtained by calculation by taking the current time value of the target base transceiver station as a time parameter t; and/or, periodically performing clock synchronization processing on the current clock of the target base transceiver station, specifically: and correcting the current clock of the target base transceiver station according to the clock adjustment value Y obtained by calculation by taking the difference value between the current time of the target base transceiver station and the time of the previous clock synchronization operation as a time parameter t.
The present invention provides a clock synchronization apparatus for a base transceiver station, which in one embodiment comprises: a selection module for determining a reference base transceiver station and a target base transceiver station to be synchronously processed; a calculation module for calculating a clock difference parameter between the reference base transceiver station and the target base transceiver station; the processing module is used for obtaining a clock synchronization function according to the clock difference parameter; and a synchronization module for performing clock synchronization processing on the target base transceiver station according to the clock synchronization function.
Meanwhile, the present invention also provides a base station subsystem, which in one embodiment comprises: comprising a base station controller and at least two base transceiver stations, wherein the base station controller comprises a memory, one or more processors, and one or more modules, the one or more modules of the base station controller being stored in the memory of the base station controller and configured to be executed by the one or more processors of the base station controller, the one or more modules of the base station controller comprising instructions for: determining a reference base transceiver station and a target base transceiver station to be synchronously processed from all base transceiver stations, calculating a clock difference parameter between the reference base transceiver station and the target base transceiver station, and obtaining a clock synchronization function according to the clock difference parameter; the target base transceiver station includes a memory, one or more processors, and one or more modules, the one or more modules of the target base transceiver station being stored in the memory of the target base transceiver station and configured to be executed by the one or more processors of the target base transceiver station, the one or more modules of the target base transceiver station including instructions for performing the steps of: and performing clock synchronization processing on the target base transceiver station according to the clock synchronization function.
The invention has the beneficial effects that:
the clock synchronization method, the device and the base station subsystem provided by the invention select the reference BTS and the target BTS from the BTSs, obtain the clock synchronization function of the target BTS according to the clock difference parameter between the reference BTS and the target BTS, perform clock synchronization processing on the target BTS by using the clock synchronization function to ensure that the clocks of the target BTS and the reference BTS are consistent, and perform clock synchronization processing on all BTSs except the reference BTS in the BSS in sequence according to the method to achieve the effect of completely synchronizing the clocks of all BTSs and the clocks of the reference BTS.
Drawings
FIG. 1 is a schematic diagram of a base station subsystem;
FIG. 2 is a diagram illustrating a clock synchronization method according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a clock synchronization apparatus according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a clock synchronization method provided by an application example of the present invention.
Detailed Description
The clock synchronization method provided by the present invention can be applied to the synchronization of clocks between BTSs in a base station subsystem BSS in all communication network systems, and the present invention will be further explained by way of specific embodiments with reference to the accompanying drawings.
Fig. 2 is a schematic diagram of a clock synchronization method according to an embodiment of the present invention, and as can be seen from fig. 2, in this embodiment, the clock synchronization method for BTS clock synchronization according to the present invention includes the following steps:
s201: determining a reference base transceiver station and a target base transceiver station to be synchronously processed;
referring to fig. 1, this step selects a reference BTS and a target BTS to be synchronized from among BTS1, BTS2, and BTS 3; the reference BTS can be selected by using the BTS with a smaller number as the reference BTS, for example, using BTS1 as the reference BTS, so that BTS2 and BTS3 are both BTSs to be synchronized, and one of BTS2 and BTS3, for example, BTS2, is selected as the target BTS in the step;
s202: calculating a clock difference parameter between the reference base transceiver station and the target base transceiver station;
step S201, which is to calculate a clock difference parameter between BTS1 and BTS 2;
preferably, the clock difference parameter includes: the reference BTS to target BTS direction (BTS 1 → BTS 2) and/or the target BTS to reference BTS direction (BTS 2 → BTS 1), because the clocks are not the same between the two BTSs, the clock difference parameters for both directions are not necessarily the same;
preferably, the clock difference parameter is a difference between clocks of the reference BTS and the target BTS, and in an application example of the present invention, for convenience of calculation, the unit of the clock difference parameter is a "half symbol number";
preferably, in order to ensure the validity of the calculated clock difference parameter, the clock difference parameter between BTS1 and BTS2 may be periodically calculated, and for the sake of counting, in the application example of the present invention, the period is "100 ms";
s203: obtaining a clock synchronization function according to the clock difference parameter;
preferably, the clock synchronization function obtained in step S203 is an n-th order linear function, where n ≧ 1.
Preferably, the step S203 may include: performing linear regression processing on the clock difference parameters to obtain a clock synchronization function;
preferably, the step S203 further includes, before performing the linear regression process on the clock difference parameter: merging the clock difference parameters and/or correcting the clock difference parameters; specifically, when the clock difference parameter includes a clock difference parameter from the target base transceiver station to the reference base transceiver station, step S203 further includes, before performing the correction processing on the clock difference parameter: merging the clock difference parameters, specifically, converting the clock difference parameters from the target base transceiver station to the reference base transceiver station (BTS 2 → BTS 1) into the clock difference parameters from the reference base transceiver station to the target base transceiver station (BTS 1 → BTS 2), wherein the purpose of the conversion is to ensure the consistency of the clock difference parameter directions and the uniqueness that the reference BTS is BTS 1; when the clock difference parameter includes an excessively large clock difference parameter value (for example, more than 500 half-symbol), in order to avoid the influence of the excessively large data on the subsequent calculation, step S203 further includes, before performing the correction process on the clock difference parameter: the clock difference parameter is corrected, specifically, an overlarge clock difference parameter is converted into a smaller new clock difference parameter, so that the purpose of correction is to ensure the stability of the calculated clock synchronization function.
Since the free-running clocks of the BTSs are stable in the GSM network, the clock difference between the target BTS and the reference BTS is linearly changed to the first order; then, preferably, the clock synchronization function in step S203 is a first-order linear function: y = a + b × t; wherein, Y represents the clock correction value of the target base transceiver station, t represents the time parameter when the target base transceiver station is processed synchronously, a is the intercept parameter obtained according to the clock difference parameter, b is the slope parameter obtained according to the clock difference parameter; the steps of performing linear regression processing on the clock difference parameters specifically comprise: and performing linear regression processing on the clock difference parameters and the respective calculation time to obtain a clock synchronization function.
S204: performing clock synchronization processing on the target base transceiver station according to the clock synchronization function;
the clock synchronization process for the target BTS in step S204 includes: the initial clock carries out synchronization and periodical clock synchronization;
for the two cases, when the clock synchronization function in step S203 is the first-order linear function Y = a + b × t, the step of performing clock synchronization processing on the initial clock of the target BTS specifically includes correcting the current time value of the target base transceiver station according to the calculated clock correction value Y, with the current time value of the target base transceiver station as the time parameter t; the clock synchronization processing (which may be periodic clock synchronization) of the current clock of the target BTS specifically includes taking a difference between the current time of the target base transceiver station and the time of the previous clock synchronization operation as a time parameter t (when the clock synchronization is performed periodically, t is the synchronization period), and correcting the current clock of the target base transceiver station according to the calculated clock correction value Y.
It is anticipated that steps S201 to S204 may be performed sequentially for other BTSs, such as BTS3 in fig. 1 (only BTS2 is replaced with BTS 3), and that synchronization of clocks between BTS3 and the reference BTS may be achieved, and then synchronization of clocks among BTS1, BTS2, and BTS3 may be achieved on the basis.
FIG. 3 is a schematic diagram of a clock synchronization apparatus according to an embodiment of the present invention; as can be seen from fig. 3, in this embodiment, the clock synchronization apparatus 3 provided by the present invention includes: a selection module 31, a calculation module 32, a processing module 33 and a synchronization module 34, wherein,
the selection module 31 is used for determining a reference base transceiver station and a target base transceiver station to be synchronously processed;
the calculation module 32 is used for calculating a clock difference parameter between the reference base transceiver station and the target base transceiver station;
the processing module 33 is configured to obtain a clock synchronization function according to the clock difference parameter;
the synchronization module 34 is used for performing clock synchronization processing on the target base transceiver station according to the clock synchronization function.
Preferably, the clock synchronization function obtained by the processing module 33 in fig. 3 is an nth-order linear function, where n ≧ 1.
Preferably, the clock difference parameters calculated by the calculating module 32 in fig. 3 include: a clock difference parameter from the reference base transceiver station to the target base transceiver station and/or a clock difference parameter from the target base transceiver station to the reference base transceiver station; further, the clock difference parameter is a difference in clock between the reference base transceiver station and the target base transceiver station.
Preferably, in one embodiment, the processing module 33 in fig. 3 includes: and the first submodule is used for performing linear regression processing on the clock difference parameters to obtain a clock synchronization function.
Preferably, in another embodiment, the processing module 33 in the above embodiment further includes: the second submodule is used for carrying out merging processing on the clock difference parameters, and/or the third submodule is used for carrying out correction processing on the clock difference parameters.
Preferably, in an embodiment, the clock synchronization function obtained by the processing module 33 in fig. 3 is a first-order linear function: y = a + b × t; wherein, Y represents the clock correction value of the target base transceiver station, t represents the time parameter when the target base transceiver station is processed synchronously, a is the intercept parameter obtained according to the clock difference parameter, b is the slope parameter obtained according to the clock difference parameter; specifically, the first sub-module in the processing module 33 is specifically configured to perform linear regression processing on the clock difference parameter and the respective calculation time thereof to obtain a clock synchronization function.
Preferably, in one embodiment, the synchronization module 34 in fig. 3 includes: and the first synchronization submodule is specifically used for correcting the current time value of the target base transceiver station according to the clock correction value Y obtained through calculation by taking the current time value of the target base transceiver station as a time parameter t.
Preferably, in one embodiment, the synchronization module 34 in fig. 3 includes: and the second synchronization submodule is specifically used for correcting the current clock of the target base transceiver station according to the clock correction value Y obtained through calculation by taking the difference value between the current time of the target base transceiver station and the time of the previous clock synchronization operation as a time parameter t.
It is foreseen that the clock synchronization apparatus 3 shown in fig. 3 may be a stand-alone apparatus, or may be a part of the structure in the BSC and/or BTS in the BSS, such as the selection module 31, the calculation module 32, and the processing module 33 are located in the BSC, and the synchronization module 34 is located in the target BTS.
An application example of the present invention is now described with reference to fig. 1 and 4, in which a BSS is set as a base station subsystem in a GSM network; referring to fig. 1, the base station subsystem BSS provided in the present invention includes: a base station controller and at least two base transceiver stations, wherein,
the base station controller includes a memory, one or more processors, and one or more modules, the one or more modules of the base station controller being stored in the memory of the base station controller and configured to be executed by the one or more processors of the base station controller, the one or more modules of the base station controller including instructions for performing the steps of: determining a reference base transceiver station and a target base transceiver station to be synchronously processed from all base transceiver stations, calculating a clock difference parameter between the reference base transceiver station and the target base transceiver station, and obtaining a clock synchronization function according to the clock difference parameter;
the target base transceiver station includes a memory, one or more processors, and one or more modules, the one or more modules of the target base transceiver station being stored in the memory of the target base transceiver station and configured to be executed by the one or more processors of the target base transceiver station, the one or more modules of the target base transceiver station including instructions for performing the steps of: and performing clock synchronization processing on the target base transceiver station according to the clock synchronization function.
Preferably, the clock synchronization function obtained by one or more modules of the base station controller in the above embodiment is an nth-order linear function, where n ≧ 1.
Preferably, the clock difference parameters calculated by one or more modules of the base station controller in the above embodiments include: a reference base transceiver station to target base transceiver station direction clock difference parameter, and/or a target base transceiver station to reference base transceiver station direction clock difference parameter.
Preferably, one or more modules of the base station controller in the above embodiments further include instructions for performing the following steps: and performing linear regression processing on the clock difference parameters to obtain a clock synchronization function.
Preferably, one or more modules of the base station controller in the above embodiments further include instructions for performing the following steps: and merging the clock difference parameters, and/or correcting the clock difference parameters.
Preferably, one or more modules of the base station controller in the above embodiments further include instructions for performing the following steps: performing linear regression processing on the clock difference parameters and respective calculation time to obtain a clock synchronization function; the clock synchronization function calculated by one or more modules of the base station controller is a first-order linear function: y = a + b × t, where Y represents a clock adjustment value of the target base transceiver station, t represents a time parameter when the target base transceiver station is synchronized, a is an intercept parameter obtained from the clock difference parameter, and b is a slope parameter obtained from the clock difference parameter.
Preferably, one or more of the modules of the target base transceiver station in the above embodiments includes instructions for performing the steps of: performing clock synchronization processing on an initial clock of a target base transceiver station, specifically, correcting a current time value of the target base transceiver station according to a clock adjustment value Y obtained by calculation by taking the current time value of the target base transceiver station as a time parameter t; and/or, periodically performing clock synchronization processing on the current clock of the target base transceiver station, specifically: and correcting the current clock of the target base transceiver station according to the clock adjustment value Y obtained by calculation by taking the difference value between the current time of the target base transceiver station and the time of the previous clock synchronization operation as a time parameter t.
Fig. 4 is a schematic diagram of a clock synchronization method provided by an application example of the present invention, and as can be seen from fig. 4, in the application example, the clock synchronization method provided by the present invention includes the following steps:
s401: determining BTS1 as a reference BTS and BTS2 as a target BTS;
s402: calculating a clock difference parameter between the reference BTS and the target BTS;
to explain the present invention in detail, it is set that in step S402, the clock difference parameters in the directions of BTS1 → BTS2 and BTS2 → BTS1 are calculated simultaneously, the unit of the clock difference parameter is "half symbol number", 12 clock difference parameters are periodically calculated and sorted by calculation time, and the sorting results are shown in table 1 below:
TABLE 1
| Station direction | Time points (ms) | Clock difference parameter (Y) |
| BTS1→BTS2 | 0 | 6789119996 |
| BTS1→BTS2 | 102 | 6789119998 |
| BTS1→BTS2 | 198 | 6789119997 |
| BTS1→BTS2 | 300 | 6789119999 |
| BTS1→BTS2 | 402 | 0 |
| BTS1→BTS2 | 504 | 1 |
| BTS2→BTS1 | 602 | 1 |
| BTS2→BTS1 | 695 | 6789119999 |
| BTS2→BTS1 | 800 | 6789119998 |
| BTS2→BTS1 | 902 | 6789119997 |
| BTS2→BTS1 | 1004 | 6789119996 |
| BTS2→BTS1 | 1103 | 6789119996 |
As can be seen from table 1, the calculated clock difference parameter includes the clock difference parameter from the target BTS to the reference BTS, and then the clock difference parameter from the target BTS to the reference BTS needs to be converted into the clock difference parameter from the reference BTS to the target BTS, that is, step S403 is executed; if the table 1 does not include the clock difference parameter from the target BTS to the reference BTS, step S403 may be skipped and step S404 may be directly performed after step S402;
s403: merging the clock difference parameters;
in the GSM network, the frame number of the data frame used by the BTS to transmit/receive data is cycled at a period of 2048 × 26 × 51, and each data frame includes 8 subframes, each subframe contains 156.25 symbols, that is, in the GSM network, the maximum value of the clock difference parameter Y of two BTSs is 2048 × 26 × 51 × 156.25 × 2 half-symbols; that is, at a certain time Ti, the following relationship exists for the clock difference parameter between the two BTSs:
Yi(BTS1→BTS2)+Yi(BTS2→BTS1)=2048*26*51*156.25*2=6789120000；
based on the above relationship, after converting the clock difference parameter in the direction of BTS2 → BTS1 in table 1 into the clock difference parameter in the direction of BTS1 → BTS2, table 1 is updated to table 2 below:
TABLE 2
| Station direction | Time points (ms) | Clock difference parameter (Y) |
| BTS1→BTS2 | 0 | 6789119996 |
| BTS1→BTS2 | 102 | 6789119998 |
| BTS1→BTS2 | 198 | 6789119997 |
| BTS1→BTS2 | 300 | 6789119999 |
| BTS1→BTS2 | 402 | 0 |
| BTS1→BTS2 | 504 | 1 |
| BTS1→BTS2 | 602 | 6789119999 |
| BTS1→BTS2 | 695 | 1 |
| BTS1→BTS2 | 800 | 2 |
| BTS1→BTS2 | 902 | 3 |
| BTS1→BTS2 | 1004 | 4 |
| BTS1→BTS2 | 1103 | 4 |
S404: correcting the clock difference parameter;
when the measured data is near the maximum value of the clock difference parameter (26 × 51 × 2048 × 8 × 156.25 × 2), the range of the clock difference parameter is too large (as shown in table 2, the variation range is 0-6789119999) to affect the calculation of the slope parameter and the intercept parameter of the subsequent clock synchronization function; as shown in table 2, it can be seen from table 2 that the variation range of the clock difference parameter is too large, and some clock difference parameters need to be modified to eliminate the calculation deviation caused by the calculation period; the calculation algorithm is as follows:
ifYmax-Ymin<Δ
Yi=Yi
else
for(i=1;i≤n;i++)
ifYi-Ymin<Δ
Yi=Yi
else
Yi=Yi-2048×26×51×8×156.25×2
end
end
end
the above algorithm involves Ymax and Ymin, which among all the calculated n clock difference parameters shown in table 2, Ymax =6789119999, Ymin = 0; in the present application example, n = 12;
where Δ may be set to be several half-symbol numbers, which means the allowable variation range of the clock difference parameter in the initial clock difference parameter calculation time window, 2048 × 26 × 51 × 8 × 156.25 × 2 represents the half-symbol number included in one super frame, in practice, we take Δ =500, and it is considered that the difference between the clock difference parameters is greater than 500 due to exceeding the maximum value of the half-symbol number of the super frame;
table 2 was modified according to the above algorithm to yield the following Table 3:
TABLE 3
| Station direction | Time points (ms) | Clock difference parameter (Y) |
| BTS1→BTS2 | 0 | -4 |
| BTS1→BTS2 | 102 | -2 |
| BTS1→BTS2 | 198 | -3 |
| BTS1→BTS2 | 300 | -1 |
| BTS1→BTS2 | 402 | 0 |
| BTS1→BTS2 | 504 | 1 |
| BTS1→BTS2 | 602 | -1 |
| BTS1→BTS2 | 695 | 1 |
| BTS1→BTS2 | 800 | 2 |
| BTS1→BTS2 | 902 | 3 |
| BTS1→BTS2 | 1004 | 4 |
| BTS1→BTS2 | 1103 | 4 |
It is expected that if the difference between all the clock difference parameters in table 2 is not greater than 500, step S404 may be skipped after step S403, and step S405 may be directly performed;
s405: performing linear regression processing on the processing result to obtain a clock synchronization function;
since in GSM networks, the clock synchronization function is a first order linear function: y = a + b × t; only the intercept parameter a and the slope parameter b need to be calculated, and the invention also exemplarily provides an algorithm as follows:
wherein, YiRepresenting the ith clock difference parameter, tiRepresents the calculation time point of the ith clock difference parameter,represents the average of all clock difference parameters,represents an average value of time points of calculating the clock difference parameter; according to the algorithm and the data given by way of example in table 3, the following are calculated:
a=-3.515715267；b=0.006985569
Y=0.006985569×t-3.515715267
s406: performing clock synchronization processing on the target BTS according to a clock synchronization function;
the step can be executed by BSC, or executed by target BTS, when executed by target BTS, the parameters a, b in the function are transmitted to target BTS by BSC;
the method comprises the following steps: the initial clock carries out synchronization and periodical clock synchronization; wherein,
examples of the initial clock synchronization are: calculating a clock correction value at the current time point based on the current time point and the clock synchronization function, e.g. at t1Synchronizing at a time point of =1200ms, calculating to obtain a clock correction value of 4.866967533, and rounding to obtain an integer to adjust 5 half-symbol numbers;
periodic clock synchronization is exemplary such as: due to the crystal oscillator difference of each BTS and the existence of measurement error, the clock between BTSs gradually deviates along with the accumulation of time, and the requirement is thatCarrying out periodic clock deviation calculation and adjustment, and when a preset clock adjustment period T is reached, calculating a clock correction value by the BTS according to the adjustment period T and a clock synchronization function; since the periodic adjustment is made after the initial clock synchronization, as above at t1The time has been adjusted, then at t2Time (t)2-t1= T =1200 ms), the clock correction value obtained by direct calculation from the clock synchronization function is 13, and therefore T is the time at which the adjustment is performed1The time has been adjusted, at t2The clock correction value which is actually required to be adjusted in time is 8 (13-5 = 8) half-symbol numbers, and is at t3Time (t)3-t2= T =1200 ms), the clock correction value obtained by direct calculation from the clock synchronization function is 21, and therefore T is T2The time has been adjusted, at t3The clock correction value which is actually required to be adjusted at the moment is 8 (21-13 = 8) half-symbol numbers; it can be seen that, after the adjustment period is determined, the clock correction value of each period is also determined, and therefore, in other embodiments, the clock correction value may also be directly calculated according to the period T, because the synchronization at the initial time overcomes the clock difference once, that is, the intercept parameter in the clock synchronization function is corrected, and the calculation formula of the clock correction value of each period is as follows: y = b × T.
In summary, the implementation of the present invention has at least the following advantages:
firstly, selecting a reference BTS and a target BTS from a plurality of BTSs, obtaining a clock synchronization function of the target BTS according to a clock difference parameter between the reference BTS and the target BTS, and performing clock synchronization processing on the target BTS by using the clock synchronization function to ensure that clocks of the target BTS and the reference BTS are consistent, and sequentially performing clock synchronization processing on all BTSs except the reference BTS in the BSS according to the method to achieve the effect of completely synchronizing the clocks of all BTSs in the BSS and the clock of the reference BTS;
secondly, the uniqueness of the reference BTS is ensured by combining the calculated clock difference parameters;
thirdly, the accuracy of the clock synchronization function obtained by the clock difference parameter is ensured by correcting the clock difference parameter obtained by calculation;
and finally, the clock synchronization is carried out periodically, so that the clock consistency among all BTSs in the BSS is ensured.
The above embodiments are only examples of the present invention, and are not intended to limit the present invention in any way, and any simple modification, equivalent change or modification made to the above embodiments according to the technical spirit of the present invention still belongs to the protection scope of the technical solution of the present invention.
Claims (21)
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| CN201310351739.2A CN104378818A (en) | 2013-08-13 | 2013-08-13 | Clock synchronization method and device and base station subsystem |
| PCT/CN2014/084204 WO2015021911A1 (en) | 2013-08-13 | 2014-08-12 | Clock synchronization method and device, and base station system |
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| CN201310351739.2A CN104378818A (en) | 2013-08-13 | 2013-08-13 | Clock synchronization method and device and base station subsystem |
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| WO (1) | WO2015021911A1 (en) |
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| CN106712879A (en) * | 2015-07-14 | 2017-05-24 | 柳成荫 | Time synchronizing method and device |
| CN110831146A (en) * | 2018-08-14 | 2020-02-21 | 海能达通信股份有限公司 | Method for node synchronization in wireless network, terminal device and storage medium |
| CN111061209A (en) * | 2019-12-04 | 2020-04-24 | 山西诚鹏科技开发有限公司 | PLC authorization overdue shutdown method based on multi-master-station communication mode |
| CN111142467A (en) * | 2019-12-04 | 2020-05-12 | 山西诚鹏科技开发有限公司 | PLC authorization overdue shutdown method based on master-slave station communication mode |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111142467A (en) * | 2019-12-04 | 2020-05-12 | 山西诚鹏科技开发有限公司 | PLC authorization overdue shutdown method based on master-slave station communication mode |
| CN111142467B (en) * | 2019-12-04 | 2022-04-15 | 山西诚鹏科技开发有限公司 | PLC authorization overdue shutdown method based on master-slave station communication mode |
| CN111061209B (en) * | 2019-12-04 | 2022-04-15 | 山西诚鹏科技开发有限公司 | PLC authorization overdue shutdown method based on multi-master-station communication mode |
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| WO2015021911A1 (en) | 2015-02-19 |
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