CN104303274B - Plasma etching method and plasma processing device - Google Patents

Abstract

A method for etching a silicon oxide film layer laminated on a wafer by plasma etching using a silicon mask formed on the silicon oxide film as a mask, etching the silicon oxide film layer (3) by a plasma containing a CF gas, depositing a Si-containing substance on the mask by the plasma containing the Si gas, and etching the silicon oxide film layer again by the plasma containing the CF gas while the Si-containing substance is deposited on the silicon mask. Thus, a hole having an aspect ratio of 60 or more is formed.

Description

Plasma etching method and plasma processing device

technical field

The present invention relates to a method of performing plasma etching on an object to be processed and a plasma processing apparatus for performing the plasma etching.

This application claims priority based on Japanese Patent Application No. 2012-136093 filed in Japan on June 15, 2012, and US61/663133 filed in the United States on June 22, 2012, and their contents are incorporated herein.

Background technique

In the manufacturing process of a semiconductor device, for example, microfabrication such as etching and film formation is performed on an object to be processed under the action of plasma. Examples of microfabrication by plasma etching include trenches and holes for capacitors.

When forming a hole in a silicon layer by etching using plasma, for example, a silicon oxide film is used as a mask, but in this etching process, if the etching rate of the silicon layer is to be increased, the etching rate of the silicon oxide film will also rise. Therefore, there is a problem that the selectivity at the time of etching cannot be increased, and the etching depth cannot be increased. Because, if the mask is etched, the etching has to be stopped.

Therefore, for example, Patent Document 1 discloses a technique in which HBr gas, O ₂ gas, SiF gas, etc. are used as processing gases when etching a silicon layer as an object to be processed. Etching is carried out by applying two types of high-frequency power with different frequencies to the lower electrode on which the object to be processed is placed. Using this etching method, holes with high aspect ratios can be formed in the silicon layer.

Patent Document 1: Japanese PCT Publication No. 2008-505497

Contents of the invention

The problem to be solved by the invention

However, in recent years, with the miniaturization and high integration of semiconductor devices, in order to form capacitors having desired capacitances, it is necessary to form holes and trenches with high aspect ratios such as 60 or more. The reason for this is that the capacitance of the capacitor increases in proportion to the area of the electrodes forming the capacitor, and as miniaturization, in order to maintain the surface area of the electrodes, it is required to increase the depth of the holes.

However, the etching method of Patent Document 1 cannot form a hole with a high aspect ratio having an aspect ratio of 60 or more.

The present invention has been made in view of the above problems, and an object of the present invention is to form holes and trenches with high aspect ratios by plasma etching.

solutions to problems

In order to achieve the above object, the present invention is a plasma etching method in which high-frequency power is applied between an upper electrode and a lower electrode provided in a processing container to make a processing gas plasma, Plasma etching is performed on the silicon oxide film layer and the silicon nitride layer stacked on the substrate using the silicon layer formed on the silicon nitride as a mask, and it is characterized in that, in the plasma etching method, A hole or a trench having a predetermined aspect ratio is formed by the following steps: performing a first etching process in which the silicon nitride layer is treated with a plasma containing a CF gas and a plasma containing a CHF gas. performing etching, and then performing a second etching process, in which the silicon oxide film layer is etched with a plasma containing a CF gas, and then, the mask is etched with a plasma containing a Si gas A Si-containing material is deposited on the substrate, and then a third etching process is performed. In the 3rd etching process, in the state where the Si-containing material is deposited on the silicon mask, the silicon oxide film layer is oxidized by plasma containing CF gas. Etching is performed again.

The present inventors have confirmed that after etching the silicon oxide film using the silicon layer as a mask, a Si-containing substance is deposited using a plasma containing a Si-containing gas, so that even if the etching process is performed again using a plasma containing a CF gas, the mask The mold will not be etched away and disappear. The present invention was made based on this finding, and according to the present invention, a silicon oxide film layer is etched using a silicon layer as a mask, and then a Si-containing substance is deposited using plasma of a Si-containing gas. Then, etching treatment is performed again using plasma containing CF gas. At this time, even if etching is performed again, the mask is maintained without disappearing, so that holes of a desired pattern can be drilled deeper than conventionally. As a result, holes and trenches with a predetermined aspect ratio, for example, holes and trenches with an aspect ratio of 60 or more can be formed.

Another invention of the present application is a plasma processing apparatus that applies high-frequency power between an upper electrode and a lower electrode provided in a processing container to make a processing gas plasma, and treat silicon oxide layered on a substrate. The plasma processing device for performing plasma etching on the film layer and the silicon nitride layer is characterized in that the plasma processing device includes: a processing container for accommodating the substrate; a high-frequency power supply for supplying High-frequency power is applied to the upper electrode and the lower electrode in the processing container; a processing gas supply source is used to supply processing gas into the processing container, and the processing gas supply source includes: an etching gas supply part, which is used to supply A CF-containing gas and a CHF-containing gas for etching a silicon nitride layer, a CF-containing gas for etching a silicon oxide film layer; Deposit the Si-containing species with the Si-containing gas on the silicon mask.

The effect of the invention

According to the present invention, holes and trenches with high aspect ratios can be formed by plasma etching.

Description of drawings

FIG. 1 is a longitudinal sectional view showing a schematic configuration of a plasma processing apparatus according to this embodiment.

2 is a cross-sectional view schematically showing a state where a silicon oxide film layer, a silicon nitride layer, and a silicon mask are formed on a wafer.

3 is a cross-sectional view schematically showing a state in which holes are formed in a wafer by a second etching process.

4 is a cross-sectional view schematically showing a state in which a Si-containing substance is deposited on a mask by coating treatment.

5 is a cross-sectional view schematically showing the state of the wafer after the third etching process.

FIG. 6 is an explanatory diagram showing the results of a confirmation test.

Fig. 7 is a table showing the results of confirmation tests.

detailed description

Hereinafter, an example of embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a longitudinal sectional view showing a schematic configuration of a plasma processing apparatus 1 according to an embodiment of the present invention. The plasma processing apparatus 1 of this embodiment is, for example, a parallel plate type plasma etching processing apparatus, and performs etching processing on a silicon oxide film layer stacked on a wafer W using plasma. In addition, in this embodiment, the wafer W to be etched is a silicon substrate, and the silicon oxide film layer 3 is formed on the upper surface thereof as shown in FIG. 2 . A silicon nitride layer 4 is formed on the silicon oxide film layer 3 , and a mask 5 made of, for example, polysilicon is formed in a predetermined pattern on the silicon nitride layer 4 .

The plasma processing apparatus 1 has a substantially cylindrical processing container 11 provided with a wafer holder 10 for holding a wafer W. As shown in FIG. The processing container 11 is electrically connected to the ground by a ground wire 12 to be grounded. Furthermore, the inner wall of the processing container 11 is covered with a liner (not shown), and a sprayed coating made of a plasma-resistant material is formed on the surface of the liner.

The lower surface of the wafer holder 10 is supported by a susceptor 13 serving as a lower electrode. The base 13 is formed in a substantially disk shape from metal such as aluminum, for example. A support stand 15 is provided at the bottom of the processing container 11 via an insulating plate 14 , and the susceptor 13 is supported on the upper surface of the support stand 15 . Electrodes (not shown) are provided inside wafer holder 10 , and wafer W can be sucked and held by applying a DC voltage to the electrodes to generate electrostatic force.

A conductive correction ring 20 made of, for example, silicon is provided on the upper surface of the susceptor 13 and on the outer periphery of the wafer holder 10 . The correction ring 20 is used to improve the uniformity of plasma processing. Outer surfaces of the base 13 , the support table 15 , and the correction ring 20 are covered with a cylindrical member 21 made of, for example, quartz.

Inside the support table 15, for example, an annular refrigerant flow path 15a for flowing the refrigerant is provided, and by controlling the temperature of the refrigerant supplied in the refrigerant flow path 15a, it is possible to control the 10 to maintain the temperature of the wafer W. In addition, between the wafer holder 10 and the wafer W held by the wafer holder 10, a heat transfer gas pipe 22 for supplying a heat transfer gas, such as helium, is provided. The heat transfer gas pipe 22 runs through the bottom of the processing container 11 , base 13, support platform 15 and insulating plate 14 are set.

A first high-frequency power supply 30 is electrically connected to the susceptor 13 via a first matching unit 31 , and the first high-frequency power supply 30 supplies high-frequency power to the susceptor 13 to generate plasma. The first high-frequency power supply 30 is configured to output high-frequency power at a frequency of, for example, 27 MHz to 100 MHz, and outputs high-frequency power at, for example, 100 MHz in the present embodiment. The first matching unit 31 is used to match the internal impedance of the first high-frequency power supply 30 with the load impedance, and plays such a role: when plasma is generated in the processing container 11, the internal impedance of the first high-frequency power supply 30 and the load impedance are matched. Impedances are apparently consistent.

In addition, a second high-frequency power supply 40 is electrically connected to the susceptor 13 via a second matching unit 41, and the second high-frequency power supply 40 is used to supply high-frequency power to the susceptor 13 to apply a bias voltage to the wafer W, thereby Ions are directed towards wafer W. The second high-frequency power supply 40 is configured to output high-frequency power at a frequency of, for example, 400 kHz to 13.56 MHz, and outputs high-frequency power at, for example, 3.2 MHz in the present embodiment. Like the first matching unit 31 , the second matching unit 41 is used to match the internal impedance of the second high-frequency power supply 40 to the load impedance.

The first high-frequency power supply 30 , the first matching unit 31 , the second high-frequency power supply 40 , and the second matching unit 41 are connected to a control unit 150 described later, and their operations are controlled by the control unit 150 .

An upper electrode 42 is provided above the susceptor 13 as a lower electrode so as to face and parallel to the susceptor 13 . The upper electrode 42 is supported on the upper portion of the processing chamber 11 via a conductive support member 50 . Therefore, the upper electrode 42 is at the ground potential similarly to the processing container 11 .

The upper electrode 42 is composed of an electrode plate 51 and an electrode support plate 52. The electrode plate 51 has a surface facing the wafer W held by the wafer holder 10. The electrode support plate 52 supports the electrode plate 51 from above. 51. A plurality of gas supply ports 53 are formed on the electrode plate 51 so as to penetrate the electrode plate 51 , and the plurality of gas supply ports 53 are used to supply processing gas into the processing chamber 11 . The electrode plate 51 is made of, for example, a low-resistance conductor or semiconductor with little Joule heat, and in this embodiment, silicon is used, for example. Furthermore, the electrode support plate 52 is made of a conductor, and in this embodiment, for example, aluminum is used.

A gas diffusion chamber 54 formed in a substantially disk shape is provided at a central portion inside the electrode support plate 52 . In addition, a plurality of air holes 55 extending downward from the gas diffusion chamber 54 are formed on the lower portion of the electrode support plate 52 , and the gas supply port 53 is connected to the gas diffusion chamber 54 through the air holes 55 .

The gas diffusion chamber 54 is connected to a gas supply pipe 71 . The gas supply pipe 71 is connected to a processing gas supply source 72 as shown in FIG. 1 , and the processing gas supplied from the processing gas supply source 72 is supplied to the gas diffusion chamber 54 through the gas supply pipe 71 . The processing gas supplied to the gas diffusion chamber 54 is introduced into the processing container 11 through the gas hole 55 and the gas supply port 53 . That is, the upper electrode 42 functions as a shower head for supplying processing gas into the processing chamber 11 .

The processing gas supply source 72 of the present embodiment includes an etching gas supply unit 72 a for supplying a processing gas for etching processing and a coating gas supply unit 72 b for performing coating processing. In addition, the processing gas supply source 72 includes a valve 73a and a flow adjustment mechanism 74a provided between the gas supply part 72a and the gas diffusion chamber 54, and a valve 73b and a flow adjustment mechanism provided between the gas supply part 72b and the gas diffusion chamber 54. 74b. The flow rate of the gas supplied to the gas diffusion chamber 54 is controlled by the flow rate adjustment mechanisms 74a and 74b.

As the etching gas for etching, the etching gas for etching the silicon nitride layer 4 can use, for example, a mixed gas of C ₄ F ₆ /CH ₂ F ₂ /O ₂ , and the etching gas for etching the silicon oxide film layer 3 can use C ₄ F ₆ /Ar/O ₂ mixed gas. The coating gas used for the coating process can be, for example, a gas containing SiCl ₄ , and in this embodiment, a mixed gas of SiCl ₄ /He is used, for example.

At the bottom of the processing container 11, an exhaust flow path 80 is formed by the inner wall of the processing container 11 and the outer surface of the cylindrical member 21, and the exhaust flow path 80 is used to discharge the atmospheric gas in the processing container 11 to the outside of the processing container 11. The flow path works. An exhaust port 90 is provided on the bottom surface of the processing container 11 . An exhaust chamber 91 is formed below the exhaust port 90 , and the exhaust chamber 91 is connected to an exhaust device 93 via an exhaust pipe 92 . Therefore, by driving the exhaust device 93 , the atmospheric gas in the processing container 11 can be exhausted through the exhaust flow path 80 and the exhaust port 90 , thereby decompressing the inside of the processing container to a predetermined vacuum degree.

In addition, an annular magnetic body 100 is disposed concentrically with the processing container 11 around the processing container 11 . A magnetic field can be applied to the space between the wafer holder 10 and the upper electrode 42 by the annular magnetic body 100 . The annular magnetic body 100 is configured to be rotatable by a not-shown rotation mechanism.

The aforementioned plasma processing apparatus 1 is provided with the control unit 150 as described above. The control unit 150 is, for example, a computer, and has a program storage unit (not shown). The program storage unit also stores programs for operating the plasma processing apparatus 1 by controlling the power supplies 30 and 40 , the matching units 31 and 41 , the flow rate adjustment mechanisms 74 a and 74 b , and the like.

In addition, the program may be stored in a computer-readable storage medium such as a computer-readable hard disk (HD), floppy disk (FD), compact disk (CD), magneto-optical disk (MO), memory card, etc., from This storage medium is installed in the control unit 150 .

The plasma processing apparatus 1 of the present embodiment is configured as described above. Next, the plasma etching process performed by the plasma processing apparatus 1 of the present embodiment will be described.

For the plasma etching process, first, a wafer W is loaded into the processing container 11 , and the wafer W is placed and held on the wafer holder 10 . At this time, as described above, the silicon oxide film layer 3 , the silicon nitride layer 4 , and the mask 5 having a predetermined pattern are formed on the wafer W as shown in FIG. 2 .

When the wafer W is held on the wafer holder 10, the inside of the processing chamber 11 is exhausted by the action of the exhaust device 93, and at the same time, it is used for etching the silicon nitride layer 4 (first etching process). The processing gas is first supplied from the etching gas supply unit 72 a into the processing chamber 11 at a predetermined flow rate. The processing gas for the first etching process uses a mixed gas of C ₄ F ₆ /CH ₂ F ₂ /O ₂ , and is supplied at flow rates of 42 sccm/90 sccm/100 sccm, respectively.

At the same time, high-frequency power is continuously applied to the susceptor 13 as the lower electrode by the first high-frequency power supply 30 and the second high-frequency power supply 40 . As a result, the etching process gas supplied into the processing chamber 11 is converted into plasma between the upper electrode 42 and the susceptor 13 . At this time, the plasma is confined between the upper electrode 42 and the susceptor 13 by the magnetic field of the annular magnetic body 100 . Then, the silicon nitride layer 4 is etched using the ions and radicals generated by the plasma in the processing chamber 11 using the polysilicon as the etching mask 5 .

After the etching of the silicon nitride layer 4 is completed, the etching process of the silicon oxide film layer 3 is performed as the second etching process. In this etching process, C ₄ F ₆ /Ar/O ₂ as an etching gas is supplied from the etching gas supply unit 72 a at a flow rate of 100 sccm/100 sccm/94 sccm, and the ions and radicals generated by the plasma in the processing chamber 11 are utilized The silicon oxide film layer 3 is etched through the mask 5 . Thus, as shown in FIG. 3 , holes 200 are formed. In addition, when the silicon nitride layer 4 and the silicon oxide film layer 3 are etched, the polysilicon mask 5 is also etched simultaneously.

After the second etching process is completed, the coating process of the wafer W is performed next. In the coating process, SiCl ₄ /He as a coating gas was supplied from the coating gas supply part 72b at a flow rate of 18 sccm/100 sccm. In addition, at this time, the application of high-frequency power to the susceptor 13 by the second high-frequency power supply 40 is stopped. Then, as shown in FIG. 4 , the Si-containing compound D is deposited on the mask 5 on the wafer W using ions and radicals generated by the plasma in the processing chamber 11 to coat the upper surface of the mask 5 .

After the coating process of the mask 5 is completed, the etching process of the silicon oxide film layer 3 is performed again next. In the etching process after coating (third etching process), C ₄ F ₆ /Ar/O ₂ as an etching gas is supplied from the etching gas supply part 72 a at a flow rate of 100 sccm/100 sccm/94 sccm. Then, using the mask 5 deposited with the Si-containing compound D as an etching mask, the silicon oxide film layer 3 is etched again. When this third etching process is performed, as shown in FIG. 5 , the mask 5 is also etched at the same time, but the mask 5 is coated with the Si-containing compound D to increase the thickness in the height direction. Therefore, even after the third etching process is performed, the mask 5 will not be completely etched and disappear. In this way, since the mask 5 remains, the silicon oxide film layer 3 can be etched again, and the silicon oxide film layer 3 can be further dug in the depth direction.

In addition, as shown in FIG. 4 , the Si-containing compound D is deposited not only on the upper surface of the mask 5 after the etching process, but also on the side surfaces of the holes 200 in the silicon oxide film layer 3 formed by the second etching process. Thus, not only the upper surface of the mask 5 but also the side surface of the silicon oxide film layer 3 is coated. Therefore, it is possible to prevent the side surface of the silicon oxide film layer 3 from being etched and over-etched during the third etching process, thereby increasing the diameter of the hole 200 in the silicon oxide film layer 3 . Furthermore, for example, when forming a capacitor by embedding metal in the hole 200 in a subsequent process, the capacitance of the formed capacitor is inversely proportional to the diameter of the hole 200 . In other words, if the diameter of the hole 200 can be kept small, it is possible to prevent a decrease in the capacity of the capacitor.

In the above embodiments, the second high-frequency power supply 40 does not apply high-frequency power to the susceptor 13 during the coating process. Therefore, ions are not introduced to the wafer W, and the mask 5 is not etched by the attracted ions during the coating process. Therefore, the reduction in the thickness of the mask 5 in the height direction can be prevented, and the silicon oxide film layer 3 can be further dug in the depth direction in the third etching process.

In the above embodiment, after the silicon oxide film layer 3 is etched using polysilicon as the mask 5, the Si-containing compound D is deposited on the mask 5 by the plasma of the Si-containing gas. And, thereafter, etching treatment is performed again using plasma containing CF gas. At this time, since the mask is maintained without disappearing even in the etching performed again, it is possible to make the hole 200 of a desired pattern deeper than before. As a result, a high aspect ratio hole having an aspect ratio of 60 or more can be formed, for example.

In addition, the Si-containing compound D is deposited not only on the upper surface of the mask 5 after the second etching process, but also on the side surfaces of the holes 200 formed by the second etching process, so that it is possible to prevent the side surfaces of the holes 200 from being damaged during the third etching process. is over-etched. As a result, the diameter of the pores 200 of the silicon oxide film layer 3 can thereby be prevented from becoming large. For example, when forming a capacitor by embedding metal in the hole 200 in a subsequent process, the capacitance of the formed capacitor is inversely proportional to the diameter of the hole 200 . Therefore, according to the present invention, the diameter of the hole 200 can be prevented from becoming large, in other words, the diameter of the hole 200 can be kept small, so that a decrease in capacitance of a capacitor to be formed later can be prevented.

In the above embodiments, the case where the silicon nitride layer is formed between the mask 5 and the silicon oxide film layer 3 has been described, but the present invention can be used regardless of the presence or absence of the silicon nitride layer.

In the above embodiments, the mixed gas of SiCl ₄ /He was used as the Si-containing gas, but O ₂ may be added to the mixed gas to obtain the same effect. The inventors of the present invention have carried out a comparative test described later and conducted intensive studies, and found that when O ₂ is added to supply a mixed gas of SiCl ₄ /He/O ₂ , it is preferable that the flow rates of each gas of the mixed gas are 20 sccm/ 100sccm/125sccm.

In addition, the present inventors have confirmed that when the mixed gas of SiCl ₄ /He is used for the coating process of the mask ₅ , the mask 5 is coated with a silicon film _. In this case, the mask 5 is coated with a silicon oxide film. Furthermore, it was confirmed that the mask 5 can be satisfactorily coated no matter which mixed gas is used, and that the mask 5 can be prevented from disappearing in the third etching process.

In the above embodiments, the third etching treatment is performed after the coating treatment, but the coating treatment and the third etching treatment may be repeated. More specifically, the etching process is temporarily stopped until the mask 5 coated with the Si-containing compound D disappears due to the third etching process. Then, the coating process is performed again, and the remaining mask 5 is coated with the Si-containing compound D, so that the third etching process can be performed again. In this way, by repeating the coating process and the etching process, for example, the hole 200 can be dug deeper, thereby further forming a hole or a trench with a high aspect ratio.

Furthermore, when the coating process and the etching process are repeated, a mixed gas of SiCl ₄ /He and a mixed gas of SiCl ₄ /He/O ₂ may be alternately used as the mixed gas for the coating process.

In addition, in the above embodiments, polysilicon was used as the mask 5 , but amorphous silicon may also be used as the mask 5 .

Example

As an example, after performing the first etching treatment and the second etching treatment on the wafer W, the mask 5 is coated with a mixed gas of SiCl ₄ /He or a mixed gas of SiCl ₄ /He/O ₂ , A third etching process was performed using the applied mask 5 . At that time, a confirmatory test was carried out regarding the influence of the conditions of the coating process and the time of the third etching on the shape of the hole 200 to be formed. At this time, the diameter of the wafer W is 300 mm, the film thickness of the polysilicon used as the mask 5 is 1200 nm, and the film thickness of the silicon nitride layer 4 is 300 nm. Furthermore, the film thickness of the silicon oxide film layer 3 formed on the wafer W is 3500 nm.

Regarding the conditions of the plasma treatment during the coating treatment, when a mixed gas of SiCl ₄ /He is used, the flow rate of SiCl ₄ is 20 sccm, and the flow rate of He is 100 sccm. In addition, when a mixed gas of SiCl ₄ /He/O ₂ was used for the coating process, the flow rate of SiCl ₄ was 20 sccm, the flow rate of He was 100 sccm, and the flow rate of O ₂ was 125 sccm. At that time, the pressure in the processing container 11 was 1.33Pa, and the power of the first high-frequency power supply 30 was 500W, so that the number of repetitions of the coating process was changed, and the time of each coating process was 5 seconds to 20 seconds. The range of seconds occurs. In addition, in the coating process, the electric power of the 2nd high-frequency power supply 40 was 0W (no power supply) in all cases.

The first etching process was performed using a mixed gas of C ₄ F ₆ /CH ₂ F ₂ /O ₂ , the flow rate of C ₄ F ₆ was 42 sccm, the flow rate of CH ₂ F ₂ was 90 sccm, and the flow rate of O ₂ was 100 sccm. At that time, the pressure in the processing container 11 was 2.0 Pa, the power of the first high-frequency power source 30 was 1400 W, the power of the second high-frequency power source 40 was 4200 W, and the first etching process was performed for 205 seconds. In addition, the second etching process and the third etching process are performed using a mixed gas of C ₄ F ₆ /O ₂ /Ar, the flow rate of the C ₄ F ₆ gas is 100 sccm, the flow rate of the O ₂ gas is 94 sccm, and the flow rate of the Ar gas is 100 sccm. At that time, the pressure in the processing container 11 was 2.26Pa, the power of the first high-frequency power supply 30 was 1500W, the power of the second high-frequency power supply 40 was 7800W-10000W, and the temperature of the wafer W was 40°C-200°C. The diameter of the wafer W is 300 mm. Therefore, when converted to power per unit area, that is, power density (Japanese: power density), the power density of the first high-frequency power supply 30 is 2.12 W/cm ² , and the power density of the second high-frequency power supply 40 is 2.12 W/cm 2 . 11W/cm ² to 14.2W/cm ² .

In addition, as a comparative example, a confirmation test was also performed on the case where holes were formed only by the second etching process. At that time, the cumulative time of the second etching process performed in the comparative example was the same as the cumulative time of the second and third etching processes in the example.

The results of the confirmation test are shown in the tables of FIGS. 6 and 7 . 6 schematically shows a cross-sectional view of a state in which holes are formed in the silicon oxide film layer 3 by etching, and the check items in the check test are the dimensions 1 to 4 indicated by numbers surrounded by circles in FIG. 6 . Dimension 1 represents the size of the opening at the upper end of silicon nitride layer 4 , dimension 2 represents the size of the narrowest portion of mask 5 , and dimension 3 represents the size of the widest portion of hole 200 . Dimension 4 represents the dimension in the depth direction of the hole 200 formed by the etching process. Dimensions 1 to 4 in FIG. 6 correspond to the numbers described in the table of FIG. 7 . Also, the "aspect ratio" in the table refers to the ratio of size 1 to size 4. The "residual mask film" refers to the thickness of the mask 5 remaining on the wafer W after the etching process is completed. In addition, the "selection ratio" in the table of FIG. 7 refers to the selection ratio of the etching process calculated based on the remaining film of the mask 5 .

The temperature of the wafer W was constant between 40° C. and 200° C. during the first etching process to the third etching process and the coating process, but the temperature of the wafer W was varied according to experiments. And, the value of the power of the 2nd high-frequency power supply 40 is also between 11W/cm ² ～14.2W/cm ² in the 2nd etching treatment and the 3rd etching treatment, is constant, according to the difference of test, make the power The value changes.

As shown in the table of FIG. 7 , it was confirmed that in Example 1 using the mixed gas of SiCl ₄ /He, a larger aspect ratio was obtained than in the comparative example in which the coating treatment and the third etching treatment were not performed. Improvement, it is possible to etch with an aspect ratio of 60 or more. Furthermore, in the results shown in FIG. 7 , the dimension 4 in Example 1, that is, the dimension in the depth direction of the hole 200 was significantly increased compared to the dimension 4 in the comparative example. From this, it can be seen that the etching rate can be improved in Example 1 as well.

It was confirmed that also in Examples 2 and 3 in which the coating process and the third etching process were repeated, as in Example 1, the aspect ratio was improved compared to the comparative example. In addition, in Example 2 and Example 3, the size 3 is smaller than the size 3 in the comparative example. This is because the side surface of the hole 200 is coated with the Si-containing compound D, so that the side surface of the hole 200 can be suppressed from being over-etched in the subsequent third etching treatment. Moreover, compared with Example 1 in which the coating treatment was performed only once and then the third etching treatment was performed, in Example 2 and Example 3, the third etching treatment was performed multiple times, and each time a plurality of third etching treatments were performed Since the coating process is performed in all of the third etching processes, it is considered that the protection of the side surfaces of the hole 200 is strictly performed. That is, it is possible to perform etching at a higher aspect ratio by repeating the coating process and the etching process. In addition, since the dimension 3 is reduced, for example, when forming a capacitor for the hole 200 , the distance between electrodes can be reduced. Therefore, in Example 2 and Example 3, a capacitor with larger capacitance can be formed than in the comparative example.

Compared with the comparative example without the coating treatment and the third etching treatment, in Example 4 using the mixed gas of SiCl ₄ /He/O ₂ , the aspect ratio was also greatly improved, and the aspect ratio could be increased to 60 or more. Etching is performed.

Example 5 shows the case where the coating process was performed for 5 seconds using a mixed gas of SiCl ₄ /He, and then the coating process was further performed for 20 seconds using a mixed gas of SiCl ₄ /He/O ₂ result. In this case as well, it was confirmed that the aspect ratio was greatly improved compared with the comparative example. In addition, in Example 6, the selection ratio was significantly improved as compared with the comparative example. This is because the O (oxygen)-containing Si coating film of SiCl ₄ /He/O ₂ and the Si coating film of SiCl ₄ /He effectively suppress the etching of the sidewall.

Example 6 shows the results of the case where the temperature of the wafer W was 200° C. compared to the temperature of the wafer W of Example 1, which was 40° C., but was completely the same as that of Example 1. Also in this case, it was confirmed that the aspect ratio was greatly improved compared with the comparative example. This is because the portion where dimension 2 is narrowed is relatively widened at high temperature, thus being able to etch into a deeper portion of hole 200 . The reason why the dimension 2 becomes wider is that the chemical reaction of radicals is promoted when the temperature of the wafer W is high.

Example 7 shows the results of the case where the temperature of the wafer W is 120°C compared to the temperature of the wafer W of 40°C in Example 1, and the power of the second high-frequency power supply 40 during the second and third etching processes The value changed from 7800W to 10000W. That is, the electric power per unit area, that is, the electric power density, changed from 11 W/cm ² to 14.2 W/cm ² . Also in this case, it was confirmed that the aspect ratio was greatly improved compared with the comparative example. This is because the electric power density for attracting ions increases when the dimension 2 becomes wider due to high temperature. In other words, according to Examples 6 and 7, in order to have an aspect ratio of 60 or more, it is preferable that the temperature of the wafer W is 120° C. to 200° C., and that the power density of the second high-frequency power supply 40 is preferably 11 W/ cm ² ~14.2W/cm ² .

As mentioned above, although preferred embodiment of this invention was described, this invention is not limited to the said example. It is obvious to those skilled in the art that it is easy to think of various alterations or modifications within the scope of the technical concept described in the claims, and these of course also belong to the protection scope of the present invention.

Explanation of reference signs

1. Plasma processing device; 10. Wafer fixture; 11. Processing container; 12. Ground wire; 13. Base; 14. Insulation plate; 15. Support table; 20. Correction ring; 21. Cylindrical component; , heat-conducting gas tube; 30, the first high-frequency power supply; 31, the first matching device; 40, the second high-frequency power supply; 41, the second matching device; 42, the upper electrode; 50, the supporting member; 51, the electrode plate; 52. Electrode support plate; 53. Gas supply port; 54. Gas diffusion chamber; 55. Air hole; 72a. Etching gas supply part; 72b. Coating gas supply part; ;80, exhaust flow path; 90, exhaust port; 91, exhaust chamber; 92, exhaust pipe; 93, exhaust device; 100, annular magnetic body; 150, control unit; W, wafer; R , resist pattern; H, residual film thickness; D, Si-containing compound; M, etch mask.

Claims (5)

1. A plasma etching method, in which a high-frequency power is applied between an upper electrode and a lower electrode provided in a processing container to make a processing gas plasma, and oxidize the layered substrate. The silicon film layer and the silicon nitride layer are subjected to a plasma etching process using the silicon layer formed on the silicon nitride layer as a mask. It is characterized in that, in the plasma etching method, a film having A hole or groove with a specified aspect ratio, wherein the specified aspect ratio is 60 or more: performing a first etching process in which the silicon nitride layer is etched using plasma containing CF gas and plasma containing CHF gas, Next, a second etching process is performed, in which the silicon oxide film layer is etched with plasma containing CF gas, Next, depositing a Si-containing substance on the mask using a plasma of a Si-containing gas, Thereafter, a third etching process is performed in which the silicon oxide film layer is etched again by plasma containing CF gas in the state where the Si-containing substance is deposited on the mask. 2. The plasma etching method according to claim 1, wherein, A process of depositing a Si-containing substance on the mask and a third etching process of etching a silicon oxide film layer with the CF-containing gas are repeated. 3. The plasma etching method according to claim 1, wherein, The Si-containing gas is SiCl ₄ gas. 4. The plasma etching method according to claim 1, wherein, The Si-containing gas is a mixed gas of SiCl ₄ and O ₂ . 5. The plasma etching method according to claim 1, wherein, The temperature of the substrate in the second etching treatment and the third etching treatment is 120°C to 200°C, In the second etching process and the third etching process, high-frequency power for attracting ions is applied to the lower electrode, The power density of the high-frequency power to be applied is 11 W/cm ² to 14.2 W/cm ² .