CN104300928A - Differential to Single-Ended Converter - Google Patents

Abstract

The invention provides a differential-to-single-ended converter and a related method, which are used for converting a differential input signal into a single-ended output signal. The differential-to-single-ended converter comprises a first transistor, a second transistor, a third transistor, a fourth transistor and a current source pair. The first transistor and the second transistor are driven by the differential input signal. The first transistor and the second transistor have two first conductive terminals coupled together and two second conductive terminals not coupled together. The third transistor and the fourth transistor are driven by the differential input signal and are respectively connected in series with the first transistor and the second transistor. The current source pair is connected in series with the third transistor and the fourth transistor respectively, and has a common control terminal coupled to the second conduction terminal of the first transistor. The second conductive terminal of the second transistor is used for generating the single-ended output signal.

Description

Differential to Single-Ended Converter

technical field

Embodiments of the present invention generally relate to differential-to-single-ended converters, and more particularly to converters that convert a differential input signal into a single-ended output signal.

Background technique

In order to resist the noise transmitted from the power line and the semiconductor substrate, the internal signals in the integrated circuit can be processed in a differential mode. For example, a ring oscillator (ringoscillator) often uses a differential mode to generate a clock signal, which can avoid the influence of common mode noise on frequency.

However, the differential signal used in the differential mode requires at least two signal transmission lines, which will increase the complexity of the wiring and the pin count of the integrated circuit compared to one signal transmission line required by the single-ended signal. Therefore, the signals of most logic circuits in the integrated circuit adopt single-end mode (single-end mode), and the parts requiring high anti-noise adopt differential mode. The differential-to-single-ended converter is responsible for converting a differential input signal into a single-ended output signal, serving as a bridge in circuits using different signal modes.

FIG. 1 shows a known differential-to-single-ended converter 10, which includes two NMOS transistors N1 and N2, and two PMOS transistors P1 and P2. The differential-to-single-ended converter 10 can be regarded as a known differential amplifier. The non-inversion signal S-NON and the inversion signal S-INV constituting a differential signal are input to the gates of the NMOS transistors N1 and N2 respectively. The PMOS transistors P1 and P2 are combined to form a current mirror, and their common control terminal CON-O is connected to a drain of the PMOS transistor P1. The NMOS transistor N1 and the PMOS transistor P1 are connected in series between the power lines VDD and VSS. The NMOS transistor N2 and the PMOS transistor P2 are connected in series between the power lines VDD and VSS through the output terminal OUT. The output terminal OUT generates a single-ended signal S-ONE.

A good differential-to-single-ended converter should be able to quickly change the logic value of its single-ended signal as the logic value of the differential signal switches. In addition, the voltage slew rate of the differential-to-single-ended converter must also be fast. In this way, when receiving the differential clock signal provided by the ring oscillator to generate the single-ended clock signal, the duty cycle of the single-ended clock signal can be very close to the ideal value of 50%.

Contents of the invention

Embodiments of the present invention provide a differential-to-single-ended converter for converting a differential input signal into a single-ended output signal. The differential-to-single-ended converter includes first, second, third and fourth transistors, and a pair of current sources. The first transistor and the second transistor are driven by the differential input signal. The first transistor and the second transistor have two first conduction terminals coupled together, and two second conduction terminals not coupled together. The third transistor and the fourth transistor are driven by the differential input signal and are connected in series with the first transistor and the second transistor respectively. The current source pair is respectively connected in series with the third transistor and the fourth transistor, has a common control terminal coupled to the second conduction terminal of the first transistor. The second conducting end of the second transistor is used to generate the single-ended output signal.

Embodiments of the present invention further provide a signal conversion method for converting a differential signal into a single-ended signal. The differential signal includes a non-inversion signal and an inversion signal. The method includes: providing an output terminal for generating the single-ended signal; providing a current source; controlling the current source according to the non-reverse signal; and conducting a discharge path and a charge according to the reverse signal. One of the paths, and cut off the other one of the discharge path and the charge path, wherein, when the differential signal is a first logic value, the current source passes through the conduction charge path to the signal output terminal Charging, when the differential signal is a second logic value, the output end is discharged through the conducting discharge path.

Description of drawings

In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and understandable, the specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

Figure 1 shows a known differential-to-single-ended converter.

FIG. 2 and FIG. 3 show two differential-to-single-ended converters implemented according to the present invention.

FIG. 4 shows an integrated circuit using the differential-to-single-ended converter 20 of FIG. 2 .

Explanation of component numbers in the figure:

10, 20, 30 Differential to single-ended converter

52 Voltage Controlled Oscillator

54 logic circuit

CON, CON-O common control terminal

N1, N2, N11, N12 NMOS transistors

OUT output terminal

P1, P2, P11, P12, P21, P22 PMOS transistors

S-INV reverse signal

S-ONE single-ended signal

S-NON non-reverse signal

VCC, VDD, VSS Power lines

Detailed ways

FIG. 2 shows a differential-to-single-ended converter 20 according to an embodiment of the present invention. As shown in FIG. 2 , the differential-to-single-ended converter 20 has two NMOS transistors N11 and N12 and four PMOS transistors P11 , P12 , P21 and P22 . In one embodiment, the element sizes of the NMOS transistors N11 and N12 are about the same; the element sizes of the PMOS transistors P11 and P12 are about the same; and the element sizes of the PMOS transistors P21 and P22 are about the same.

The NMOS transistors N11 and N12 are used as a differential pair, and their gate terminals are respectively driven by the non-inversion signal S-NON and the inversion signal S-INV of the differential signal. The sources of the NMOS transistors N11 and N12 are coupled to the power line VSS, while the drains of the NMOS transistors N11 and N12 are not coupled together. The operating states of the NMOS transistors N11 and N12 are complementary. In other words, when the NMOS transistor N11 is turned on, the NMOS transistor N12 is turned off, and vice versa.

The PMOS transistors P11 and P12 are another differential pair, and their gate terminals are respectively driven by the non-inversion signal S-NON and the inversion signal S-INV of the differential signal. As shown in FIG. 2 , the PMOS transistors P11 and P12 are connected in series with the NMOS transistors N11 and N12 respectively. In FIG. 2 , the operation states of the PMOS transistors P11 and P12 are complementary. In other words, when the PMOS transistor P11 is turned on, the PMOS transistor P12 is turned off, and vice versa.

The PMOS transistors P21 and P22 can be regarded as a pair of current sources, the gate terminals of which are connected together as a common control terminal CON, which is connected to the drain terminal of the NMOS transistor N11, which is also the drain terminal of the PMOS transistor P11. The PMOS transistors P21 and P22 are connected in series with the PMOS transistors P11 and P12 respectively. Source terminals of the PMOS transistors P21 and P22 are coupled to the power line VDD.

The drain terminal of the NMOS transistor N12 is also the drain terminal of the PMOS transistor P12, which serves as a signal output terminal OUT, which can generate a single-ended output signal S-ONE.

In the following operations, the power line VDD is 1.1V, and the power line VSS is 0V. There is no rail-to-rail (rail-to-rail) voltage change between the non-inverted signal S-NON and the inverted signal S-INV. 0V to 0.6V is used as an example, but not to limit the present invention. When the voltages of the non-reverse signal S-NON and the reverse signal S-INV are 0V and 0.6V respectively, the logic value of the differential signal is "0"; otherwise, when the non-reverse signal S-NON and the reverse signal When the voltages of S-INV are 0.6V and 0V respectively, the logic value of the differential signal is "1".

When the differential signal is "0", the NMOS transistor N11 and the PMOS transistor P12 are turned off, and the NMOS transistor N12 and the PMOS transistor P11 are turned on. Therefore, the signal output terminal OUT is pulled down to 0V by the discharge path provided by the turned-on NMOS transistor N12, and the logic value of the single-ended output signal S-ONE is "0". At this time, the common control terminal CON is equivalently connected to the drain terminal of the PMOS transistor P21, so the PMOS transistors P21 and P22 form an equivalent current mirror. The PMOS transistors P21 and P22 are respectively used as two charging current sources to charge the two drains of the PMOS transistors P21 and P22, so the voltages of the two drains and the common control terminal CON can be about 1V or slightly lower than 1V.

When the differential signal changes from "0" to "1", the non-inversion signal S-NON starts to rise from 0V, and the inversion signal S-INV starts to fall from 0.6V. Once the voltage of the non-inversion signal S-NON is higher than the inversion signal S-INV, the NMOS transistor N11 and the PMOS transistor P12 are turned on, and the NMOS transistor N12 and the PMOS transistor P11 are turned off. The charging current source of the PMOS transistor P21 cannot charge the common control terminal CON because the PMOS transistor P11 is turned off. Therefore, the common control terminal CON is rapidly discharged to 0V through a discharge path provided by the turned-on NMOS transistor N11 . Turning off the NMOS transistor N12 is equivalent to cutting off the discharge path from the signal output terminal OUT to the power supply line VSS. At this time, the PMOS transistor P22 acts as a charging current source, and charges the signal output terminal OUT through the charging path provided by the turned-on PMOS transistor P12 . Because the voltage of the common control terminal CON is 0V, the gate-to-source voltage of the PMOS transistor P22 will be -1V, which is the maximum possible negative value under the system powered by the power line VDD and the power line VSS, Therefore, the PMOS transistor P22 will quickly charge the signal output terminal OUT with the maximum charging current. Finally, the voltage of the single-ended output signal S-ONE is 1V, and the logic value is "1".

When the differential signal changes from "1" to "0", the non-inversion signal S-NON starts to drop from 0.6V, while the inversion signal S-INV starts to rise from 0V. Once the voltage of the non-inversion signal S-NON is lower than the inversion signal S-INV, the NMOS transistor N12 and the PMOS transistor P11 are turned on, and the NMOS transistor N11 and the PMOS transistor P12 are turned off. At this time, the charging path provided by the PMOS transistor P12 is cut off. The turned-on NMOS transistor N12 provides a discharge path to discharge the signal output terminal OUT. Therefore, the voltage of the single-ended output signal S-ONE will quickly drop from 1V to 0V, and the logic value becomes "0". Turning off the NMOS transistor N11 decouples the common control terminal CON from the power line VSS, that is, disconnects it from the power line VSS. The charging current source of the PMOS transistor P21 will charge the common control terminal CON to about 1V-Vthp through the turned-on PMOS transistor P11, where Vthp is the threshold voltage of the PMOS transistor P21. The charging current source of the PMOS transistor P22 will charge the drain terminal of the PMOS transistor P22 to about 1V and then stop.

In the embodiment of FIG. 2, the voltage swing (voltage swing) of the non-inverting signal S-NON and the inverting signal S-INV is 0.6V, which is smaller than the voltage swing of the single-ended output signal S-ONE (which is 1V ). The low logic levels of the non-inversion signal S-NON, the inversion signal S-INV, and the single-ended output signal S-ONE are all 0V. The high logic levels of the non-inversion signal S-NON and the inversion signal S-INV are 0.6V, and the high logic level of the single-ended output signal S-ONE is 1V.

With proper design, the falling slew rate and rising slew rate of the single-ended output signal S-ONE in Figure 2 can be quite fast, higher than the falling slew rate and rising slew rate of the single-ended output signal S-ONE in Figure 1 . When the differential signal in Figure 2 is converted from "1" to "0", because even if the charging current provided by the PMOS transistor P22 is temporarily not 0, the reverse signal S-INV will first cut off the charging current provided by the PMOS transistor P12 path, so that the signal output terminal OUT is only discharged by the NMOS transistor N12 and falls rapidly. When the differential signal is converted from "0" to "1", because the inversion signal S-INV cuts off the discharge path provided by the NMOS transistor N12, and the PMOS transistor P22 passes through the charging path provided by the PMOS transistor P12, the signal output The charging current at the terminal OUT is the maximum value, so the rising slew rate of the single-ended output signal S-ONE will be quite fast.

When the differential signal in Figure 2 is switched, the charging path and discharging path to the signal output terminal OUT will be quickly formed or cut off, so the single-ended output signal S-ONE on the signal output terminal OUT has an effect on the differential signal The reaction speed will also be quite fast.

The falling slew rate and rising slew rate of the single-ended output signal S-ONE in Figure 1 are theoretically slower than those in Figure 2. For example, when the differential signal in FIG. 1 is to be converted from "1" to "0", although the NMOS transistors N2 and N1 are turned on and off quickly respectively, the signal output terminal OUT will not be turned on quickly at the beginning. Decline, must wait until the common control terminal CON-O is charged to a certain extent, until the charging current provided by the PMOS transistor P2 is lower than the discharge current provided by the NMOS transistor N2, the voltage of the signal output terminal OUT will start to "slowly" decline. Therefore, the response speed and falling slew rate of the single-ended output signal S-ONE in Fig. 1 will be relatively small.

Similarly, when the differential signal in Figure 1 is to be converted from "0" to "1", although the NMOS transistors N1 and N2 are quickly turned on and off respectively, the common control terminal CON-O cannot be lowered to 0V, Clamped because it is limited by the MOS diode formed by PMOS transistor P1. Therefore, the charging current of the PMOS transistor P2 to the signal output terminal OUT cannot reach the maximum possible current of the PMOS transistor P2. Therefore, the rising slew rate of the single-ended output signal S-ONE in FIG. 1 is also quite limited.

Because the single-ended output signal S-ONE in Figure 2 responds very quickly to the differential signal (consisting of the non-inverted signal S-NON and the inverted signal S-INV), and the single-ended output signal S-ONE The rising/falling conversion rate is quite high, so when the duty cycle of the differential signal is 50%, as long as the proper design is made, the single-ended output signal S-ONE in Fig. %Working period.

FIG. 3 shows a differential-to-single-ended converter 30 according to another embodiment of the present invention. The differential-to-single-ended converter 30 in FIG. 3 and the differential-to-single-ended converter 20 in FIG. 2 are complementary to each other. The operation and principle of the differential-to-single-ended converter 30 can be understood by analogy for those with general circuit design knowledge based on the teaching and description of FIG. 2 , so it will not be repeated here.

FIG. 4 shows an integrated circuit using the differential-to-single-ended converter 20 of FIG. 2 . The voltage-controlled oscillator 52 can generate a clock signal, which is processed by two inverters powered by the 0.6V power line VCC and the 0V power line VSS to generate a non-inverted signal S-NON and an inverted signal S-INV , sent to the differential-to-single-ended converter 20, as shown in FIG. 4 . The differential-to-single-ended converter 20 generates a 50% duty cycle single-ended output signal S-ONE, which is sent to the logic circuit after being strengthened by two inverters powered by 1V power line VDD and 0V power line VSS 54.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection should be defined by the claims.

Claims (13)

1. A differential to single-end converter (differential to single-end converter), used to convert a differential input signal into a single-end output signal, the differential to single-end converter includes: A first transistor and a second transistor, driven by the differential input signal, the first transistor and the second transistor have two first conducting terminals coupled together, and two second conducting terminals not coupled together conduction end; A third transistor and a fourth transistor, driven by the differential input signal, are connected in series with the first transistor and the second transistor respectively; a pair of current sources, respectively connected in series with the third transistor and the fourth transistor, having a common control terminal coupled to the second conduction terminal of the first transistor; Wherein, the second conducting end of the second transistor is used to generate the single-ended output signal. 2. The differential-to-single-ended converter according to claim 1, wherein the first transistor and the second transistor are first-type transistors, the third transistor and the fourth transistor are second-type transistors, and the The first type transistor is complementary to the second type transistor. 3. The differential-to-single-ended converter according to claim 1, wherein the pair of current sources comprises a fifth transistor and a sixth transistor, which are connected in series with the third transistor and the fourth transistor respectively, and the fifth transistor A common control terminal of the transistor and the sixth transistor is connected to the second conduction terminal of the first transistor. 4. The differential-to-single-ended converter according to claim 1, wherein the operating states of the first transistor and the second transistor are complementary, and the operating states of the third transistor and the fourth transistor are complementary. 5. The differential-to-single-ended converter according to claim 1, wherein the first transistor and the second transistor have approximately the same element size, the third transistor and the fourth transistor have approximately the same element size, and the current The elements of the source pair are about the same size. 6. The differential-to-single-ended converter according to claim 1, characterized in that, the differential-to-single-ended converter comprises a high-voltage power supply line and a low-voltage power supply line, the two of the first transistor and the second transistor The first conducting end is coupled to the low voltage power line, and the current source pair is coupled to the high voltage power line. 7. The differential-to-single-ended converter according to claim 1, wherein the differential input signal is composed of a non-inverted signal and an inverted signal, respectively driving the first transistor and the second transistor. 8. The differential-to-single-ended converter of claim 7, wherein voltage swings of the non-inverting signal and the inverting signal are smaller than voltage swings of the single-ended output signal. 9. The differential-to-single-ended converter of claim 8, wherein the non-inverting signal, the inverting signal, and the single-ended output signal share a low logic level. 10. A signal conversion method for converting a differential signal into a single-ended signal, the differential signal comprising a non-inverted signal and an inverted signal, the method comprising: providing an output terminal for generating the single-ended signal; providing a current source; controlling the current source according to the non-inverting signal; and According to the reverse signal, one of a discharge path and a charge path is turned on, and the other one of the discharge path and the charge path is cut off, wherein, when the differential signal is a first logic value, the current The source charges the output terminal through the conductive charging path, and when the differential signal is a second logic value, the output terminal discharges through the conductive discharging path. 11. The signal conversion method according to claim 10, wherein the step of controlling the current source according to the non-inverting signal comprises: controlling a control terminal of the current source to be coupled to a low voltage according to the non-inverting signal source line to maximize the charge current provided by this current source. 12. The signal converting method of claim 10, further comprising: controlling the current source to be approximately 0 according to the non-reverse signal when the discharge path is turned on according to the reverse signal. 13. The signal conversion method of claim 11, further comprising: when the discharge path is turned on according to the reverse signal, controlling the control terminal to disconnect from the low-voltage power line according to the non-reverse signal.