CN104281544B - Memory controller and signal generating method thereof - Google Patents
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Abstract
本发明提供一种存储器控制器及其信号产生方法。用以操控一第一存储器模块,该方法包括下列步骤:产生信号周期为一单位时间的一第一时脉信号;产生信号周期为该单位时间的一指令信号,其中,该指令信号中包括多个指令群,每一该指令群具有连续的一第一个指令及一第二个指令;产生信号周期为二倍于该单位时间的一定址信号组;将该第一时脉信号的一第一信号沿设定于该指令信号的安全相位区间;以及将该第一时脉信号的一第二信号沿设定于该指令信号与该定址信号组的安全相位区间。
The present invention provides a memory controller and a signal generation method thereof. The method is used to control a first memory module, and the method includes the following steps: generating a first clock signal with a signal period of a unit time; generating a command signal with a signal period of the unit time, wherein the command signal includes a plurality of command groups, each of which has a first command and a second command that are continuous; generating an address signal group with a signal period of twice the unit time; setting a first signal edge of the first clock signal in a safe phase interval of the command signal; and setting a second signal edge of the first clock signal in a safe phase interval between the command signal and the address signal group.
Description
技术领域technical field
本发明有关于存储器领域,且特别是有关于一种存储器控制器及其信号产生方法。The present invention relates to the field of memory, and in particular to a memory controller and a signal generation method thereof.
背景技术Background technique
一般来说,存储器控制器(memory controller)连接至存储器模块,可将数据写入存储器模块或者由存储器模块中读取数据。现今最普遍的存储器模块即为双倍数据速率(double data rate,以下简称DDR)存储器模块。Generally, a memory controller (memory controller) is connected to the memory module, and can write data into the memory module or read data from the memory module. The most common memory module nowadays is a double data rate (DDR) memory module.
请参照图1A与图1B,其所绘示为存储器控制器与存储器模块之间的连接关系以及控制信号眼图(eye diagram)示意图。存储器控制器100与DDR存储器模块110设计于电路板(PCB)上,控制信号包括时脉信号(CLK1)、地址信号A[15:0]、指令信号CMD及区块控制信号BANK[2:0]。指令信号CMD包括写入致能信号(WE)、列地址触发信号(row address strobe,RAS)及行地址触发信号(column address strobe,CAS)。区块控制信号BANK[2:0]包括3脚位(pin),地址信号A[15:0]包括16脚位。Please refer to FIG. 1A and FIG. 1B , which are schematic diagrams of the connection relationship between the memory controller and the memory module and the control signal eye diagram. The memory controller 100 and the DDR memory module 110 are designed on a circuit board (PCB), and the control signals include a clock signal (CLK1), an address signal A[15:0], a command signal CMD and a block control signal BANK[2:0 ]. The command signal CMD includes a write enable signal (WE), a row address strobe (RAS) and a column address strobe (CAS). The block control signal BANK[2:0] includes 3 pins, and the address signal A[15:0] includes 16 pins.
存储器控制器100利用控制信号来操控DDR存储器模块110,例如,读取数据、写入数据等等。由于DDR存储器模块110根据时脉信号(CLK1)的信号沿(例如上升沿或下降沿下降沿)来拴锁地址信号A[15:0]、指令信号CMD、区块控制信号BANK[2:0]上的数据。因此,存储器控制器100必须适当地调整时脉信号(CLK1)的相位(phase),使得DDR存储器模块110得以根据时脉信号(CLK1)的信号沿而顺利地拴锁(latch)住所有控制信号中的数据。为了方便说明,以下皆以时脉信号(CLK1)的上升沿来拴锁信号,但并不限定于此。The memory controller 100 manipulates the DDR memory module 110 using control signals, for example, to read data, write data, and so on. Since the DDR memory module 110 latches the address signal A[15:0], the command signal CMD, and the block control signal BANK[2:0] according to the signal edge (for example, rising edge or falling edge) of the clock signal (CLK1). ] on the data. Therefore, the memory controller 100 must properly adjust the phase of the clock signal (CLK1), so that the DDR memory module 110 can smoothly latch all control signals according to the signal edge of the clock signal (CLK1). data in . For convenience of description, the rising edge of the clock signal ( CLK1 ) is used to latch the signal below, but it is not limited thereto.
如图所示,时脉信号(CLK1)的周期为T,地址信号A[15:0]、指令信号CMD、区块控制信号BANK[2:0]的信号周期也是T。然而,由于每一条控制信号的驱动能力不同,所以控制信号的安全相位区间(或称为数据有效区间)会小于T。因此,存储器控制器100必须将时脉信号(CLK1)的上升沿调整到安全相位区间之内,以避免在控制信号的安全相位区间的外拴锁这些控制信号而造成错误。As shown in the figure, the cycle of the clock signal ( CLK1 ) is T, and the signal cycles of the address signal A[15:0], the command signal CMD, and the block control signal BANK[2:0] are also T. However, since the driving capability of each control signal is different, the safe phase interval (or data valid interval) of the control signal will be smaller than T. Therefore, the memory controller 100 must adjust the rising edge of the clock signal ( CLK1 ) within the safe phase interval to avoid errors caused by latching the control signals outside the safe phase interval of the control signals.
时脉信号(CLK1)的上升沿调整至指令信号CMD的安全相位区间(Eye_cmd)、区块控制信号BANK[2:0]的安全相位区间(Eye_bank)以及地址信号A[15:0]的安全相位区间(Eye_addr)之内。很明显地,上述信号的安全相位区间皆小于T,尤其是地址信号A[15:0]的数目众多,所以其安全相位区间(Eye_addr)最小。The rising edge of the clock signal (CLK1) is adjusted to the safe phase interval (Eye_cmd) of the command signal CMD, the safe phase interval (Eye_bank) of the block control signal BANK[2:0] and the safe phase interval of the address signal A[15:0] within the phase interval (Eye_addr). Obviously, the safe phase intervals of the above signals are all smaller than T, especially the number of address signals A[15:0] is large, so the safe phase interval (Eye_addr) is the smallest.
随着存储器(DRAM)模块存取的速度越来越快,已从DDR2模块进步到DDR3与DDR4模块。当存储器模块速度提高的同时,讯号品质会大幅降低,再加上电路板(PCB)的变异以及存储器模块的各个脚位的不同,会造成控制信号由存储器控制器到存储器模块的时间有些许差异,以及信号变化时的上升时间(rise time)及下降时间(fall time)也不同,而导致控制信号的安全相位区间变小。As the access speed of memory (DRAM) modules is getting faster and faster, it has progressed from DDR2 modules to DDR3 and DDR4 modules. When the speed of the memory module is increased, the signal quality will be greatly reduced. In addition, the variation of the circuit board (PCB) and the different pins of the memory module will cause a slight difference in the time of the control signal from the memory controller to the memory module. , and the rise time (rise time) and fall time (fall time) when the signal changes are also different, resulting in a smaller safe phase interval of the control signal.
请参照图2A图与图2B,其所绘示为存储器控制器与二个存储器模块之间的连接关系以及控制信号眼图示意图。利用存储器控制器200来控制二个DDR存储器模块210、220时,第一时脉信号(CLK1)连接至第一DDR存储器模块210,第二时脉信号(CLK2)连接至第二DDR存储器模块220,而共用地址信号A[15:0]、指令信号CMD、区块控制信号BANK[2:0]。第一DDR存储器模块210根据第一时脉信号(CLK1)拴锁地址信号A[15:0]、指令信号CMD、区块控制信号BANK[2:0]上的数据;第二DDR存储器模块220根据第二时脉信号(CLK2)拴锁地址信号A[15:0]、指令信号CMD、区块控制信号BANK[2:0]上的数据。Please refer to FIG. 2A and FIG. 2B , which are diagrams showing the connection relationship between the memory controller and two memory modules and the eye diagrams of the control signals. When using the memory controller 200 to control the two DDR memory modules 210, 220, the first clock signal (CLK1) is connected to the first DDR memory module 210, and the second clock signal (CLK2) is connected to the second DDR memory module 220 , and share the address signal A[15:0], the command signal CMD, and the block control signal BANK[2:0]. The first DDR memory module 210 latches the data on the address signal A[15:0], the command signal CMD, and the block control signal BANK[2:0] according to the first clock signal (CLK1); the second DDR memory module 220 Data on the address signal A[15:0], the command signal CMD, and the block control signal BANK[2:0] are latched according to the second clock signal (CLK2).
由于存储器控制器200必需要推动(drive)存储器的脚位数目为图1A图的两倍,加上电路板(PCB)的差异,使得信号的品质更加恶化,尤其是地址信号A[15:0]。相较于图1B,图2B所示的安全相位区更小,尤其是地址信号A[15:0]的安全相位区间(Eye_addr)变得非常小。由于地址信号A[15:0]的安全相位区间(Eye_addr)很小,使得存储器控制器200更不容易调整出适当的时脉信号(CLK1、CLK2)相位,让二个DDR存储器模块210、220正确地拴锁控制信号。Since the memory controller 200 must drive (drive) the number of pins of the memory to be twice that of FIG. ]. Compared with FIG. 1B , the safe phase region shown in FIG. 2B is smaller, especially the safe phase region (Eye_addr) of the address signal A[15:0] becomes very small. Since the safe phase interval (Eye_addr) of the address signal A[15:0] is very small, it is not easy for the memory controller 200 to adjust the phase of the appropriate clock signal (CLK1, CLK2), so that the two DDR memory modules 210, 220 Correctly latch control signals.
由于在高速的情况下所有信号的品质很难被一一地优化(qualify),所以需要一个有效的解决方案来解决上述的问题。Since the quality of all signals is difficult to be optimized (qualify) one by one under the condition of high speed, an effective solution is needed to solve the above problems.
发明内容Contents of the invention
有鉴于此,本发明的目的在于提出一种存储器控制器及其信号产生方法,本发明限定指令信号的产生方式,并将部份的控制信号的安全相位区间予以扩大,使得存储器模块可以正常操作。In view of this, the purpose of the present invention is to provide a memory controller and its signal generation method. The present invention limits the generation method of command signals, and expands the safe phase range of part of the control signals, so that the memory module can operate normally. .
本发明提出一种存储器控制器的信号产生方法,用以操控第一存储器模块,包括下列步骤:产生信号周期为一单位时间的第一时脉信号;产生信号周期为该单位时间的指令信号,指令信号中包括多个指令群,每一指令群具有连续的第一个指令及第二个指令;产生信号周期为二倍于该单位时间的一定址信号组;将第一时脉信号的第一信号沿设定于指令信号的安全相位区间;以及将第一时脉信号的第二信号沿设定于指令信号与定址信号组的安全相位区间。The present invention proposes a method for generating a signal of a memory controller for controlling a first memory module, comprising the following steps: generating a first clock signal whose signal period is a unit time; generating a command signal whose signal period is the unit time, The instruction signal includes a plurality of instruction groups, each instruction group has a continuous first instruction and a second instruction; an address signal group whose signal cycle is twice the unit time is generated; the first clock signal of the first clock signal A signal edge is set in the safe phase interval of the command signal; and a second signal edge of the first clock signal is set in the safe phase interval of the command signal and the address signal group.
本发明还提出一种存储器控制器,连接至第一存储器模块,存储器控制器包括:时脉产生单元,产生信号周期为单位时间的第一时脉信号至第一存储器模块;控制信号转译单元,产生信号周期为单位时间的指令信号至第一存储器模块,指令信号包括多个指令群,每一该指令群具有连续的第一个指令与第二个指令;以及地址转译单元,产生信号周期为二倍于该单位时间的定址信号组至第一存储器模块;其中,时脉产生单元将第一时脉信号的第一信号沿设定于指令信号的安全相位区间;以及将第一时脉信号的第二信号沿设定于指令信号与定址信号组的安全相位区间。The present invention also proposes a memory controller connected to the first memory module. The memory controller includes: a clock generation unit that generates a first clock signal with a signal period of unit time to the first memory module; a control signal translation unit, Generate an instruction signal with a signal period as unit time to the first memory module, the instruction signal includes a plurality of instruction groups, each of which has a continuous first instruction and a second instruction; and an address translation unit that generates a signal period of The address signal group twice the unit time is sent to the first memory module; wherein, the clock generating unit sets the first signal edge of the first clock signal to the safe phase interval of the command signal; and the first clock signal The second edge of the signal is set in the safe phase interval of the command signal and the addressing signal group.
为了对本发明的上述及其他方面有更佳的了解,下文例举较佳实施例,并配合附图,作详细说明如下:In order to have a better understanding of the above and other aspects of the present invention, the preferred embodiments are exemplified below, together with the accompanying drawings, and described in detail as follows:
附图说明Description of drawings
图1A与图1B绘示存储器控制器与存储器模块之间的连接关系以及控制信号眼图示意图。FIG. 1A and FIG. 1B are diagrams illustrating the connection relationship between a memory controller and a memory module and eye diagrams of control signals.
图2A与图2B绘示存储器控制器与二个存储器模块之间的连接关系以及控制信号眼图示意图。2A and 2B are diagrams illustrating the connection relationship between the memory controller and two memory modules and the eye diagrams of the control signals.
图3A与图3B绘示根据本发明实施例的存储器控制器与存储器模块的连接关系及其控制信号眼图示意图。3A and 3B are diagrams illustrating the connection relationship between the memory controller and the memory module and the eye diagrams of the control signals according to an embodiment of the present invention.
图4A与图4B绘示根据本发明其他实施例的存储器控制器与存储器模块的连接关系及其控制信号眼图示意图。4A and 4B are diagrams illustrating the connection relationship between the memory controller and the memory module and their control signal eye diagrams according to other embodiments of the present invention.
图5绘示根据本发明具体实施例的存储器控制器的信号产生方法流程图。FIG. 5 is a flowchart of a signal generating method of a memory controller according to an embodiment of the invention.
符号说明Symbol Description
100、200、400:存储器控制器100, 200, 400: memory controller
110:DDR存储器模块110: DDR memory module
210、410:第一DDR存储器模块210, 410: the first DDR memory module
220、420:第二DDR存储器模块220, 420: the second DDR memory module
402:地址转译单元402: address translation unit
404:控制信号转译单元404: Control signal translation unit
406:时脉产生单元406: clock generation unit
S502~S512:步骤流程S502~S512: step process
具体实施方式detailed description
以二个存储器模块为例,控制信号包括第一时脉信号(CLK1)、第二时脉信号(CLK2)、指令信号CMD、区块控制信号BANK[2:0]及地址信号A[15:0]。指令信号CMD包括写入致能信号(WE)、列地址触发信号(row address strobe,RAS)及行地址触发信号(columnaddress strobe,CAS)。举例而言,3脚位(pin)的区块控制信号为BANK[2:0];而16脚位的地址信号为A[0:15]。再者,当存储器模块中晶粒(chip)的组成不同时,控制信号的数目也会有差异。换句话说,上述的控制信号数目仅是本发明的一个实施例,其并非用来限制本发明。Taking two memory modules as an example, the control signals include the first clock signal (CLK1), the second clock signal (CLK2), the command signal CMD, the block control signal BANK[2:0] and the address signal A[15: 0]. The command signal CMD includes a write enable signal (WE), a row address strobe (RAS) and a column address strobe (CAS). For example, the 3-pin bank control signal is BANK[2:0]; and the 16-pin address signal is A[0:15]. Furthermore, when the composition of chips in the memory module is different, the number of control signals will also be different. In other words, the above-mentioned number of control signals is only an embodiment of the present invention, and is not intended to limit the present invention.
DDR存储器模块接收指令信号后,据以执行的指令包括无运作指令(NOP)、区块总线充电指令(PRE)、驱动区块总线指令(ACT)、写入指令(Write)与读取指令(Read)。After the DDR memory module receives the instruction signal, the instructions to be executed include no operation instruction (NOP), block bus charge instruction (PRE), drive block bus instruction (ACT), write instruction (Write) and read instruction ( Read).
而于NOP指令时,不需理睬(don’t care)16脚位的地址信号A[15:0]以及3脚位的区块控制信号BANK[2:0]。亦即,执行NOP指令时,可忽略地址信号A[15:0]以及区块控制信号BANK[2:0]上的数据。In the NOP instruction, it is unnecessary to ignore (don’t care) the address signal A[15:0] of the 16-pin and the block control signal BANK[2:0] of the 3-pin. That is, when the NOP instruction is executed, the data on the address signal A[15:0] and the bank control signal BANK[2:0] can be ignored.
在一具体实施例中,根据NOP指令的特性发展出存储器控制器的信号产生方法。举例而言,在存储器控制器输出的指令信号CMD中以二个指令为一个指令群。而指令群中依序为指令1(cmd1)与指令2(cmd2),较佳地,指令1(cmd1)仅能是NOP指令;而指令2(cmd2)则可以是上述任一种指令。In a specific embodiment, a signal generating method of the memory controller is developed according to the characteristics of the NOP instruction. For example, in the command signal CMD output by the memory controller, two commands are regarded as a command group. The command group includes command 1 (cmd1) and command 2 (cmd2) in sequence. Preferably, command 1 (cmd1) can only be a NOP command; and command 2 (cmd2) can be any one of the above commands.
请参照图3A与图3B,其所绘示为本发明存储器控制器与存储器模块的连接关系及其控制信号眼图示意图。存储器控制器400包括地址转译单元402、控制信号转译单元404以及时脉产生单元406。时脉产生单元406产生第一时脉信号(CLK1)、第二时脉信号(CLK2);控制信号转译单元404产生指令信号CMD;而地址转译单元402产生区块控制信号BANK[2:0]以及地址信号A[15:0]。时脉产生单元406可视DDR存储器模块的数目,分别产生一个时脉信号至个别的DDR存储器模块。Please refer to FIG. 3A and FIG. 3B , which illustrate the connection relationship between the memory controller and the memory module and the eye diagrams of the control signals of the present invention. The memory controller 400 includes an address translation unit 402 , a control signal translation unit 404 and a clock generation unit 406 . The clock generation unit 406 generates a first clock signal (CLK1) and a second clock signal (CLK2); the control signal translation unit 404 generates a command signal CMD; and the address translation unit 402 generates a block control signal BANK[2:0] and address signal A[15:0]. Depending on the number of DDR memory modules, the clock generating unit 406 generates a clock signal to each DDR memory module.
如图3A所示,第一时脉信号(CLK1)连接至第一DDR存储器模块410,第二时脉信号(CLK2)连接至第二DDR存储器模块420,而第一DDR存储器模块410与第二DDR存储器模块420共用地址信号A[15:0]、指令信号CMD、区块控制信号BANK[2:0]。第一DDR存储器模块210根据第一时脉信号(CLK1)拴锁地址信号A[15:0]、指令信号CMD、区块控制信号BANK[2:0]上的数据;第二DDR存储器模块220根据第二时脉信号(CLK2)拴锁地址信号A[15:0]、指令信号CMD、区块控制信号BANK[2:0]上的数据。As shown in FIG. 3A, the first clock signal (CLK1) is connected to the first DDR memory module 410, the second clock signal (CLK2) is connected to the second DDR memory module 420, and the first DDR memory module 410 and the second The DDR memory module 420 shares the address signal A[15:0], the command signal CMD, and the bank control signal BANK[2:0]. The first DDR memory module 210 latches the data on the address signal A[15:0], the command signal CMD, and the block control signal BANK[2:0] according to the first clock signal (CLK1); the second DDR memory module 220 Data on the address signal A[15:0], the command signal CMD, and the block control signal BANK[2:0] are latched according to the second clock signal (CLK2).
于此实施例中,在存储器控制器400发出的指令信号中包括多个指令群,每个指令群中皆包括2个连续指令。如图3B所示,第一个指令群依序为指令1(cmd1)、指令2(cmd2);第二个指令群依序为指令1’(cmd1’)、指令2’(cmd2’);以及第三个指令群依序为指令1”(cmd1”)、指令2”(cmd2”)。In this embodiment, the command signal sent by the memory controller 400 includes multiple command groups, and each command group includes two consecutive commands. As shown in Figure 3B, the first command group is command 1 (cmd1) and command 2 (cmd2); the second command group is command 1' (cmd1') and command 2' (cmd2'); And the third command group is command 1" (cmd1") and command 2" (cmd2") in sequence.
于此实施例中,限定指令群中的第一个指令仅可以是NOP指令,而DDR存储器模块410、420执行NOP指令时,不需理睬地址信号A[0:15]以及区块控制信号BANK[2:0]上的数据。较佳地,存储器控制器400在产生指令群中的第一个指令时,其第一时脉信号(CLK1)与第二时脉信号(CLK2)的上升沿并不限定于要落在地址信号A[0:15]以及区块控制信号BANK[2:0]的安全相位区间Eye_addr与Eye_bank之内。换句话说,存储器控制器400在产生指令群中的第一个指令时,就算第一时脉信号(CLK1)与第二时脉信号(CLK2)的上升沿落在地址信号A[0:15]以及区块控制信号BANK[2:0]的安全相位区间Eye_addr与Eye_bank之外,也不会有任何错误发生。In this embodiment, the first command in the limited command group can only be a NOP command, and when the DDR memory modules 410, 420 execute the NOP command, it is not necessary to ignore the address signal A[0:15] and the block control signal BANK data on [2:0]. Preferably, when the memory controller 400 generates the first instruction in the instruction group, the rising edges of the first clock signal (CLK1) and the second clock signal (CLK2) are not limited to fall on the address signal A[0:15] and the safe phase interval Eye_addr and Eye_bank of the block control signal BANK[2:0]. In other words, when the memory controller 400 generates the first command in the command group, even if the rising edges of the first clock signal ( CLK1 ) and the second clock signal ( CLK2 ) fall on the address signal A[0:15 ] and outside the safe phase range Eye_addr and Eye_bank of the block control signal BANK[2:0], there will be no error.
请参照图3B,存储器控制器400中时脉产生器406所输出的第一时脉信号(CLK1)与第二时脉信号(CLK2)的周期为T。并且,存储器控制器400中控制信号转译单元404输出的指令信号CMD的信号周期为T;存储器控制器400中地址转译单元402输出的区块控制信号BANK[2:0]、地址信号A[0:15]的信号周期则为2T。应注意到,地址信号A[0:15]以及区块控制信号BANK[2:0]的安全相位区间Eye_addr与Eye_bank已经变大。Referring to FIG. 3B , the period of the first clock signal ( CLK1 ) and the second clock signal ( CLK2 ) output by the clock generator 406 in the memory controller 400 is T. Referring to FIG. Moreover, the signal cycle of the command signal CMD output by the control signal translation unit 404 in the memory controller 400 is T; the block control signal BANK[2:0] and the address signal A[0] output by the address translation unit 402 in the memory controller 400 :15] the signal period is 2T. It should be noted that the safety phase intervals Eye_addr and Eye_bank of the address signal A[0:15] and the bank control signal BANK[2:0] have become larger.
如图3B所示,在时间点t0、t2、t4时依序为第一指令群中的指令1(cmd1)、第二指令群中的指令1(cmd1’)、第三指令群中的指令1”(cmd1”)。二个时脉信号(CLK1、CLK2)的上升沿位于指令信号CMD的安全相位区间(Eye_cmd),但是位于地址信号A[0:15]以及区块控制信号BANK[2:0]的安全相位区间Eye_addr与Eye_bank之外。亦即,虽然二个DDR存储器模块410、420在t0、t2、t4时间点所接收的指令无法确实得到地址信号A[0:15]以及区块控制信号BANK[2:0]的正确数据,但是二个DDR存储器模块410、420仍可以正确地执行NOP指令。As shown in FIG. 3B, at time points t0, t2, and t4, there are command 1 (cmd1) in the first command group, command 1 (cmd1') in the second command group, and commands in the third command group in sequence. 1" (cmd1"). The rising edges of the two clock signals (CLK1, CLK2) are located in the safe phase interval (Eye_cmd) of the command signal CMD, but in the safe phase interval of the address signal A[0:15] and the block control signal BANK[2:0] Outside of Eye_addr and Eye_bank. That is, although the instructions received by the two DDR memory modules 410, 420 at time points t0, t2, and t4 cannot definitely obtain the correct data of the address signal A[0:15] and the block control signal BANK[2:0], But the two DDR memory modules 410, 420 can still execute the NOP instruction correctly.
更进一步地,于时间点t1、t3、t5时依序为第一指令群中的指令2(cmd2)、第二指令群中的指令2(cmd2’)、第三指令群中的指令2”(cmd2”)。二个时脉信号(CLK1、CLK2)的上升沿位于指令信号CMD的安全相位区间(Eye_cmd)、区块控制信号BANK[2:0]的安全相位区间Eye_bank、地址信号A[0:15]的安全相位区间Eye_addr之内。应注意到,二个DDR存储器模块410、420在t1、t3、t5时间点所接收的指令可以确实得到地址信号A[0:15]以及区块控制信号BANK[2:0]的正确数据,并可以正确地据以执行指令。Furthermore, at the time points t1, t3, and t5, the command 2 (cmd2) in the first command group, the command 2 (cmd2') in the second command group, and the command 2 in the third command group" (cmd2"). The rising edges of the two clock signals (CLK1, CLK2) are located in the safe phase interval (Eye_cmd) of the command signal CMD, the safe phase interval Eye_bank of the block control signal BANK[2:0], and the safe phase interval of the address signal A[0:15]. Within the safe phase interval Eye_addr. It should be noted that the instructions received by the two DDR memory modules 410, 420 at time points t1, t3, and t5 can indeed obtain the correct data of the address signal A[0:15] and the block control signal BANK[2:0]. And can execute instructions correctly accordingly.
由以上说明可知,本实施例限定存储器控制器能输出多个指令群,而每个指令群中皆有连续二个指令。第一个指令仅可为NOP指令。如此,可将其地址信号A[0:15]以及区块控制信号BANK[2:0]的信号周期增加为2T,使得其安全相位区间Eye_addr与Eye_bank变大,更容易拴锁控制信号的数据。It can be seen from the above description that the present embodiment limits the memory controller to output multiple command groups, and each command group has two consecutive commands. The first instruction can only be a NOP instruction. In this way, the signal period of the address signal A[0:15] and the block control signal BANK[2:0] can be increased to 2T, so that the safe phase interval Eye_addr and Eye_bank become larger, and it is easier to lock the data of the control signal .
应注意到,本发明并不限定于仅控制二个DDR存储器模块的数目。本发明也可以用于控制单一DDR存储器模块或者控制二个以上的DDR存储器模块。It should be noted that the present invention is not limited to only controlling the number of two DDR memory modules. The present invention can also be used to control a single DDR memory module or control more than two DDR memory modules.
再者,本发明并不限定于同时将地址信号A[0:15]以及区块控制信号BANK[2:0]的信号周期皆增加为2T。也可以根据实际上的需要,仅将地址信号A[0:15]的信号周期增加为2T,而将区块控制信号BANK[2:0]的信号周期维持在T,其相关信号波形如图4A所示。Furthermore, the present invention is not limited to increasing the signal periods of the address signal A[0:15] and the bank control signal BANK[2:0] to 2T at the same time. It is also possible to increase the signal period of the address signal A[0:15] to 2T according to actual needs, and maintain the signal period of the block control signal BANK[2:0] at T, and the related signal waveforms are shown in the figure 4A.
或者,仅将区块控制信号BANK[2:0]的信号周期增加为2T,而将地址信号A[0:15]的信号周期维持在T,其相关信号波形如图4B所示。Alternatively, only the signal period of the bank control signal BANK[2:0] is increased to 2T, while the signal period of the address signal A[0:15] is maintained at T, and the related signal waveforms are shown in FIG. 4B .
请参照图5,其所绘示为本发明存储器控制器的信号产生方法流程图。首先,产生信号周期为一个单位时间的第一时脉信号(步骤S502);产生信号周期为一个单位时间的指令信号,在指令信号中包括多个指令群,每一个指令群具有连续的第一个指令、第二个指令(步骤S504);产生信号周期为二个单位时间定址信号组(步骤S506)。定址信号组可为地址信号A[0:15]及/或区块控制信号BANK[2:0]定址信号组。Please refer to FIG. 5 , which is a flow chart of the method for generating signals of the memory controller of the present invention. First, generate a first clock signal with a signal period of one unit time (step S502); generate a command signal with a signal period of one unit time, the command signal includes a plurality of command groups, and each command group has a continuous first instruction, the second instruction (step S504); generate a signal cycle as two unit time addressing signal groups (step S506). The address signal group can be the address signal A[0:15] and/or the block control signal BANK[2:0] address signal group.
时脉产生单元406将第一时脉信号的第一个信号沿设定于指令信号的安全相位区间,以使得DDR存储器模块执行第一个指令(步骤S510);将第一时脉信号的第二个信号沿设定于指令信号、定址信号组的安全相位区间,以使得DDR存储器执行第二个指令(步骤S512)。The clock generation unit 406 sets the first signal edge of the first clock signal to the safe phase interval of the command signal, so that the DDR memory module executes the first command (step S510); The two signal edges are set in the safe phase interval of the command signal and the address signal group, so that the DDR memory executes the second command (step S512).
根据图5的方法,当步骤S510至步骤S512执行完之后,代表已经执行一指令群;而再次回到步骤S510时,即代表执行下一个指令群。其中,上述的一个单位时间为第一时脉周期,且指令群中的第一个指令仅为NOP指令。According to the method in FIG. 5 , when steps S510 to S512 are executed, it means that an instruction group has been executed; and when returning to step S510 again, it means that the next instruction group is executed. Wherein, the above unit time is the first clock cycle, and the first instruction in the instruction group is only the NOP instruction.
由以上说明可知,搭配实施例揭露的指令群并将地址信号A[0:15]或者区块控制信号BANK[2:0]的信号周期延长为二个单位时间以扩大其安全相位区间。如此,可使得存储器控制器正确地控制DDR存储器模块,并且解决已知存储器信号安全相位区间太小的问题,并可增强随着存储器存取时脉速度日益增加的系统稳定度与存取效能。It can be seen from the above description that the instruction group disclosed in the embodiment is combined and the signal period of the address signal A[0:15] or the block control signal BANK[2:0] is extended to two unit times to expand the safe phase interval. In this way, the memory controller can correctly control the DDR memory module, and solve the problem that the safe phase interval of the known memory signal is too small, and can enhance the system stability and access performance as the memory access clock speed increases day by day.
综上所述,虽然本发明已以较佳实施例揭示如上,然其并非用以限定本发明。本发明所属技术领域中具有通常知识者,在不脱离本发明的精神和范围内,当可作各种的更动与润饰。因此,本发明的保护范围当以权利要求书界定为准。To sum up, although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the claims.
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