CN104270152A - PVT-insensitive common-mode charge control device for charge-coupled pipeline ADC - Google Patents

Abstract

The invention relates to a circuit device used for controlling common mode charges in a charge coupling assembly line analog-digital converter. The circuit device comprises two output common mode adjusting charge transmission circuits (BBD), a common mode detection adjusting circuit and a voltage turning-off copy circuit. According to the aim of the circuit device, a common mode charge problem caused by an existing charge transmission technology is restrained, and the purpose of adjusting common mode charges precisely is achieved through two adjusting modes. According to the first adjusting mode, the large-signal characteristic of a cascade amplifier is changed by adjusting voltage of a substrate of an input tube of the cascade amplifier, and therefore on-off point voltage of a whole BBD is changed. According to the second mode, the large-signal characteristic of the cascade amplifier is changed by changing grid voltage of a parallel-connection tube M4, and the on-off point voltage of the whole BBD can be changed. The two modes are respectively used for dealing with errors of the two common mode charges.

Description

PVT-insensitive common-mode charge control device for charge-coupled pipeline ADC

technical field

The invention belongs to the technical field of integrated circuits, and in particular relates to a circuit device that can be used to control common-mode charges inside a charge-coupled pipeline analog-to-digital converter.

technical background

In the charge-coupled pipeline analog-to-digital converter, the charge packets sampled by the charge-coupled sample-and-hold circuit will be sent to subsequent stages of charge-coupled sub-stage pipeline circuits for step-by-step comparison and quantization processing. For a charge-coupled pipeline ADC implemented with a fully differential structure, signal processing is carried out synchronously on two signal states, the positive and negative signal processing paths are complementary and symmetrical with the common mode signal as the center, and finally processed by two signal channels The difference between the results is used as the final processing result. The input voltage signal is first converted into two charge packets in a fully differential form, which are respectively used for quantization processing by subsequent fully differential charge-coupled sub-stage pipeline circuits, and finally quantized output results are obtained.

In the above-mentioned charge-coupled pipeline analog-to-digital converter, when the charge-coupled sub-stage pipeline circuits of subsequent stages process the input charge packets, the size of the common-mode charge packets generally remains equal. Under the existing CMOS process conditions, due to the randomness of process fluctuations and the existence of various other irrational factors, the common-mode charges of the implemented charge-coupled sub-stage pipeline circuits at all levels cannot be strictly equal, but there is a certain common-mode charge. model error.

Among the many factors affecting the common-mode charge, the influence of the charge transfer circuit block between sub-circuits is crucial. For the realization of high-efficiency charge transfer technology, there is a typical existing technical implementation method patent: US2007/0279507A1 enhanced charge transfer circuit, and its typical circuit structure is shown in Figure 1. The gate V _G of the charge transfer MOSFET S is connected to the output terminal of the operational amplifier 1 composed of MOS transistors M1 , M2 and M3 . Before the operational charge is transmitted at the output terminal of the operational amplifier 1, S is in an off state, and the charge to be transmitted is stored on _C1 . Figure 2 is a schematic diagram of the working voltage waveform of the circuit. At t0, Ck1 changes negatively and Ck1n changes positively, causing Ni voltage V _Ni to suddenly change to a low potential and No voltage V _No to change suddenly to a high potential. Operational amplifier 1 will respond to this change and drive MOSFET The V _G voltage of the S gate is high, so that S starts to conduct; due to the potential difference, the charge stored on Ni will be transferred to No in the form of electrons, causing V _Ni to rise and V _No to fall, and the operational amplifier 1 will also It will respond to this change and drive the MOSFET S gate V _G voltage to gradually decrease; at time t1, when V _Ni rises to the voltage V _r , and the V _G voltage gradually decreases to the cut-off voltage V _th , S turns off again, and the charge transfer process ends , where _Vr is determined by the quiescent operating point of the cascode op amp.

The amount of charge _QT transmitted by the circuit shown in Figure 1 in one clock cycle can be expressed by the amount of charge change on _C1 .

Q _T ＝C ₁ *(ΔV _Ck1 -ΔV _Ni )

(1)

＝C ₁ *((V _Ck1 (t0)-V _Ck1 (t1))-(V _Ni (t0)-V _Ni (t1))

In the above formula, V _Ck1 (t0), V _Ck1 (t1), and V _Ni (t0) are fixed quantities directly controlled by the reference voltage; V _Ni (t0) is determined by the charge of the signal to be transmitted, and V _Ni (t1 ) approaches the voltage V _r at the end of the charge transfer. During the entire charge transfer process, the speed and accuracy of V _Ni approaching V _r directly determine the charge transfer speed and accuracy of the BCT circuit. If V _r is accurate and stable, the amount of charge transferred during the transfer is a linear function of the charge of the signal to be transferred. But since V _r is determined by the quiescent operating point of the cascode operational amplifier, V _r is very sensitive to PVT (process fluctuation, supply voltage noise, temperature variation) fluctuations. Assuming that ΔV changes due to PVT fluctuation V _r , the corresponding V _Ni (t1) will produce a voltage change of ΔV. From formula (1), we can see that ΔV will directly generate an error charge amount of ΔQ=ΔV*C ₁ on Q _T.

When this circuit is used fully differentially, the amount of common-mode charge transferred can be obtained as:

Q _TCM ＝(C ₁ *(ΔV _Ck1 -ΔV _NiP )+C ₁ *(ΔV _Ck1 -ΔV _NiN ))/2

(2)

＝C ₁ *(V _Ck1 (t0)-V _Ck1 (t1))-C ₁ *((2V _Ni (t0)-V _NiP (t1)-V _NiN (t1))/2

It can be seen that the error caused by V _Ni (t1) cannot be eliminated during the common-mode charge transfer, and the error is directly transmitted to the subsequent circuit, so the error must be effectively controlled.

Contents of the invention

The object of the present invention is to address the shortcomings of the prior art, to provide a PVT-insensitive common-mode charge control device that can be linearly adjusted by an external signal, and to suppress the common-mode charge problem caused by the existing charge transmission technology.

According to the technical solution provided by the present invention, the PVT-insensitive common-mode charge control device used for charge-coupled pipeline analog-to-digital converters includes: two output common-mode adjustable charge transmission circuits, a common-mode detection and adjustment circuit, a switch Off-voltage replication circuit; the OUT output signals of the first output common-mode adjustable charge transmission circuit and the second output common-mode adjustable charge transmission circuit are both input to the common-mode detection adjustment circuit, and the common-mode detection adjustment circuit is based on the first output common mode. The OUT signal of the mode adjustable charge transfer circuit, the OUT signal of the second output common mode adjustable charge transfer circuit, the control clock and the reference voltage V _REF are processed and the output feedback signal Vfb is connected to the two outputs respectively The P terminal of the common-mode adjustable charge transmission circuit adjusts the output common mode of the OUT terminal, and the shutdown voltage replica circuit generates the substrate control voltage Vbody according to the reference voltage V _R,1 and connects the B terminals of the two output common-mode adjustable charge transmission circuits; The first output common-mode adjustable charge transfer circuit and the second output common-mode adjustable charge transfer circuit respectively generate output OUT signals according to the signals of the IN terminal, the B terminal and the P terminal, and the fully differential OUT signal is detected by the common-mode detection adjustment circuit At the same time, it is also directly output to the next-level common-mode charge control circuit;

The output common-mode adjustable charge transmission circuit includes: the drains of the NMOS transistor M4 and the NMOS transistor M1 are connected to the source of the NMOS transistor M2 at the same time, the sources of the NMOS transistors M4 and M1 are connected to the ground at the same time, and the NMOS transistor M1 The gates of M1 and M4 are respectively connected to the IN terminal and the P terminal, and the substrate potential of the NMOS transistor M1 is controlled by the B terminal; the drain of the NMOS transistor M2 is connected to the gate of the charge transfer NMOS transistor Ms and the drain of the PMOS transistor M3 , and also connected to the drain of the NMOS transistor Men, the gate of the NMOS transistor M2 is connected to the bias voltage Vbn; the drain of the PMOS transistor M3 is connected to the source of the NMOS transistor M2, and the gate of the PMOS transistor M3 is connected to the bias voltage Vbp, The drain of the PMOS transistor M3 is connected to the drain of the PMOS transistor Mep; the source of the PMOS transistor Mep is connected to the power supply voltage, the gate of the PMOS transistor Mep is connected to the working clock Ck0; the source of the NMOS transistor Men is grounded, and the gate of the NMOS transistor Men is connected to The working clock Ck0; the source, drain and gate terminals of the charge transfer NMOS transistor Ms are respectively connected to the IN terminal, the OUT terminal and the drain of the NMOS transistor M2.

The common-mode detection and adjustment circuit adjusts the output common-mode charge of the first and second output common-mode adjustable charge transfer circuits by controlling the MOS transistor M4 inside the first and second output common-mode adjustable charge transfer circuits respectively. The P-side implementation.

The shutdown voltage replica circuit adjusts the output common-mode charge of the first and second output common-mode adjustable charge transfer circuits by separately controlling the MOS transistor M1 inside the first and second output common-mode adjustable charge transfer circuits The substrate voltage at terminal B is achieved.

The common-mode detection and adjustment circuit includes a common-mode error amplifier module and an error signal processing module, and the common-mode error amplifier module compares the differential output charge signal and the Vref signal under the control of the control clock, and outputs the result to the error signal Processing module; the error signal processing module processes the common-mode error signal to obtain a Vfb output signal, which is used to control and output the P terminal of the common-mode adjustable charge transmission circuit. The error signal processing module inside the common mode detection and adjustment circuit adopts a programmable transconductance amplifier circuit.

The invention has the advantages that the purpose of accurately adjusting the common-mode charge is achieved through two adjustment methods. The first adjustment method changes the large-signal characteristics of the cascode amplifier by adjusting the substrate voltage of the input transistor of the cascode amplifier, thereby changing the turn-off point voltage of the entire BBD. The second method changes the large-signal characteristics of the cascode amplifier by changing the gate voltage of the parallel transistor M4, thereby changing the turn-off point voltage of the entire BBD. These two methods are respectively used to deal with the aforementioned two kinds of common-mode charge errors.

Description of drawings

FIG. 1 is a schematic diagram of a charge transmission circuit in the prior art.

FIG. 2 is a waveform diagram of charge transmission in the prior art.

FIG. 3 is a structural diagram of a PVT-insensitive common-mode charge control device according to the present invention.

FIG. 4 is a circuit diagram of an output common-mode adjustable charge transfer circuit (BBD for short) of the present invention.

FIG. 5 is a schematic structural diagram of a shutdown voltage replication circuit.

FIG. 6 is a specific implementation of the low power consumption error amplifier circuit in FIG. 5 .

FIG. 7 is a specific structural block diagram of the common-mode detection and adjustment circuit.

FIG. 8 is a specific implementation of the common-mode error amplifier module in FIG. 7 .

FIG. 9 is a specific implementation of the programmable error signal processing module in FIG. 7 .

Detailed ways

The present invention will be described in further detail below in conjunction with the accompanying drawings and examples.

Fig. 3 shows the structural block diagram of the PVT insensitive common-mode charge control circuit provided by the present invention, which includes two output common-mode adjustable charge transmission circuits 31 and 32, a scale detection adjustment circuit 33, and a shutdown voltage replication circuit 34, 35 in the figure is the relevant common-mode charge control circuit of the next-stage pipeline circuit. The connection relationship of the circuit shown in Fig. 3 is as follows: the output signals at the OUT terminals of the output common-mode adjustable charge transfer circuits 31 and 32 are all detected by the common-mode detection and adjustment circuit 33, and are compared and processed with the Vref voltage under the control of the control clock , and the output feedback signal Vfb is connected to the P control terminals of the circuits 31 and 32 to adjust the output common mode of the OUT terminal; the shutdown voltage replica circuit 34 generates the substrate control voltage Vbody according to the voltage Vr,1 to control the B terminals of the circuits 31 and 32; The output common-mode adjustable charge transfer circuits 31 and 32 generate the output signal OUT according to the signals provided by the IN, B and P terminals. While the fully differential OUT signal is detected by the common-mode detection and adjustment circuit 33, it is also directly output to the next stage ( N+1th stage) common mode charge control circuit.

For a charge-coupled pipeline ADC, in addition to the common-mode charge affected by the BBD turn-off point voltage due to PVT changes, the change in the common-mode level of the input signal of the entire ADC will also cause relatively large common-mode charges in this stage and subsequent stages. A large error will affect the normal operation of the subsequent circuit. In order to cope with these two factors, the BBD circuit of the present invention provides two adjustment means to control the error of the common-mode charge output by the sub-stage circuit. This modified BBD circuit is as buggy! Reference source not found. shown. The first adjustment method changes the large-signal characteristics of the cascode amplifier by adjusting the substrate voltage of the input transistor of the cascode amplifier, thereby changing the turn-off point voltage of the entire BBD. The second method changes the large-signal characteristics of the cascode amplifier by changing the gate voltage of the parallel transistor M4, thereby changing the turn-off point voltage of the entire BBD. These two methods are respectively used to deal with the aforementioned two kinds of common-mode charge errors.

FIG. 4 is a circuit diagram of an output common-mode adjustable charge transfer circuit according to the present invention. It adds 3 MOS transistors and 3 control signals on the basis of the enhanced charge transfer circuit shown in Figure 1. The 3 MOS transistors are: a parallel drive transistor M4 (NMOS), clock reset Mep (PMOS) and Men Tube (NMOS); 3 control signals are B, P and working clock Ck0. The connection relationship of the circuit shown in Figure 4 is: the drains of NMOS transistors M4 and M1 are connected to the source of NMOS transistor M2 at the same time, the sources of M4 and M1 are connected to ground at the same time, and the gates of M1 and M4 are respectively connected to IN Terminal and P input terminal, and the substrate potential of M1 is controlled by B; the drain of M2 is connected to the gate of NMOS transistor Ms and the drain of PMOS transistor M3, and is also connected to the drain of Men and the gate of M2 Connect the bias voltage Vbn; the drain of M3 is connected to the source of M2, the gate of M3 is connected to the bias voltage Vbp, the drain of M3 is connected to the drain of Mep; the source of Mep is connected to the power supply voltage, and the gate is connected to the working clock Ck0 ; The source of Men is grounded, and the gate is connected to the working clock Ck0; the source, drain and gate terminals of the charge transfer NMOS transistor Ms are respectively connected to the drains of IN, OUT and M2.

FIG. 5 shows the structure of the shutdown voltage replica circuit 34 . The function realized by this circuit is to control the substrate voltage of the M1 tube in Figure 4, that is, the adjustment and control of the potential of point B in Figure 3. The shutdown voltage replica circuit 34 shown in FIG. 5 structurally includes two circuit function modules: an error amplifier 51 and a gate bootstrap BBD replica circuit 52 .

The size of each transistor of the common source amplifier in the gate bootstrap BBD replica circuit 52 and the corresponding transistor size of the main BBD circuit in FIG. 4 must be designed in strict accordance with a fixed ratio. Generally, in order to reduce the power consumption of the circuit, the circuit size in the circuit 52 and the corresponding MOS tube size in the main BBD circuit are designed to be proportionally reduced. The replica circuit does not contain capacitors and clock control logic, and a voltage source V _B and a bias current source I _B are respectively added at the drain end and the source end of the transmission switch. The current source I _B is very small, only a few μA, so it can well simulate the state of the main BBD circuit when the charge transfer is about to end, and the voltage at point S is very close to the turn-off point voltage V ₀ of the main BBD transfer switch. The error amplifier 51 in the feedback control circuit compares the voltage at point S with the designed reference voltage _VR to obtain an error signal, and generates a substrate control signal V _body after processing to adjust the substrate terminal of M1 in the replica circuit . The negative feedback can ensure that the voltage at point S is always approximately equal to _VR , thereby suppressing the influence of PVT changes on the voltage at point S of the replica circuit to a large extent. In order to achieve better flexibility, the size of VR can be changed by setting the N-bit register to control the size of the current source separated from the resistor string, so as to realize the control of the switch off point voltage in the replica circuit.

Figure 6 shows a specific implementation of the error amplifier 51 in Figure 5, the circuit adopts the integrator structure of the switched capacitor structure, the switch capacitor technology is used to achieve lower power consumption, and the traditional continuous time integrator circuit is adopted The above functions can also be realized. The error amplifier 51 connects the feedback control signal Vbody to the B terminal of the corresponding gate-bootstrap BBD replica circuit 52 to realize the control of the main BBD turn-off voltage. Since the feedback control signal simultaneously adjusts the substrate control terminals of the master circuit and the replica circuit, the turn-off point voltage of the master BBD will follow the voltage at point S of the replica circuit. The feedback loop stabilizes the voltage at point S, which makes the voltage at the cut-off point of the main BBD approximately equal to _VR all the time.

FIG. 7 is a block diagram showing a specific implementation structure of the common-mode detection and adjustment circuit 33 of the present invention, which includes a common-mode error amplifier module and an error signal processing module. The common-mode error amplifier module compares the differential output charge signal and the Vref signal under the control of the control clock, and outputs the result to the error signal processing module; the error signal processing module processes the common-mode error signal to obtain the Vfb output signal, which is used for Control the P terminal of the BBD circuit. The common-mode detection and adjustment circuit shown in Figure 7 detects the deviation between the output common-mode level of the charge-coupled sub-stage pipeline and the reference signal, and generates a control signal according to the deviation to change the gate voltage P of the parallel transistor in the BBD , so as to fine-tune the shutdown voltage of the BBD to offset the common-mode charge error caused by the common-mode level fluctuation of the input signal.

FIG. 8 shows a specific implementation of the common-mode error amplifier module in FIG. 7 . Its structure is a basic switched capacitor sample-and-hold device, in which the single-tube switch is a PMOS switch, and the upper end of the complementary switch is an NMOS tube and the lower end is a PMOS tube. Its working process can be divided into two phases: sampling phase and establishment phase. In the sampling phase, cp1 becomes low, and when cp is high, the threshold voltages Vp and Vn and the common mode bias Vset of the comparator are connected to the bottom plate and top plate of the capacitor for sampling; in the establishment phase, the bottom plate of the capacitor is connected to the input Signals Vip and Vin, so that the difference between the input signal and the threshold signal appears at the two input terminals of the voltage comparator, and then the voltage comparator starts to amplify. The establishment process of the comparison signal is as follows: the charges on the two capacitors in the sampling phase are C (Vset-Vip) and C (Vset-Vin) respectively; in the establishment phase, due to the conservation of charge, the voltages at the two input terminals of the comparator will be Vset respectively -Vip+Vp and Vset-Vin+Vn are equivalent to comparing the input voltage with the comparison threshold voltage, namely:

(Vset－Vip+Vp)－(Vset－Vin+Vn)＝(Vp-Vn)－(Vip－Vin) (3)

FIG. 9 shows a specific implementation of the error signal processing module in FIG. 7 . To increase design flexibility, a programmable transconductance amplifier circuit is used. The specific connection relationship of the circuit is: PMOS transistors M3 and M4 constitute a simple PMOS current mirror circuit, the gate of PMOS transistor M3 is connected to the drain end of M3 transistor, NMOS transistors M1 and M2 form an input differential pair, and the drain of M1 is connected to M3 The drain of M2 is connected to the drain of M4, the sources of NMOS tubes M1 and M2 are connected to the upper ends of resistors R1 and R2 respectively, and the lower ends of resistors R1 and R2 are connected together and connected to the drain of M5 tube , the source of M5 is connected to the drain of M6, the source of M6 is connected to the ground, NMOS transistors M5 and M8 constitute a simple NMOS current mirror circuit, NMOS transistors M6 and M7 constitute a simple NMOS current mirror circuit, NMOS transistors M7 and The source of M8 is respectively connected to the input bias current sources Ib2 and Ib1, and the drain of the NMOS transistor M6 is connected to the current input DAC controlled by the external adjustment code.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection of the present invention. within range.

Claims (5)

1. for the insensitive common mode charge control device of PVT of charge coupling assembly line analog to digital converter, it is characterized in that, comprise two output common mode tunable charge transmission circuits, a common mode detects Circuit tuning (33), a shutoff voltage duplicate circuit (34); The OUT end output signal of the first output common mode tunable charge transmission circuit (31) and the second output common mode tunable charge transmission circuit (32) is all input to common mode and detects Circuit tuning (33), common mode detect Circuit tuning (33) according to the OUT signal of the OUT signal of the first output common mode tunable charge transmission circuit (31), the second output common mode tunable charge transmission circuit, control clock and reference voltage V _rEFcarry out processing and output feedback signal Vfb, feedback signal Vfb are connected respectively to two output common mode tunable charge transmission circuits P end regulate OUT end output common mode, shutoff voltage duplicate circuit (34) is according to reference voltage V _{r, 1}produce the B end that substrate control voltage Vbody connects two output common mode tunable charge transmission circuits; First output common mode tunable charge transmission circuit (31) and the second output common mode tunable charge transmission circuit (32) produce separately according to the signal of IN end, B end and P end and export OUT signal, the OUT signal of fully differential is detected while Circuit tuning (33) detects by common mode, also directly outputs to next stage common mode charge control circuit;

Described output common mode tunable charge transmission circuit comprises: the drain electrode of NMOS tube M4 and NMOS tube M1 is connected to the source electrode of NMOS tube M2 simultaneously, the source electrode of NMOS tube M4 and M1 is connected to ground simultaneously, NMOS tube M1 and the grid of M4 are connected IN end and P end respectively, and the substrate electric potential of NMOS tube M1 holds control by B; The drain electrode of NMOS tube M2 is connected to the grid of transferring charge NMOS tube Ms and the drain electrode of PMOS M3, is also connected to the drain electrode of NMOS tube Men simultaneously, and the grid of NMOS tube M2 meets bias voltage Vbn; The drain electrode of PMOS M3 is connected to NMOS tube M2 source electrode, and the grid of PMOS M3 meets bias voltage Vbp, and the drain electrode of PMOS M3 connects the drain electrode of PMOS Mep; The source electrode of PMOS Mep connects supply voltage, and the grid of PMOS Mep meets work clock Ck0; The source ground of NMOS tube Men, the grid of NMOS tube Men meets work clock Ck0; Transferring charge NMOS tube Ms source, leakage and grid end connect the drain electrode of IN end, OUT end and NMOS tube M2 respectively.

2. according to claim 1 for the insensitive common mode charge control device of PVT of charge coupling assembly line analog to digital converter, it is characterized in that, described common mode detects the P end realization that Circuit tuning (33) adjustment to the output common mode electric charge of first, second output common mode tunable charge transmission circuit is the metal-oxide-semiconductor M4 by controlling first, second output common mode tunable charge transmission circuit inside respectively.

3. according to claim 1 for the insensitive common mode charge control device of PVT of charge coupling assembly line analog to digital converter, it is characterized in that, the adjustment of described shutoff voltage duplicate circuit (34) to the output common mode electric charge of first, second output common mode tunable charge transmission circuit is the underlayer voltage B end realization of the metal-oxide-semiconductor M1 by controlling first, second output common mode tunable charge transmission circuit inside respectively.

4. according to claim 1 for the insensitive common mode charge control device of PVT of charge coupling assembly line analog to digital converter, it is characterized in that, described common mode detects Circuit tuning (33) and comprises a common-mode error amplifier module and an error signal processing module, common-mode error amplifier module compares difference output charge signal and Vref signal under the control controlling clock, and result is outputted to error signal processing module; Error signal processing module is carried out process to common-mode error signal and is obtained Vfb output signal, for controlling the P end of output common mode tunable charge transmission circuit.

5. according to claim 4 for the insensitive common mode charge control device of PVT of charge coupling assembly line analog to digital converter, it is characterized in that, described common mode detects the inner error signal processing module of Circuit tuning (33) and adopts programmable trans-conductance amplifier circuit.