CN104270138B - Input/output buffer of multiple voltage domains - Google Patents

Abstract

This application discloses a multi-voltage domain input/output buffer, including a VCC voltage detection circuit, a charge pump circuit, a charge pump control circuit, a pre-driver stage, and a low-voltage application driver with a low withstand voltage MOS as the basic device. stage, a high-voltage application driver stage with a high withstand voltage MOS as the basic device, and an overvoltage prevention circuit with a high withstand voltage MOS as the basic device; by detecting that the input/output buffer works in the high voltage domain When the low-voltage application driver stage is turned off and the high-voltage application driver stage is started, when it is detected that it is working in the low-voltage domain, the low-voltage application driver stage is turned on and the high-voltage application driver stage is turned off, so that the area of the input/output buffer is not increased Under the premise of improving the performance of the input/output buffer and the difficulty in designing the ESD protection circuit, the multi-voltage domain design of the input/output buffer is realized.

Description

Input/Output Buffers for Multiple Voltage Domains

technical field

The present invention relates to the field of electronic information technology, more specifically, to an input/output buffer of multiple voltage domains.

Background technique

When MOS is used as the basic device of the input/output buffer, if the operating voltage of the input/output buffer is inconsistent with the withstand voltage value of the MOS, the following problems will exist:

First, when a MOS with a low withstand voltage value is applied under high voltage conditions, overvoltage breakdown will occur. Although multiple MOSs with low withstand voltage values can be superimposed to enhance its withstand voltage capability, it will inevitably cause the area of the input/output buffer to be too large, and at the same time, the ESD (Electro -Static discharge, electrostatic discharge) design is too complicated;

Second, the higher the withstand voltage value of the MOS, the higher the threshold voltage, and when the MOS with the higher threshold voltage is applied under low voltage conditions, its overdrive voltage varies with PVT (process-voltage-temperature, process-voltage-temperature) The greater the range of variation produced by the change, it is easy to exceed the allowable range of variation and directly affect the performance of the input/output buffer.

Therefore, how to develop a multi-voltage domain input/output buffer that can avoid the above-mentioned negative effects has become an urgent problem to be solved by those skilled in the art.

Contents of the invention

In view of this, the present invention provides a multi-voltage domain input/output buffer, without increasing the area of the input/output buffer and the difficulty of ESD protection circuit design, and improving the performance of the input/output buffer Next, the multi-voltage domain design of the input/output buffer is realized.

A multi-voltage domain input/output buffer, including a VCC voltage detection circuit, a pre-driver stage, a low-voltage application driver stage with a first MOS and a second MOS, and a high-voltage application driver with a third MOS and a fourth MOS The stage has an overvoltage prevention circuit of the fifth MOS, the sixth MOS, the seventh MOS and the eighth MOS, a charge pump circuit, and a charge pump control circuit, wherein:

The VCC voltage detection circuit has a first power input pin connected to the system operating power supply, a second power input pin connected to the charge pump circuit, a power output pin connected to the pre-driver stage, and an input The input pin connected to the working power supply of the /output buffer, and the first output pin and the second output pin connected to the pre-driver stage are used to detect that the working power supply of the input/output buffer is In the high voltage domain, control the first output pin to output low level, the second output pin to output high level, and when it is detected that the working power supply of the input/output buffer is in the low voltage domain, control all The first output pin outputs a high level, and the second output pin outputs a low level;

The charge pump control circuit is respectively connected with the charge pump circuit, the VCC voltage detection circuit and the system working power supply, and is used to turn on the the charge pump circuit, and disconnect the connection between the VCC voltage detection circuit and the system operating power supply; otherwise, close the charge pump circuit, and restore the connection between the VCC voltage detection circuit and the system operation power supply, wherein The selection of the preset value is determined by the working power supply voltage of the input/output buffer;

The pre-driver stage has a first output pin, a second output pin, a third output pin and a fourth output pin, which are used to detect that the first output pin of the VCC voltage detection circuit is a high voltage level, when the second output pin is low level, control the third output pin of the pre-driver stage to output high level, the fourth output pin output low level, and detect the VCC voltage detection circuit When the first output pin is at low level and the second output pin is at high level, control the first output pin of the pre-driver stage to output high level, and the second output pin to output low level;

For the first MOS, its gate is connected to the first output pin of the pre-driver stage, and its drain is connected to the drain of the second MOS;

For the second MOS, its gate is connected to the second output pin of the pre-driver stage, and its source is grounded;

For the third MOS, its gate is connected to the third output pin of the pre-driver stage, its source is connected to the operating power supply of the input/output buffer, and its drain is connected to the drain of the fourth MOS ;

For the fourth MOS, its gate is connected to the fourth output pin of the pre-driver stage, and its source is grounded;

For the fifth MOS, its gate is connected to the first output pin of the VCC voltage detection circuit, its drain is connected to the working power supply of the input/output buffer, and its source is respectively connected to the source of the first MOS and the drain of the seventh MOS;

For the sixth MOS, its gate is connected to the first output pin of the VCC voltage detection circuit, its drain is connected to the drain of the third MOS, and its source is connected to the drain of the second MOS;

For the seventh MOS, its gate is connected to the second output pin of the VCC voltage detection circuit, and its source is grounded;

For the eighth MOS, its gate is connected to the second output pin of the VCC voltage detection circuit, its drain is connected to the drain of the second MOS, and its source is grounded;

Wherein, the first MOS is a PMOS with a low withstand voltage, the second MOS is an NMOS with a low withstand voltage, the third MOS is a PMOS with a high withstand voltage, and the fourth MOS and the fifth MOS , the sixth MOS, the seventh MOS and the eighth MOS are all NMOSs with a high withstand voltage.

Wherein, the first MOS is a PMOS with a withstand voltage equal to 1.2V, the second MOS is an NMOS with a withstand voltage equal to 1.2V, the third MOS is a PMOS with a withstand voltage equal to 3.3V, and the second MOS is a PMOS with a withstand voltage equal to 3.3V. The fourth MOS, the fifth MOS, the sixth MOS, the seventh MOS and the eighth MOS are all NMOSs with a withstand voltage equal to 3.3V.

Wherein, the preset value is equal to 2.7V.

Wherein, the first MOS is a PMOS with a withstand voltage equal to 1.2V, the second MOS is an NMOS with a withstand voltage equal to 1.2V, the third MOS is a PMOS with a withstand voltage equal to 2.5V, and the second MOS is a PMOS with a withstand voltage equal to 2.5V. The fourth MOS, the fifth MOS, the sixth MOS, the seventh MOS and the eighth MOS are all NMOSs with a withstand voltage equal to 2.5V.

Wherein, the first MOS is a PMOS with a withstand voltage equal to 1.2V, the second MOS is an NMOS with a withstand voltage equal to 1.2V, the third MOS is a PMOS with a withstand voltage equal to 1.8V, and the second MOS is a PMOS with a withstand voltage equal to 1.2V. The fourth MOS, the fifth MOS, the sixth MOS, the seventh MOS and the eighth MOS are all NMOSs with a withstand voltage equal to 1.8V.

Wherein, the first MOS is a PMOS with a withstand voltage equal to 1.8V, the second MOS is an NMOS with a withstand voltage equal to 1.8V, the third MOS is a PMOS with a withstand voltage equal to 3.3V, and the second MOS is a PMOS with a withstand voltage equal to 3.3V. The fourth MOS, the fifth MOS, the sixth MOS, the seventh MOS and the eighth MOS are all NMOSs with a withstand voltage equal to 3.3V.

Wherein, the first MOS is a PMOS with a withstand voltage equal to 1.8V, the second MOS is an NMOS with a withstand voltage equal to 1.8V, the third MOS is a PMOS with a withstand voltage equal to 2.5V, and the second MOS is a PMOS with a withstand voltage equal to 2.5V. The fourth MOS, the fifth MOS, the sixth MOS, the seventh MOS and the eighth MOS are all NMOSs with a withstand voltage equal to 2.5V.

Wherein, the first MOS is a PMOS with a withstand voltage equal to 2.5V, the second MOS is an NMOS with a withstand voltage equal to 2.5V, the third MOS is a PMOS with a withstand voltage equal to 3.3V, and the second MOS is a PMOS with a withstand voltage equal to 3.3V. The fourth MOS, the fifth MOS, the sixth MOS, the seventh MOS and the eighth MOS are all NMOSs with a withstand voltage equal to 3.3V.

It can be seen from the above-mentioned technical scheme that the present invention closes the low-voltage application driver stage with a MOS of a low withstand voltage value as a basic device when detecting that the input/output buffer is operating in a high voltage domain, and starts the drive stage with a high withstand voltage value. The MOS is used as the high-voltage application driver stage of the basic device; when it is detected that it is working in the low-voltage domain, the low-voltage application driver stage is started and the high-voltage application driver stage is turned off; thereby reducing the MOS with a high withstand voltage value in the Under the influence of PVT changes in low-voltage applications, the performance of the input/output buffer is improved; at the same time, it avoids overvoltage breakdown of MOS with low withstand voltage values in high-voltage applications, and because there is no need to use multiple low withstand voltage values The MOS is superimposed and resisted, so the area of the input/output buffer and the difficulty of ESD protection circuit design will not be increased;

In addition, when the output voltage of the working power supply of the system is unstable, the present invention introduces a charge pump circuit to provide a stable power supply for the VCC voltage detection circuit, thereby ensuring the performance of the input/output buffer.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 is a schematic structural diagram of an input/output buffer with multiple voltage domains disclosed by an embodiment of the present invention.

detailed description

For reference and clarity, technical terms, abbreviations or abbreviations used hereinafter are summarized as follows:

MOS: Metal Oxide Semiconductor FET, Metal Oxide Semiconductor Field Effect Transistor;

PMOS: P-Metal Oxide Semiconductor FET, P-channel Metal Oxide Semiconductor Field Effect Transistor;

NMOS: N-Metal Oxide Semiconductor FET, N-channel Metal Oxide Semiconductor Field Effect Transistor;

ESD: Electro-Static discharge, electrostatic discharge;

SSN: Simultaneous Switch Noise, synchronous switching noise.

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

Referring to FIG. 1 , an embodiment of the present invention discloses a multi-voltage domain input/output buffer, so as to improve the performance of the input/output buffer without increasing the area of the input/output buffer and the difficulty of ESD protection circuit design. Under the premise of performance, realize the multi-voltage domain design of the input/output buffer, which includes:

A low-voltage application driver stage 10 having a first MOS and a second MOS, a high-voltage application driver stage 20 having a third MOS and a fourth MOS, and an anti-corrosion stage 20 having a fifth MOS, a sixth MOS, a seventh MOS, and an eighth MOS Overvoltage circuit 30 , VCC voltage detection circuit 40 , pre-driver stage 50 , charge pump circuit 60 , and charge pump control circuit 70 . in:

The VCC voltage detection circuit 40 has a first power input pin connected to the system operating power VDD (the system operating power VDD is the power supply voltage of the chip to which the input/output buffer belongs), and a second power input connected to the charge pump circuit 60. Pin, the power output pin connected to the pre-driver stage 50, the input pin connected to the working power supply VCC of the input/output buffer, the first output pin and the second output pin connected to the pre-driver stage 50;

The charge pump control circuit 70 is connected with the charge pump circuit 60, the VCC voltage detection circuit 40 and the system operating power supply VDD respectively, and is used to detect that the output voltage of the system operating power supply VDD is lower than a preset value (the selection of the preset value is determined by VCC The working power supply voltage VCC of the input/output buffer detected by the voltage detection circuit 40 is determined, for example, when the working power supply voltage VCC is equal to 3.3V, and the preset value is determined to be 2.7V), the charge pump circuit 60 is turned on and off. Open the connection between the VCC voltage detection circuit 40 and the system operating power supply VDD. At this time, the power required by the VCC voltage detection circuit 40 and the pre-driver stage 50 is provided by the charge pump circuit 60; otherwise, close the charge pump circuit 60 and restore the VCC voltage detection. The connection between the circuit 40 and the system operating power supply VDD, at this time, the power required by the VCC voltage detection circuit 40 and the pre-driver stage 50 is provided by the system operating power supply VDD;

The pre-driver stage 20 has a first output pin, a second output pin, a third output pin and a fourth output pin.

In order to facilitate the description of the circuit topology of the input/output buffer of the multi-voltage domain, the first MOS, the second MOS, the third MOS, the fourth MOS, the fifth MOS, the sixth MOS, the seventh MOS and the first MOS are defined below The eight MOSs are respectively M1, M2, M3, M4, M5, M6, M7 and M8, the first output pin and the second output pin of the VCC voltage detection circuit 40 are defined as VLV_EN and VLV_ENB respectively, and the pre-driver stage 50 is defined The first output pin, the second output pin, the third output pin and the fourth output pin are respectively VLpre_driver_P, VLpre_driver_N, VHpre_driver_P and VHpre_driver_N. Then the circuit topology of the input/output buffer of the multi-voltage domain is specifically:

1) In low voltage application driver stage 10

For M1, its gate is connected to the VLpre_driver_P pin of the pre-driver stage 50, and its drain is connected to the drain of M2;

For M2, its gate is connected to the VLpre_driver_N pin of the pre-driver stage 50, and its source is grounded to VSS;

2) In high voltage application driver stage 20

For M3, its gate is connected to the VHpre_driver_P pin of the pre-driver stage 50, its source is connected to the working power supply VCC of the input/output buffer, and its drain is connected to the drain of M4;

For M4, its gate is connected to the VHpre_driver_N pin of the pre-driver stage 50, and its source is grounded to VSS;

3) In the anti-overvoltage circuit 30

For M5, its gate is connected to the VLV_EN pin of the VCC voltage detection circuit 40, its drain is connected to the working power supply VCC of the input/output buffer, and its source is respectively connected to the source of M1 and the drain of M7;

For M6, its gate is connected to the VLV_EN pin of the VCC voltage detection circuit 40, its drain is connected to the drain of M3, and its source is connected to the drain of M1;

For M7, its gate is connected to the VLV_ENB pin of the VCC voltage detection circuit 40, and its source is grounded to VSS;

For M8, its gate is connected to the VLV_ENB pin of the VCC voltage detection circuit 40, its drain is connected to the drain of M2, and its source is grounded to VSS;

4) M1 is PMOS with low withstand voltage, M2 is NMOS with low withstand voltage, M3 is PMOS with high withstand voltage, M4, M5, M6, M7 and M8 are all NMOS with high withstand voltage;

5) The information input port IN of the input/output buffer of the multi-voltage domain is the information input port IN of the pre-driver stage 50; the information output port PAD of the input/output buffer of the multi-voltage domain is the drain of M3 , that is, the drain of M4, that is, the drain of M6.

The working principle of the multi-voltage-domain input/output buffer finally constructed is as follows:

The VCC voltage detection circuit 40 uses the operating voltage VCC of the input/output buffer as the input of the detection information, and when it detects that the input/output buffer is operating in a high voltage domain, controls the VLV_EN pin to output a low-level logic "0", Control the VLV_ENB pin to output a high-level logic "1"; and when it is detected that the input/output buffer is operating in a low-voltage domain, control the VLV_EN pin to output a high-level logic "1", and control the VLV_ENB pin to output a low-level logic "0".

The pre-driver stage 50 receives the level signal transmitted by the VLV_EN pin and the VLV_ENB pin, and controls the VLpre_driver_P pin to output a high level when it detects that the VLV_EN pin is a low-level logic "0" and the VLV_ENB pin is a high-level logic "1". Logic "1", control the VLpre_driver_N pin to output a low level logic "0"; and when it is detected that the VLV_EN pin is a high level logic "1" and the VLV_ENB pin is a low level logic "0", control the VHpre_driver_P pin to output a high level Level logic "1", control VHpre_driver_N pin output low level logic "0".

Then, the input/output buffer works in the high-voltage domain, that is, the VLV_EN pin is a low-level logic "0", the VLV_ENB pin is a high-level logic "1", the VLpre_driver_P pin is a high-level logic "1", and the VLpre_driver_N pin is a high-level logic "1". In the case of a low logic "0", there is:

①M1 and M2 are turned off, that is, the low-voltage application driver stage 10 is turned off;

② The pre-driver stage 50 drives the high-voltage application driver stage 20 to turn on; specifically, the pre-driver stage 50 uses the information input port IN to receive binary information, and uses the VHpre_driver_P pin and VHpre_driver_N pin to send drive signals to M3 and M4 to drive the high-voltage application drive The information output port PAD of stage 20 outputs the required pulse signal;

③M5 is turned off, which is used to isolate the connection between M1 and the power supply voltage VCC of the input/output buffer to prevent M1 from overvoltage;

M6 is turned off, which is used to isolate the connection between M2 and the information output port PAD to prevent overvoltage of M2;

④M7 is turned on, which is used to pull down the NET01 terminal (that is, the source of M5, that is, the source of M1) to prevent M5 from leaking and charge the NET01 terminal to a high voltage;

M8 is turned on, and is used to pull down the NET02 terminal (that is, the drain of M1, that is, the drain of M2) to prevent the leakage of M6 from charging the NET02 terminal to a high voltage.

The input/output buffer works in the low voltage domain, that is, the VLV_EN pin is low-level logic "1", the VLV_ENB pin is high-level logic "0", the VHpre_driver_P pin is high-level logic "1", and the VHpre_driver_N pin is low In the case of level logic "0", there are:

①M3 and M4 are turned off, that is, the driving stage 20 of the high voltage application is turned off;

②M5 and M6 are turned on, and M7 and M8 are turned off;

③ The pre-driver stage 50 drives the low-voltage application driver stage 10 to turn on; specifically, the pre-driver stage 50 uses the information input port IN to receive binary information, and uses the VLpre_driver_P pin and VLpre_driver_N pin to send drive signals to M1 and M2 to drive the low-voltage application drive The information output port PAD of stage 10 outputs the required pulse signal.

It can be seen that in this embodiment, when it is detected that the input/output buffer is working in the high-voltage domain, the low-voltage application driver stage with low withstand voltage MOS as the basic device is turned off, and the high withstand voltage MOS is used as the basic device. The high-voltage application driver stage of the device; when it is detected that the input/output buffer is working in the low-voltage domain, the low-voltage application driver stage is started and the high-voltage application driver stage is turned off; thereby reducing the MOS with a high withstand voltage value in the Under the influence of PVT changes in low-voltage applications, the performance of the input/output buffer is improved; at the same time, it avoids the overvoltage breakdown of MOS with low withstand voltage values in high-voltage applications, and because there is no need to use multiple low withstand voltage values The MOS is superimposed and resisted, so the area of the input/output buffer and the difficulty of ESD protection circuit design will not be increased (because the existing input/output buffer directly multiplexes the driver stage into the ESD protection circuit as the ESD protection circuit Partly, if the structure of the driver stage is complicated, it will inevitably increase the difficulty of designing the ESD protection circuit. However, in this embodiment, since multiple MOSs with low withstand voltage values are not required to perform superimposed pressure resistance, the structure of the driver stage 20 for high-voltage applications is simple. Its multiplexing into the ESD protection circuit will not increase the design difficulty of the ESD protection circuit).

In addition, considering that in an ideal state, the system working power supply VDD is equal to the working power supply VCC of the input/output buffer; however, due to the MOS impedance in the overvoltage prevention circuit 30 to the driving voltage (that is, the input voltage of the M5-M8 grid) There are certain requirements, and when the operating voltage of the system is too low, the performance of the input/output buffer will be degraded. Therefore, in order to ensure that the input/output buffer can work normally when the system operating power supply VDD is unstable, the present embodiment designs a charge pump circuit 60 and a charge pump control circuit 70; when the output voltage of the system operating power supply VDD is not lower than When the preset value is enabled, the system operating power supply VDD is enabled to supply power to the VCC voltage detection circuit 40, and when the output voltage of the system operating power supply VDD is lower than the preset value, the charge pump is immediately enabled to provide a stable power supply for the VCC voltage detection circuit 40. power supply, thereby avoiding the performance of the input/output buffer being affected by the instability of the system operating power supply VDD.

Wherein, considering that the working voltage domains of the input/output buffer are mainly 3.3V voltage domain, 2.5V voltage domain, 1.8V voltage domain and 1.2V voltage domain, this embodiment provides several items of the input/output buffer Specific application examples include:

①Using the MOS with a withstand voltage equal to 1.2V and 3.3V as the input/output buffer of the basic device, among them: M1 is a PMOS with a withstand voltage equal to 1.2V, M2 is an NMOS with a withstand voltage equal to 1.2V, and M3 is a withstand voltage PMOS with voltage equal to 3.3V, M4, M5, M6, M7 and M8 are all NMOS with withstand voltage equal to 3.3V.

Wherein, the judgment threshold of the charge pump control circuit 70, that is, the preset value, can be set to 2.7V, of course, it can also be properly adjusted according to the actual situation, without limitation.

② MOS with a withstand voltage equal to 1.2V and 2.5V is used as the input/output buffer of the basic device, among which: M1 is a PMOS with a withstand voltage equal to 1.2V, M2 is an NMOS with a withstand voltage equal to 1.2V, and M3 is a withstand voltage PMOS with voltage equal to 2.5V, M4, M5, M6, M7 and M8 are all NMOS with withstand voltage equal to 2.5V.

③Using MOS with a withstand voltage equal to 1.2V and 1.8V as the input/output buffer of the basic device, among which: M1 is a PMOS with a withstand voltage equal to 1.2V, M2 is an NMOS with a withstand voltage equal to 1.2V, and M3 is a withstand voltage PMOS with voltage equal to 1.8V, M4, M5, M6, M7 and M8 are all NMOS with withstand voltage equal to 1.8V.

④ MOS with a withstand voltage equal to 1.8V and 3.3V is used as the input/output buffer of the basic device, among which: M1 is a PMOS with a withstand voltage equal to 1.8V, M2 is an NMOS with a withstand voltage equal to 1.8V, and M3 is a withstand voltage PMOS with voltage equal to 3.3V, M4, M5, M6, M7 and M8 are all NMOS with withstand voltage equal to 3.3V.

⑤Using MOS with a withstand voltage equal to 1.8V and 2.5V as the input/output buffer of the basic device, where: M1 is a PMOS with a withstand voltage equal to 1.8V, M2 is an NMOS with a withstand voltage equal to 1.8V, and M3 is a withstand voltage PMOS with voltage equal to 2.5V, M4, M5, M6, M7 and M8 are all NMOS with withstand voltage equal to 2.5V.

⑥Using MOS with a withstand voltage equal to 2.5V and 3.3V as the input/output buffer of the basic device, where: M1 is a PMOS with a withstand voltage equal to 2.5V, M2 is an NMOS with a withstand voltage equal to 2.5V, and M3 is a withstand voltage PMOS with voltage equal to 3.3V, M4, M5, M6, M7 and M8 are all NMOS with withstand voltage equal to 3.3V.

The compatible voltage domains of the above-mentioned several input/output buffers are selected according to actual conditions. Taking the first type of input/output buffer as an example, its compatible voltage domain includes 1.2V voltage domain and 3.3V voltage domain, and it can also be compatible with 1.8V voltage domain and 2.5V voltage domain in occasions that require less impact on PVT The voltage domain, that is, the first type of input/output buffer defaults to the 1.8V voltage domain, 2.5V voltage domain and 3.3V voltage domain as the high voltage domain, and the default 1.2V voltage domain as the low voltage domain. Taking the fourth type of input/output buffer as an example, its compatible voltage domain includes 1.8V voltage domain and 3.3V voltage domain, and it can also be compatible with 2.5V voltage domain at the same time in occasions that require less impact on PVT, that is , The ④ input/output buffer defaults to the 2.5V voltage domain and the 3.3V voltage domain as the high voltage domain, and the default 1.8V voltage domain as the low voltage domain. The principles of other examples are the same, and will not be listed one by one.

Finally, it should be noted that during production and development of the input/output buffer, the impedance of M5 and M6 in the overvoltage prevention circuit and the delay of the input/output buffer need to be considered, such as: The impedance shown by the voltage circuit when it works under different PVT conditions is used to analyze its impact on the performance of the input/output buffer; and the impact on the SSN is estimated based on the impedance of the anti-overvoltage circuit, so that it is reasonable Select the impedance of M5 and M6, and fine-tune the turn-on speed of the I/O buffers and the turn-on timing of each I/O buffer to improve the performance of the SSN.

To sum up, the present invention turns off the low-voltage application driver stage with a MOS of a low withstand voltage value as a basic device when detecting that the input/output buffer is operating in a high voltage domain, and starts the MOS with a high withstand voltage value as a basic device. The high-voltage application driver stage of the device; when it is detected that it is working in the low-voltage domain, start the low-voltage application driver stage and turn off the high-voltage application driver stage; thereby reducing the MOS with high withstand voltage value in low-voltage applications. The influence of PVT changes improves the performance of the input/output buffer; at the same time, it avoids the overvoltage breakdown of the MOS with low withstand voltage value in high voltage applications, and because there is no need to use multiple MOS with low withstand voltage values for superposition Compression resistance, so it will not increase the area of the input/output buffer and the difficulty of ESD protection circuit design;

In addition, when the output voltage of the working power supply of the system is unstable, the present invention introduces a charge pump circuit to provide a stable power supply for the VCC voltage detection circuit, thereby ensuring the performance of the input/output buffer.

The above description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the embodiments of the present invention . Therefore, the embodiments of the present invention will not be limited to these embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims (8)

1. A multi-voltage domain input/output buffer, characterized in that it includes a VCC voltage detection circuit, a pre-driver stage, a low-voltage application driver stage with the first MOS and the second MOS, with the third MOS and the fourth MOS high-voltage application driver stage, with the fifth MOS, the sixth MOS, the seventh MOS and the eighth MOS anti-overvoltage circuit, a charge pump circuit, and a charge pump control circuit, wherein: The VCC voltage detection circuit has a first power input pin connected to the system operating power supply, a second power input pin connected to the charge pump circuit, a power output pin connected to the pre-driver stage, and an input The input pin connected to the working power supply of the /output buffer, and the first output pin and the second output pin connected to the pre-driver stage are used to detect that the working power supply of the input/output buffer is In the high voltage domain, control the first output pin to output low level, the second output pin to output high level, and when it is detected that the working power supply of the input/output buffer is in the low voltage domain, control all The first output pin outputs a high level, and the second output pin outputs a low level; The charge pump control circuit is respectively connected with the charge pump circuit, the VCC voltage detection circuit and the system working power supply, and is used to turn on the the charge pump circuit, and disconnect the connection between the VCC voltage detection circuit and the system operating power supply; otherwise, close the charge pump circuit, and restore the connection between the VCC voltage detection circuit and the system operation power supply, wherein The selection of the preset value is determined by the working power supply voltage of the input/output buffer; The pre-driver stage has a first output pin, a second output pin, a third output pin and a fourth output pin, which are used to detect that the first output pin of the VCC voltage detection circuit is a high voltage level, when the second output pin is low level, control the third output pin of the pre-driver stage to output high level, the fourth output pin output low level, and detect the VCC voltage detection circuit When the first output pin is at low level and the second output pin is at high level, control the first output pin of the pre-driver stage to output high level, and the second output pin to output low level; For the first MOS, its gate is connected to the first output pin of the pre-driver stage, and its drain is connected to the drain of the second MOS; For the second MOS, its gate is connected to the second output pin of the pre-driver stage, and its source is grounded; For the third MOS, its gate is connected to the third output pin of the pre-driver stage, its source is connected to the operating power supply of the input/output buffer, and its drain is connected to the drain of the fourth MOS ; For the fourth MOS, its gate is connected to the fourth output pin of the pre-driver stage, and its source is grounded; For the fifth MOS, its gate is connected to the first output pin of the VCC voltage detection circuit, its drain is connected to the working power supply of the input/output buffer, and its source is respectively connected to the source of the first MOS and the drain of the seventh MOS; For the sixth MOS, its gate is connected to the first output pin of the VCC voltage detection circuit, its drain is connected to the drain of the third MOS, and its source is connected to the drain of the second MOS; For the seventh MOS, its gate is connected to the second output pin of the VCC voltage detection circuit, and its source is grounded; For the eighth MOS, its gate is connected to the second output pin of the VCC voltage detection circuit, its drain is connected to the drain of the second MOS, and its source is grounded; Wherein, the first MOS is a PMOS with a low withstand voltage, the second MOS is an NMOS with a low withstand voltage, the third MOS is a PMOS with a high withstand voltage, and the fourth MOS and the fifth MOS , the sixth MOS, the seventh MOS and the eighth MOS are NMOS with high withstand voltage; The information input port of the pre-driver stage is the information input port of the I/O buffer, and the drain of the third MOS is the information output port of the I/O buffer. 2. The input/output buffer according to claim 1, wherein the first MOS is a PMOS with a withstand voltage equal to 1.2V, and the second MOS is an NMOS with a withstand voltage equal to 1.2V, so The third MOS is a PMOS with a withstand voltage equal to 3.3V, and the fourth MOS, the fifth MOS, the sixth MOS, the seventh MOS and the eighth MOS are all NMOS with a withstand voltage equal to 3.3V. 3. The I/O buffer according to claim 2, wherein the preset value is equal to 2.7V. 4. The input/output buffer according to claim 1, wherein the first MOS is a PMOS with a withstand voltage equal to 1.2V, and the second MOS is an NMOS with a withstand voltage equal to 1.2V, so The third MOS is a PMOS with a withstand voltage equal to 2.5V, and the fourth MOS, the fifth MOS, the sixth MOS, the seventh MOS and the eighth MOS are all NMOS with a withstand voltage equal to 2.5V. 5. The input/output buffer according to claim 1, wherein the first MOS is a PMOS with a withstand voltage equal to 1.2V, and the second MOS is an NMOS with a withstand voltage equal to 1.2V, so The third MOS is a PMOS with a withstand voltage equal to 1.8V, and the fourth MOS, fifth MOS, sixth MOS, seventh MOS and eighth MOS are all NMOS with a withstand voltage equal to 1.8V. 6. The input/output buffer according to claim 1, wherein the first MOS is a PMOS with a withstand voltage equal to 1.8V, and the second MOS is an NMOS with a withstand voltage equal to 1.8V, so The third MOS is a PMOS with a withstand voltage equal to 3.3V, and the fourth MOS, the fifth MOS, the sixth MOS, the seventh MOS and the eighth MOS are all NMOS with a withstand voltage equal to 3.3V. 7. The input/output buffer according to claim 1, wherein the first MOS is a PMOS with a withstand voltage equal to 1.8V, and the second MOS is an NMOS with a withstand voltage equal to 1.8V, so The third MOS is a PMOS with a withstand voltage equal to 2.5V, and the fourth MOS, the fifth MOS, the sixth MOS, the seventh MOS and the eighth MOS are all NMOS with a withstand voltage equal to 2.5V. 8. The input/output buffer according to claim 1, wherein the first MOS is a PMOS with a withstand voltage equal to 2.5V, and the second MOS is an NMOS with a withstand voltage equal to 2.5V, so The third MOS is a PMOS with a withstand voltage equal to 3.3V, and the fourth MOS, the fifth MOS, the sixth MOS, the seventh MOS and the eighth MOS are all NMOS with a withstand voltage equal to 3.3V.