CN104243931A - ARM (random access memory) camera interface based video collection displaying system - Google Patents
ARM (random access memory) camera interface based video collection displaying system Download PDFInfo
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- CN104243931A CN104243931A CN201410508331.6A CN201410508331A CN104243931A CN 104243931 A CN104243931 A CN 104243931A CN 201410508331 A CN201410508331 A CN 201410508331A CN 104243931 A CN104243931 A CN 104243931A
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Abstract
The invention discloses an ARM (random access memory) camera interface based video collection displaying system which comprises a black-and-white CCD (charge coupled device) camera, a video amplifier or an A/D (analog-digital) convertor, an FPGA (field programmable gate array), an ARM with the camera interface and a video sync separator. An SDRAM (synchronous dynamic random access memory), an FLASH and an LCD (liquid crystal display) touch screen which are connected with the RAM are arranged on the periphery of the ARM, the FPGA receives data video signals outputted by the A/D convertor and converts the digital video signals into a YCbCr4:2:2 format prior to inputting the digital video signals into the digital camera interface of the ARM, and a video is displayed through the LCD touch screen; the video sync separator separates the signals outputted by the black-and-white CCD camera into a horizontal sync signal and a field sync signal which are transmitted to the FPGA, the FPGA generates a camera control sequence by the aid of the horizontal sync signal and the field sync signal and determines the lattice address of a video image on the LCD touch screen, and characters or icons to be displayed are overlapped on the position of the lattice address. By the structure of combining the FPGA with the digital camera interface ARM, video collection displaying speed is high, power consumption is low, and man-machine interaction is realized.
Description
Technical field
The present invention relates to video image technical field, specifically a kind of video acquisition display system based on ARM camera interface.
Background technology
Known, Video Image Collecting System Based is the front terminal system of the systems such as video images detection, multimedia signal processing, video monitoring, it is the important ring in actual video treatment system, the ccd image at present with higher signal quality collects increasing application, and CCD is gathered to the process of image, be the method utilizing import dedicated video decoding chip, dual port RAM and FPGA to combine mostly, greatly, cost is higher on the other hand for complicated structure, power consumption on the one hand; In addition, existing IMAQ display system can not the character that will show or icon and image be superimposed is presented in real time on screen, lacks the function of man-machine interaction.
Summary of the invention
The object of the present invention is to provide a kind of video acquisition display system based on ARM camera interface, this system configuration is simple, collection display speed is fast, low in energy consumption, and can be presented at needing the character of display or icon and imaging importing on screen.
The technical solution adopted for the present invention to solve the technical problems is:
Based on a video acquisition display system for ARM camera interface, comprise the black-white CCD camera, the video amplifier and the A/D converter that are connected successively, described system also comprises:
A. video synchronous separator, the Signal separator that black-white CCD camera exports is gone out line synchronizing signal and field sync signal by video synchronous separator;
B. the input interface for the FPGA of Computer Vision, FPGA connects A/D converter and video synchronous separator respectively; Described FPGA receives the digital video signal that A/D converter exports, and digital video signal is converted to YCbCr 4:2:2 form, FPGA is the line synchronizing signal that exports of receiver, video sync separator and field sync signal also, and utilizes line synchronizing signal and field sync signal to generate camera control sequential;
C. with the ARM of digital camera interface, coupled SDRAM, FLASH and LCD touch screen outside ARM, is arranged with; Video image is sent the vision signal of YCbCr 4:2:2 form and the input of camera control sequential ARM, ARM to LCD touch screen by digital camera interface and shows by described FPGA.
Further, described FPGA also utilizes the dot matrix address of video image in line synchronizing signal and field sync signal determination LCD touch screen, and the character or icon that need display are superimposed upon the position of dot matrix address.
Further, described ARM adopts S3C2440.
The invention has the beneficial effects as follows, by FPGA, the vision signal gathered is processed, convert the YCbCr 4:2:2 form that ARM camera interface needs to, ARM directly sends the vision signal meeting call format received to LCD touch screen and shows, adopt the structure that FPGA combines with band digital camera interface ARM, structure is simple, gathers display speed fast, low in energy consumption; And determined the dot matrix address of video image in LCD touch screen by FPGA, and the character or icon that need display are superimposed upon the position of dot matrix address, realize the function of man-machine interaction.
Accompanying drawing explanation
Below in conjunction with drawings and Examples, the present invention is further described:
Fig. 1 is structured flowchart of the present invention.
Embodiment
As shown in Figure 1, the invention provides a kind of video acquisition display system based on ARM camera interface, comprise the black-white CCD camera 1, the video amplifier 2 and the A/D converter 3 that are connected successively; Described system also comprises video synchronous separator 9, for the FPGA4 of Computer Vision and the ARM5 with digital camera interface, is arranged with coupled SDRAM7, FLASH8 and LCD touch screen 6 outside ARM5; The input of video synchronous separator 9 connects the output of black-white CCD camera 1, and the output of video synchronous separator 9 connects the input of FPGA4, and the output of FPGA4 connects the digital camera interface of ARM5; The described video amplifier 2 adopts LM6361, and A/D converter 3 adopts CXD2302Q, and FPGA4 adopts XC3S200A, ARM5 to adopt S3C2440, and video synchronous separator 9 adopts LM1881.
During work, black-white CCD camera 1 is by the vision signal of collection input a/d converter 3 after the video amplifier 2 amplifies, A/D converter 3 carries out digital translation to the vision signal after amplification, FPGA4 receives the digital video signal that A/D converter 3 exports, filtering process is carried out by median filtering method, by the noise filtering in digital video signal, improve the quality of video.In order to character or the icon of any position superposition for guiding operator of the video image in display in real time, make operator can by LCD touch screen 6 input control signal simultaneously, so will determine the address of each dot matrix of video image in LCD touch screen 6, the Signal separator that black-white CCD camera 1 exports is gone out line synchronizing signal H_SYNC to video synchronous separator 9 and field sync signal V_SYNC sends FPGA4 to, for the LCD touch screen of 640x480, overlaying character or icon the address of each dot matrix on 640x312 video dot matrix will must be determined on the real-time video of 640 x312, the clock of A/D converter 3 can be used to act on the counter of FPGA4, the output of counter is from 0 ~ 639 counting, counting is stopped when counting down to 639, when line synchronizing signal H_SYNC inputs, by counter O reset, so move in circles, the output of the column address generator of such FPGA4 has just marked off 640 column addresss on the signal of every a line, for the location of horizontal direction pixel.Same, the clock end of FPGA4 another one counter is acted on line synchronizing signal H_SYNC, field sync signal V_SYNC acts on the clear terminal of this counter, often detect arrival line synchronizing signal, counter adds 1, stops counting when counting 311, during field sync signal V_SYNC input, this counter O reset, so moves in circles, and the output of the row address generator of such FPGA4 just marks off 312 row addresses in the vertical direction of image.There are row address and column address, just can have determined the lattice position of any point on video image, be reached for the location object that character or icon superpose on realtime graphic.Owing to there being the BLOCK RAM of 288k in FPGA4, therefore can the character that will show or icon be existed in this BLOCK RAM, by the multiplexer of FPGA4, the address wire of the address wire of CPU in FPGA4 and rank addresses generator is connected in the address wire of BLOCK RAM, like this, CPU just first can write in BLOCK RAM character or icon, when needing to show the information in BLOCK RAM, address wire on BLOCK RAM is switched on rank addresses line, when arriving in the display address set, data in BLOCK RAM are just read out, because rank addresses constantly moves in circles, data in BLOCK RAM are also recycled reading, therefore the character in the lattice position of specifying or icon information can not cover by view data, but refresh together with image, character or icon are stably superimposed upon on image, real time video data through medium filtering superposes black information on image with the character read in BLOCK RAM or icon data by logical "and", by logical "or" superposition light tone information on image, realize the superposition of character or icon.
Superpose the real time video data of character or icon, ITU-R BT.601 YCbCr 4:2:2 form must be converted to, the requirement of ARM5 digital camera interface could be met, the control signal of digital camera interface has CAMVSYNC, CAMHERF and CAMPCLK, and CAMVSYNC signal is exactly the paraphase of field sync signal V_SYNC, CAMHREF signal is exactly line synchronizing signal H_SYNC, CAMPCLK is 2 frequencys multiplication of A/D converter 3 clock, the clock signal of A/D converter 3 is connected to the CLK_IN end of digital dock administration module DCM in FPGA4, CLK2X end just exports 2 frequency-doubled signals of A/D converter clock, i.e. CAMPCLK signal, YCbCr 4:2:2 according to ITU-R BT.601 advises, the luminance and chrominance information of digital video obtains by formula below:
Y?=?0.257*R?+?0.504*G?+?0.098*B?+?16
Cb?=?-0.148*R?-?0.291*G?+?0.439*B?+?128
Cr?=?0.439*R?-?0.368*G?-?0.071*B?+?128
In formula, R, G, B is the three primary colors of image, to display black and white image, then make R=G=B, now, Y, Cb, Cr just represents black and white digital video, by above-mentioned formula, the digital camera interface of ARM5 is inputted after the real time video data having superposed character or icon being converted to ITU-R BT.601 YCbCr 4:2:2 form, ARM delivers to video data with its special camera DMA passage the video memory of system, then with its special display DMA passage, video data is sent to LCD touch screen to show, owing to adopting dma mode, the load of ARM is very low, video memory data can be read at random fast.Native system is without the need to using dedicated video decoding chip, adopt the structure that FPGA combines with band digital camera interface ARM, gather display speed fast, low in energy consumption, and can be presented on screen by needing the character of display or icon and imaging importing, realize the function of man-machine interaction.
The above is only preferred embodiment of the present invention, not does any pro forma restriction to the present invention; Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent replacement, equivalence change and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (3)
1., based on a video acquisition display system for ARM camera interface, comprise the black-white CCD camera, the video amplifier and the A/D converter that are connected successively, it is characterized in that, described system also comprises:
A. video synchronous separator, the Signal separator that black-white CCD camera exports is gone out line synchronizing signal and field sync signal by video synchronous separator;
B. the input interface for the FPGA of Computer Vision, FPGA connects A/D converter and video synchronous separator respectively; Described FPGA receives the digital video signal that A/D converter exports, and digital video signal is converted to YCbCr 4:2:2 form, FPGA is the line synchronizing signal that exports of receiver, video sync separator and field sync signal also, and utilizes line synchronizing signal and field sync signal to generate camera control sequential;
C. with the ARM of digital camera interface, coupled SDRAM, FLASH and LCD touch screen outside ARM, is arranged with; Video image is sent the vision signal of YCbCr 4:2:2 form and the input of camera control sequential ARM, ARM to LCD touch screen by the digital camera interface of ARM and shows by described FPGA.
2. a kind of video acquisition display system based on ARM camera interface according to claim 1, it is characterized in that, described FPGA also utilizes the dot matrix address of video image in line synchronizing signal and field sync signal determination LCD touch screen, and the character or icon that need display are superimposed upon the position of dot matrix address.
3. a kind of video acquisition display system based on ARM camera interface according to claim 1 and 2, is characterized in that, described ARM adopts S3C2440.
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| CN106231264A (en) * | 2016-08-10 | 2016-12-14 | 哈尔滨理工大学 | A kind of farmland image capturing system |
| CN106506961A (en) * | 2016-11-29 | 2017-03-15 | 中国科学院长春光学精密机械与物理研究所 | An image processing system and image processing method |
| CN107329460A (en) * | 2017-07-18 | 2017-11-07 | 哈尔滨理工大学 | A kind of novel engraving machine control system |
| CN107370924A (en) * | 2017-07-18 | 2017-11-21 | 西安电子科技大学 | Image Acquisition System |
| CN110991522A (en) * | 2019-11-29 | 2020-04-10 | 山东万腾电子科技有限公司 | Character recognition method and system and industrial intelligent gateway |
| CN116095255A (en) * | 2023-02-08 | 2023-05-09 | 北京镁伽机器人科技有限公司 | Superimposed image generation method, device, equipment and medium |
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| CN116095255A (en) * | 2023-02-08 | 2023-05-09 | 北京镁伽机器人科技有限公司 | Superimposed image generation method, device, equipment and medium |
| CN116095255B (en) * | 2023-02-08 | 2025-03-07 | 北京镁伽机器人科技有限公司 | A superimposed image generation method, device, equipment and medium |
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