CN104218001B - A manufacturing method of flash memory gate - Google Patents

Abstract

The invention discloses a method for manufacturing a flash gate, which comprises the steps of: forming a shallow trench, field oxygen, and isolating an active region. Ion implantation is performed to form the well region of the flash memory. An ONO layer and a polysilicon layer are sequentially grown on the surface of the silicon substrate and the polysilicon layer is doped. A metal tungsten silicide layer is deposited on the surface of the polysilicon layer. The fourth silicon nitride layer and the fifth silicon nitride layer are grown sequentially by furnace tube technology and chemical vapor deposition technology, and are stacked to form a gate hard mask layer. The gate hard mask layer, the metal tungsten silicide layer and the polysilicon layer are sequentially etched by a photolithography process to form the gate of the flash memory. The invention can maintain a good shape of the gate, can repair the ONO defect of the flash memory well, thereby improving the life of the flash memory and eliminating the durability test problem caused when the silicon nitride layer is formed by a chemical vapor deposition process alone , can effectively prevent the depletion of polysilicon.

Description

Manufacturing method of flash memory gate

technical field

The invention relates to a manufacturing process method of a semiconductor integrated circuit, in particular to a manufacturing method of a flash memory gate.

Background technique

As shown in Figure 1, it is a top view of the flash memory formed by the existing method; as shown in Figure 2, it is a cross-sectional view of the flash memory along the line AA' in Figure 1. The existing method for forming the gate of the flash memory includes the following steps:

Step 1. Form shallow trenches on the silicon substrate 101 by photolithography, and define an active region by the shallow trenches; fill the shallow trenches with silicon oxide to form shallow trench field oxygen 103, and form shallow trench field oxygen 103 by shallow trench field oxygen 103 isolates the active area.

Step 2, growing a sacrificial oxide layer on the surface of the active region of the silicon substrate 101 .

Ion implantation is performed to form the well region 102 of the flash memory, and the ion implantation of the well region 102 passes through the sacrificial oxide layer. The well area 102 of the flash memory includes an N-type well area or a P-type well area, the N-type well area is located in the flash memory area whose channel type is a P-type channel, and the P-type well area is located in a channel type where the channel type is an N-type channel in the flash memory area.

After the well region 102 is formed, a wet etching process is used to remove the sacrificial oxide layer.

Step 3, growing the first layer of silicon oxide, the second layer of silicon nitride and the third layer of silicon oxide in sequence on the surface of the silicon substrate 101, and the first layer of silicon oxide, the second layer of silicon nitride and the third layer of oxide ONO layer 104 is formed by stacking silicon, and a layer of polysilicon layer 105 is deposited on the surface of ONO layer 104, and the polysilicon layer 105 is doped with P-type or N-type by ion implantation process; P-type doping is performed on the polysilicon layer 105 in the region, and N-type doping is performed on the polysilicon layer located in the flash memory region whose channel type is an N-type channel.

Step 4, depositing a metal tungsten silicide layer 106 on the surface of the polysilicon layer 105 .

Step 5: Deposit a silicon nitride layer 107 on the surface of the metal tungsten silicide layer 106 by furnace tube technology, and form the gate hard mask layer 107 from the silicon nitride layer 107 .

Step 6. Form a photoresist pattern by photolithography and define the gate pattern of the flash memory by the photoresist pattern; use the photoresist pattern as a mask to etch the gate hard mask layer 107, and use photolithography The glue pattern and the gate hard mask layer 107 are used as masks to etch the metal tungsten silicide layer and the polysilicon layer in sequence to form the gate hard mask layer, the metal tungsten silicide layer and the polysilicon layer stacked to form the gate of the flash memory.

In the existing semiconductor flash memory gate process method, the gate hard mask layer composed of silicon nitride layer is usually grown by furnace tube method; the advantage of the gate hard mask layer grown by furnace tube method is During the process, the hard mask layer of the gate can provide good protection for the gate and maintain the shape of the gate after etching. However, the high-temperature heat treatment of the furnace tube process for a long time will cause the boron ions in the P-type polysilicon layer to diffuse to the metal tungsten silicide layer, thereby reducing the concentration of boron ions in the P-type polysilicon layer, resulting in the depletion of polysilicon when the transistor is working.

The silicon nitride layer in the existing method can also be grown by a chemical vapor deposition process with a lower process temperature. If the silicon nitride layer formed by the chemical vapor deposition process is used as the gate hard mask layer, although it can avoid The boron ion of the P-type polysilicon layer produced by the furnace tube process diffuses into the defect of the metal tungsten silicide layer, but due to the defects in the ONO layer in the flash memory, the chemical vapor deposition process cannot eliminate the defects in the ONO layer, and the existence of these defects will reduce The lifespan of the flash memory does not pose a problem for endurance testing of flash memory devices.

Contents of the invention

The technical problem to be solved by the present invention is to provide a method for manufacturing the flash gate, which can keep the gate in good shape, eliminate the problem of durability testing, and effectively prevent the depletion of polysilicon.

In order to solve the above-mentioned technical problems, the manufacturing method of flash gate provided by the present invention comprises the following steps:

Step 1, using a photolithographic etching process to form shallow trenches on the silicon substrate, defining an active region by the shallow trenches; filling the shallow trenches with silicon oxide to form shallow trench field oxygen, and forming shallow trench field oxygen by the shallow trenches The shallow trench field oxygen isolates the active region.

Step 2, performing ion implantation to form a well region.

Step 3, growing a first layer of silicon oxide, a second layer of silicon nitride, and a third layer of silicon oxide sequentially on the surface of the silicon substrate, and removing the first layer of silicon oxide and the second layer of silicon oxide outside the flash memory area. Silicon nitride and the third layer of silicon oxide, the first layer of silicon oxide remaining in the flash memory area, the second layer of silicon nitride and the third layer of silicon oxide are stacked to form an ONO layer; The gate dielectric layer of the CMOS device integrated with the flash memory is formed on the surface of the silicon substrate outside the flash memory area, and a polysilicon layer is deposited on the surface of the ONO layer and the gate dielectric layer, and an ion implantation process is used for the gate dielectric layer. The polysilicon layer is doped with P-type or N-type.

Step 4, depositing a metal tungsten silicide layer on the surface of the polysilicon layer.

Step 5, using a furnace tube process to deposit a fourth silicon nitride layer on the surface of the metal tungsten silicide layer; using a chemical vapor deposition process to deposit a fifth silicon nitride layer on the surface of the fourth silicon nitride layer, by The fourth silicon nitride layer and the fifth silicon nitride layer are stacked to form a gate hard mask layer; the temperature conditions of the furnace tube process of the fourth silicon nitride layer will affect the nitriding of the ONO layer The interface defects between silicon and silicon oxide are repaired, and the boron ions of the P-type doped polysilicon layer can be diffused into the metal tungsten silicide layer, under the condition that the total thickness of the gate hard mask layer remains unchanged Next, the thicknesses of the fourth silicon nitride layer and the fifth silicon nitride layer are set such that the interface defects of the ONO layer can be fully repaired during the furnace tube process time of the fourth silicon nitride layer Under certain conditions, the thinner the thickness of the fourth silicon nitride layer, the better.

Step 6: Define the gate pattern of the flash memory by photolithography; etch the gate hard mask layer, the metal tungsten silicide layer and the polysilicon layer in sequence according to the gate pattern defined by photolithography After etching, the gate hard mask layer outside the gate region, the metal tungsten silicide layer and the polysilicon layer are all removed, and the gate hard mask layer remaining in the gate region , the metal tungsten silicide layer and the polysilicon layer overlap to form the gate of the flash memory.

A further improvement is that the thickness of the fourth silicon nitride layer described in step five is 300 ~600 , the thickness of the fifth silicon nitride layer is 900 ~1200 .

A further improvement is that the well region in step 2 includes an N-type well region or a P-type well region, the N-type well region is located in the PMOS device area of the CMOS device, and the P-type well area is located in the flash memory area and the In the NMOS device region in the CMOS device described above.

A further improvement is that in step 3, N-type doping is performed on the polysilicon layer located in the flash memory area and the NMOS device area in the CMOS device, and N-type doping is performed on the polysilicon layer located in the PMOS device area in the CMOS device. P-type doping is performed in the polysilicon layer.

A further improvement is that the furnace tube process in step five is LPCVD, and the chemical vapor deposition process is PECVD.

A further improvement is that the temperature of the furnace tube process is 720°C, and the temperature of the chemical vapor deposition process is 400°C.

A further improvement is that the sufficient repair of the interface defect of the ONO layer described in step five is subject to the durability test.

A further improvement is that the condition for meeting the durability test is: the flash memory can operate normally after performing 110K cycles of erasing and programming operations on the flash memory at a temperature of 55°C.

In the present invention, the grid hard mask layer composed of a silicon nitride layer is divided into two layers, and the furnace tube process and the chemical vapor deposition process are sequentially used to form the gate hard mask layer. Good protection, so that the morphology of the gate can be well maintained; meanwhile, the method of the present invention can well repair the interface defects of silicon nitride and silicon oxide in the ONO layer by using the furnace tube process, which can improve the service life of the flash memory and Eliminate the durability test problems caused by the chemical vapor deposition process alone to form the silicon nitride layer; the use of chemical vapor deposition process can avoid the diffusion of boron in the P-type polysilicon layer to the metal silicide caused by the high temperature of the furnace tube for a long time Defects in the tungsten layer can effectively prevent polysilicon depletion.

Description of drawings

Below in conjunction with accompanying drawing and specific embodiment the present invention will be described in further detail:

Fig. 1 is the top view of the flash memory that existing method forms;

Fig. 2 is a cross-sectional view of the flash memory along line AA' in Fig. 1;

Fig. 3 is the flowchart of the embodiment method of the present invention;

Fig. 4 is the sectional view of flash memory in the embodiment method of the present invention;

Fig. 5 is a cross-sectional view of the flash memory along line BB' in Fig. 4 .

detailed description

As shown in Figure 3, it is a flowchart of the method of the embodiment of the present invention; as shown in Figure 4, it is a cross-sectional view of the flash memory in the method of the embodiment of the present invention; as shown in Figure 5, it is a flash memory along the BB' line in Figure 4 sectional view. The manufacturing method of the flash memory gate in the embodiment of the present invention comprises the following steps:

Step 1. Forming a shallow trench on the silicon substrate 1 by photolithography, and defining an active region by the shallow trench; filling the shallow trench with silicon oxide to form a shallow trench field oxygen 3, The active region is isolated by the shallow trench field oxygen 3;

Step 2, performing ion implantation to form the well region 2 of the flash memory. In the embodiment of the present invention, the flash memory and the CMOS device used for the peripheral circuit of the flash memory are integrated and manufactured, and the CMOS device includes two types of PMOS device and NMOS device. The well region 2 includes an N-type well region 2 or a P-type well region 2, the N-type well region 2 is located in the PMOS device region, and the P-type well region 2 is located in the flash memory region and the NMOS device region.

Step 3: growing a first layer of silicon oxide, a second layer of silicon nitride, and a third layer of silicon oxide on the surface of the silicon substrate 1 in sequence, and removing the first layer of silicon oxide and silicon oxide outside the flash memory area by an etching process. The second layer of silicon nitride and the third layer of silicon oxide are superimposed by the first layer of silicon oxide, the second layer of silicon nitride and the third layer of silicon oxide remaining in the flash memory area Forming an ONO layer 4; forming a gate dielectric layer of the CMOS device on the surface of the silicon substrate 1 outside the flash memory area, depositing a layer of polysilicon layer 5 on the surface of the ONO layer and the gate dielectric layer, and P-type or N-type doping is performed on the polysilicon layer 5 by ion implantation process. The specific doping area is to perform N-type doping on the polysilicon layer located in the flash memory area and the NMOS device area in the CMOS device, and perform N-type doping on the polysilicon layer located in the PMOS device area in the CMOS device. P-type doping is carried out in the polysilicon layer.

Step 4, depositing a metal tungsten silicide layer 6 on the surface of the polysilicon layer 5 .

Step 5. Deposit the fourth silicon nitride layer 7 on the surface of the metal tungsten silicide layer 6 by using a furnace tube process, the furnace tube process is LPCVD, and the process temperature is 720°C. The fifth silicon nitride layer 8 is deposited on the surface of the fourth silicon nitride layer 7 by chemical vapor deposition process, the chemical vapor deposition process is PECVD, and the process temperature is 400°C. A gate hard mask layer is formed by overlapping the fourth silicon nitride layer 7 and the fifth silicon nitride layer 8 . The temperature conditions of the furnace tube process of the fourth silicon nitride layer 7 will repair the defects of the ONO layer 4, and will diffuse the boron ions of the P-type doped polysilicon layer 5 into the metal silicide In the tungsten layer 6, under the condition that the total thickness of the gate hard mask layer remains unchanged, the thicknesses of the fourth silicon nitride layer 7 and the fifth silicon nitride layer 8 are set as follows: Under the condition that the furnace tube process time of the silicon nitride layer 7 can make the defects of the ONO layer 4 fully repaired, the thinner the thickness of the fourth silicon nitride layer 7, the better; the interface defects of the ONO layer 4 Sufficient repair of the flash memory shall be subject to meeting the durability test; the condition of satisfying the durability test is: the flash memory can operate normally after performing 110K cycles of erasing and programming operations on the flash memory at a temperature of 55°C. Preferably, the thickness of the fourth silicon nitride layer is 300 ~600 , the thickness of the fifth silicon nitride layer is 900 ~1200 .

Step 6: Forming a photoresist pattern using a photolithography process, defining the gate pattern of the flash memory in the flash memory region by the photoresist pattern, and defining the photoresist pattern in the CMOS device region at the same time The gate pattern of the CMOS device is obtained; the gate hard mask layer is etched to form a hard mask pattern with the photoresist pattern as a mask, and the photoresist pattern and the hard mask The metal tungsten silicide layer 6 and the polysilicon layer 5 are sequentially etched using the film pattern as a mask or using the hard mask pattern alone, and the gate hard mask outside the gate area is etched The film layer, the metal tungsten silicide layer 6 and the polysilicon layer 5 are all removed, and the gate hard mask layer remaining in the gate region, the metal tungsten silicide layer 6 and the polysilicon layer 5. Overlapping and forming gates of the flash memory and the CMOS device on the flash memory area and the CMOS device area respectively.

The present invention has been described in detail through specific examples above, but these do not constitute a limitation to the present invention. Without departing from the principle of the present invention, those skilled in the art can also make many modifications and improvements, which should also be regarded as the protection scope of the present invention.

Claims (7)

1. a kind of manufacture method of flash memory grid is it is characterised in that comprise the steps：

Step one, form shallow trench on a silicon substrate using lithographic etch process, active area is defined by described shallow trench；Institute State filling silica in shallow trench and form shallow trench field oxygen, by described shallow trench field oxygen, described active area is isolated；

Step 2, carry out ion implanting formed well region；

Step 3, grow ground floor silica, second layer silicon nitride and third layer silica successively on the surface of described silicon substrate, Remove described ground floor silica outside flash area, described second layer silicon nitride and described third layer silica, by remaining in The described ground floor silica of described flash area, described second layer silicon nitride and the superposition of described third layer silica form ONO Layer；Described surface of silicon outside described flash area forms the gate dielectric layer with the integrated cmos device of flash memory, described Deposit one layer of polysilicon layer on ONO layer and described gate dielectric layer surface, and using ion implantation technology, described polysilicon layer is entered Row p-type or n-type doping；

It is pointed to carry out N in the described polysilicon layer in the nmos device region in described flash area and described cmos device Type adulterates, and is pointed to carry out p-type doping in the described polysilicon layer in the PMOS device region in described cmos device；

Step 4, in described polysilicon layer surface deposited metal tungsten silicide layer；

Step 5, using furnace process in described metal silication tungsten layer surface deposition the 4th silicon nitride layer；Formed sediment using chemical gaseous phase Long-pending technique, in described 4th silicon nitride layer surface deposition the 5th silicon nitride layer, is nitrogenized by described 4th silicon nitride layer and the described 5th Silicon layer superposition forms grid hard mask layer；The temperature conditionss of the furnace process of described 4th silicon nitride layer can be to described ONO layer The boundary defect of silicon nitride and silica carries out repairing and can make the boron ion of the described polysilicon layer of p-type doping to be diffused into In described metal silication tungsten layer, under conditions of described grid hard mask layer gross thickness is constant, described 4th silicon nitride layer and institute The thickness stating the 5th silicon nitride layer is set to：Enable to described ONO layer in the furnace process time of described 4th silicon nitride layer Boundary defect fully repair under conditions of, the thickness of described 4th silicon nitride layer gets over Bao Yuehao；

Step 6, define the gate patterns of described flash memory using photoetching process；Right successively according to the gate patterns of lithographic definition Described grid hard mask layer, described metal silication tungsten layer and described polysilicon layer perform etching, the institute outside etching post tensioned unbonded prestressed concrete region State grid hard mask layer, described metal silication tungsten layer and described polysilicon layer to be all removed, by remaining in described area of grid Described grid hard mask layer, described metal silication tungsten layer and the superposition of described polysilicon layer form the grid of described flash memory.

2. flash memory grid as claimed in claim 1 manufacture method it is characterised in that：4th silicon nitride layer described in step 5 Thickness beThe thickness of described 5th silicon nitride layer is

3. flash memory grid as claimed in claim 1 manufacture method it is characterised in that：Described in step 2, well region includes N-type Well region or P type trap zone, N-type well region is located in the PMOS device region in described cmos device, and P type trap zone is located at described flash memory area In nmos device region in domain and described cmos device.

4. flash memory grid as claimed in claim 1 manufacture method it is characterised in that：Described in step 5, furnace process is LPCVD, described chemical vapor deposition method is PECVD.

5. the flash memory grid as described in claim 1 or 4 manufacture method it is characterised in that：The temperature of described furnace process is 720 DEG C, the temperature of described chemical vapor deposition method is 400 DEG C.

6. flash memory grid as claimed in claim 1 manufacture method it is characterised in that：The interface of ONO layer described in step 5 The abundant reparation of defect is defined by meeting durability test.

7. flash memory grid as claimed in claim 6 manufacture method it is characterised in that：The condition meeting durability test is： Under 55 DEG C of temperature conditionss, after described flash memory is carried out with the circulation erase and program operations of 110K time, flash memory can normally run.