CN104216681A - CPU instruction processing method and processor - Google Patents

Abstract

The invention provides a CPU instruction processing method and a processor, and relates to the field of computers. Register resources can be saved, and power consumed by register reading and writing can be reduced. The method comprises the steps that when a result of a first instruction is only used one time by a second instruction after the first instruction, an intermediate result of the first instruction and the second instruction is not written back to a register file, and the register storing the intermediate result is not renamed in the register renaming period, in other words, the register storing the intermediate result is not mapped to be a physical register. The CPU instruction processing method and the processor are used for instruction result transfer.

Description

A CPU instruction processing method and processor

technical field

The invention relates to the field of computers, in particular to a CPU instruction processing method and a processor.

Background technique

Most of the current processors (Center Process Unit, CPU) use pipeline technology. The basic five-stage pipeline includes fetching (that is, fetching instructions), decoding (that is, decoding instructions), and execution (that is, executing instructions). , memory access (that is, write data into the memory, or read data from the memory), write back (that is, write data to the register file), within the same cycle, there can be 5 instructions at different pipeline levels.

There are three kinds of dependencies among the executed instructions, namely, data dependencies, control dependencies and structure dependencies. And there are three types of data correlation: Read After Write (RAW), that is, the data written by the previous command is used in the following instructions; Write After Write (WAW), that is, two Two instructions write to the same unit at the same time; Write After Read (WAR), that is, the read data will be written by the following instruction. Data correlation may cause the pipeline to be blocked. For example, when the pipeline requires an instruction to read a register in the decoding stage, the register is the target register of the previous instruction in the pipeline, and the result has not been written back, then the instruction must be in the decoding stage. wait.

In order to solve the above blocking problem and improve the efficiency of the pipeline, the current general practice in the industry is to use forwarding technology (Forwarding), also known as bypass technology (Bypass), that is, when the following instructions use the operation of the previous instruction or memory access When the result is obtained, the result can be obtained directly through the bypass without waiting for the result to be written back to the register, and the correlation between WAW and WAR can be avoided through register renaming, thereby improving the efficiency of instruction-level parallelism. In fact, the registers used in the program are logical registers visible to the programmer. These programmer-visible registers are also called structural registers. In actual hardware execution, these registers are remapped to micro-architectural registers that are not visible to the programmer.

For a general integer operation instruction sequence, it needs to go through instruction fetching, decoding, and register renaming (Rename), and then send it to the issue queue (Issue queue). Instructions in the emission queue, if it is found that the value of its source operand is ready, then it can be sent to the idle Fix Point Arthmetic Unit (FX) to perform integer operations. The operation result is written back (Write Back, WB) and stored in the register file.

The stage of register renaming is the process of mapping structural registers (visible to programmers) to physical registers (not visible to programmers), which can avoid WRW and WAR correlation.

In the process of realizing the above solution to the blocking problem, the inventors have found that at least the following problems exist in the prior art:

With the increase of functional units (Function Unit), the register file (Register File) is getting bigger and bigger, and the reading and writing of the register file is quite energy-consuming. In fact, the results of many instructions are often only used by the next one, or one of the next few instructions, and are only used once. For such results that are only used once, write them back to the register file , which is actually a waste of register resources.

Contents of the invention

Embodiments of the present invention provide a CPU instruction processing method and a processor, which can save register resources and reduce the power consumption required for reading and writing relay registers.

In order to achieve the above object, embodiments of the present invention adopt the following technical solutions:

In a first aspect, a CPU instruction processing method is provided, the method comprising:

judging whether the result of the first instruction is only used once by a second instruction following the first instruction;

If the result is only used once by a second instruction following the first instruction, the result of the first instruction is not written back to the register file;

Sending the first instruction and the second instruction to the functional unit for calculation, so that the first instruction is executed before the second instruction, and the processing result of the first instruction is transferred to the second instruction as the second instruction The source operand for the instruction.

In a first possible implementation manner, in combination with the first aspect, the judging whether the result of the first instruction is only used once by the instruction after the first instruction includes:

In the decoding stage, it is identified whether the first instruction and the second instruction have a special identifier, and if there is a special identifier, it is determined that the result of the first instruction is only used once by the second instruction after the first instruction.

In the second possible implementation manner, in combination with the first aspect or the first implementation manner of the first aspect, the judging whether the result of the first instruction is only used once by the instruction after the first instruction further includes:

If the first register is used as the storage register for the result of the first instruction and is only used as the source operand of the second instruction, then it is determined that the result of the first instruction is only used once by the instruction after the first instruction , specifically identify the first instruction and the second instruction.

In a third possible implementation manner, in combination with the second possible implementation manner of the first aspect, special identification of the first instruction and the second instruction includes:

The first register is replaced with a special register, and a special relationship mark is made between the first instruction and the second instruction.

In a fourth possible implementation manner, in combination with the second possible implementation manner of the first aspect, special identification of the first instruction and the second instruction includes:

A special bit is added after the first instruction and the second instruction to mark the relationship between the first instruction and the second instruction.

In a fifth possible implementation manner, in combination with the first aspect or any one of the first to fourth possible implementation manners of the first aspect, the transmitting the first instruction and the second instruction to the function Performing operations in the unit so that the first instruction is executed prior to the second instruction, and transferring the processing result of the first instruction to the second instruction includes:

If the first instruction and the second instruction are two consecutive instructions, the result of the first instruction is directly passed to the second instruction through the forward path as the source operation of the second instruction number;

If the first instruction and the second instruction are two discontinuous instructions, after the execution of the first instruction, cache the result of the first instruction in the functional unit, when the second instruction When the second instruction is executed, the result of the first instruction is transferred to the second instruction as a source operand of the second instruction.

In a sixth possible implementation manner, in combination with the first aspect or the first to fifth possible implementation manners of the first aspect, the method further includes:

If the result is only used once by the second instruction after the first instruction, no renaming operation is performed on the register where the result of the first instruction is located in the renaming stage.

In a seventh possible implementation manner, in combination with the first aspect or any one of the first to sixth possible implementation manners of the first aspect, the method further includes:

Notifying the reordering buffer after the execution of the first instruction is completed, so as to submit the first instruction according to the ordering rules in the reordering buffer;

After the execution of the second instruction is completed, the result of the second instruction is written back to the register file, and the reordering buffer is notified, so that the second instruction is submitted according to the ordering rules in the reordering buffer .

In an eighth possible implementation manner, in combination with the first aspect or the first to seventh possible implementation manners of the first aspect, the method further includes:

After the execution of the first instruction and the second instruction is completed, submit the first instruction and the second instruction at the same time;

When an exception occurs in the execution of the first instruction and/or the second instruction, the first instruction and the second instruction are re-executed.

In a second aspect, a processor is provided, and the processor includes:

a judging unit, configured to judge whether the result of the first instruction is only used once by a second instruction following the first instruction;

An execution unit configured to not write the result of the first instruction back to the register file if the result is only used once by a second instruction following the first instruction; and execute the first instruction and the second instruction;

an issuing unit, configured to transmit the first instruction and the second instruction to the functional unit for calculation, so that the first instruction is executed prior to the second instruction, and the processing result of the first instruction is transferred to the second instruction, as the source operand for the second instruction.

In a first possible implementation manner, in combination with the second aspect, the judgment unit is specifically configured to:

In the decoding stage, it is identified whether the first instruction and the second instruction have a special identifier, and if there is a special identifier, it is determined that the result of the first instruction is only used once by the second instruction after the first instruction.

In a second possible implementation manner, with reference to the second aspect or the first implementation manner of the second aspect, the processor further includes:

The identification unit, in the decoding stage, identifies the first register as the storage register for the result of the first instruction, and at the same time only serves as the source operand of the second instruction, then it is determined that the result of the first instruction is only used by the first instruction Instructions following an instruction are used once, and the first instruction and the second instruction are specially identified.

In a third possible implementation manner, in combination with any one of the second implementation manners of the second aspect, the identification unit is specifically configured to:

The first register is replaced with a special register, and a special relationship mark is made between the first instruction and the second instruction.

In a fourth possible implementation manner, in combination with the second implementation manner of the second aspect, the judgment unit is specifically configured to:

A special bit is added after the first instruction and the second instruction to mark the relationship between the first instruction and the second instruction.

In a fifth possible implementation manner, in combination with the second aspect or any one of the first to fourth possible implementation manners of the second aspect, the transmitting unit is specifically configured to:

If the first instruction and the second instruction are two consecutive instructions, the result of the first instruction is directly passed to the second instruction through the forward path as the source operation of the second instruction number;

If the first instruction and the second instruction are two discontinuous instructions, after the execution of the first instruction, cache the result of the first instruction in the functional unit, when the second instruction When the second instruction is executed, the result of the first instruction is transferred to the second instruction as the source operand of the second instruction;

In a sixth possible implementation manner, with reference to the first aspect or the first to fifth possible implementation manners of the first aspect, the processor further includes:

The renaming unit is configured to not perform a renaming operation on the register where the result of the first instruction is located in the renaming stage if the result is only used once by a second instruction following the first instruction.

In a seventh possible implementation manner, in combination with the second aspect or any one of the first to sixth possible implementation manners of the second aspect, the processor further includes:

The notification unit is the same as notifying the reordering buffer after the execution of the first instruction is completed, so as to submit the first instruction according to the ordering rules in the reordering buffer; after the execution of the second instruction is completed Then write the result of the second instruction back to the register file, and notify the reordering buffer, so that the second instruction is submitted according to the ordering rules in the reordering buffer.

In an eighth possible implementation manner, in combination with the second aspect or any one of the first to seventh possible implementation manners of the second aspect, the processor further includes:

a submission unit, configured to submit the first instruction and the second instruction simultaneously after the execution of the first instruction and the second instruction is completed;

The exception processing unit is configured to re-execute the first instruction and the second instruction when an exception occurs in the execution of the first instruction and/or the second instruction.

An embodiment of the present invention provides a CPU instruction processing method and a processor. When the result of the first instruction is only used once by the second instruction after the first instruction, the intermediate results of the first instruction and the second instruction are not written back to the register. In the register renaming stage, the registers storing the intermediate results are not renamed, that is, the registers storing the intermediate results are not mapped to physical registers, thereby saving register resources and reducing the cost of reading and writing successors. power consumption required.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 is a first schematic flowchart of a CPU instruction processing method provided by an embodiment of the present invention;

FIG. 2 is a second schematic flow diagram of a CPU instruction processing method provided by an embodiment of the present invention;

FIG. 3 is a first schematic structural diagram of a processor provided by an embodiment of the present invention;

FIG. 4 is a second schematic structural diagram of a processor provided by an embodiment of the present invention;

FIG. 5 is a schematic structural diagram III of a processor provided by an embodiment of the present invention;

FIG. 6 is a fourth structural schematic diagram of a processor provided by an embodiment of the present invention;

FIG. 7 is a schematic structural diagram five of a processor provided by an embodiment of the present invention;

FIG. 8 is a schematic structural diagram of another processor provided by an embodiment of the present invention.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

An embodiment of the present invention provides a CPU instruction processing method, as shown in FIG. 1, the method includes:

101. Determine whether a result of a first instruction is only used once by a second instruction subsequent to the first instruction.

It should be noted that the relationship that the result of an instruction is only used once by the second instruction after the instruction refers to:

The source operand used when the intermediate result after an instruction is executed is executed as the second instruction after the instruction, and this relationship exists only once.

102. If the result is only used once by a second instruction following the first instruction, do not write the result of the first instruction back to the register file.

103. Send the first instruction and the second instruction to the functional unit for calculation, make the first instruction execute before the second instruction, and transfer the processing result of the first instruction to the second instruction as the The source operand for the second instruction.

An embodiment of the present invention provides a CPU instruction processing method. When the result of the first instruction is only used once by the second instruction after the first instruction, the intermediate results of the first instruction and the second instruction are not written back to the register file and are The register renaming stage does not rename the registers storing the intermediate results, that is, does not map the registers storing the intermediate results into physical registers, thereby saving register resources and reducing the cost of reading and writing the relay registers. power consumption.

In order to enable those skilled in the art to more clearly understand the technical solutions provided by the embodiments of the present invention, a CPU instruction processing method provided by the embodiments of the present invention will be described in detail below through specific embodiments, as shown in FIG. 2 , the Methods include:

201. The processor compiles the program code, and reads in instructions after the compilation is completed.

Specifically, it can be achieved by the following methods:

If there are program instructions that need to be executed, the processor reads the instructions through the instruction fetcher. If it is found that the intermediate results of the two instructions read are only used once, a special structure can be used when the compiler generates code. register R0 to store the intermediate results.

Exemplarily, if a program code is a[0]=b+c+d, generally the code generated by the compiler after compiling is as follows:

ADD R3, R1, R2

ADD R5, R3, R4

STD 0 (R6), R5

Among them, R1 stores the value of b, R2 stores the value of c, R4 stores the value of d, and R6 stores the address of a[0];

Suppose the first one is instruction A, and the second one is instruction B, where instruction A is executed before instruction B, and the execution result of instruction A is stored in register R3, and the source register of instruction B is also R3, that is, instruction A The intermediate result between instruction B and instruction B is only used once, then we can modify the compiler to store the intermediate result of instruction A and instruction B in the special structure register R0 to identify the two instructions with the above special relationship, The code generated after modifying the compiler is as follows:

ADD R0, R1, R2

ADD R5, R0, R4

STD 0 (R6), R5

Or add a flag bit to each instruction to mark the two instructions whose intermediate results are only used once. The code generated after compilation is as follows:

ADD R3, R1, R2 1

ADD R5, R3, R4 1

STD 0(R6), R5 0

When the flag bit is 1, it means that the two instructions have a relationship that the intermediate result is used once;

When the two instructions need to be executed, the processor reads the instruction A and the instruction B through the IF getter.

202. In the decoding stage, the processor judges whether the result of the first instruction is only used once by the second instruction following the first instruction, and if so, identifies the two instructions.

Specifically, it can be achieved by the following methods:

If in the decoding stage, the decoder finds that the first instruction uses the special register R0 as the result register, and the following second instruction uses the register R0 as the source operand, then the decoding stage will identify the first instruction and the second instruction. Two instructions and special identification for the two instructions;

Or, if the decoder finds that the flag bits of the first instruction and the second instruction are both 1, the two instructions are specially marked.

Exemplarily, if it is found that instruction A uses special register R0 as the result register, and at the same time a following instruction B uses the value in register R0 as the source operand, then the decoding stage will recognize that instruction A and instruction B have ' The relationship between the intermediate result is only used once', and the two instructions are specially identified;

Or if it is found that the flag bits of instruction A and instruction B are both 1, special identification is performed on instruction A and instruction B.

203. In the renaming stage, if the processor finds that two instructions have special marks, the register storing the intermediate result is not renamed, and the instruction flow information is sent to the reordering buffer and the issue queue.

Specifically, it can be achieved by the following methods:

When the instruction flow reaches the renaming stage, if two instructions are found to have special marks, the registers that store the intermediate results of the two instructions will not be renamed, that is, they will not be mapped as physical registers, but registers that store other information Need to be renamed and mapped to physical registers.

Exemplarily, when instruction A and instruction B go through the renaming stage, it is found that instruction A and instruction B have special marks, and if the intermediate results of instruction A and instruction B are stored in R0, the R0 register will not be renamed work, other registers will be renamed as usual, that is, the corresponding structural registers will be renamed as physical registers, if the intermediate results of instruction A and instruction B are stored in R3, the R3 register will not be renamed, and other registers will continue as usual Carry out the renaming work, that is, rename the corresponding structural registers to physical registers;

After the renaming work is completed, the instruction flow related information is sent to the reordering buffer and the issue queue, wherein the instruction flow information is the instruction information obtained after decoding. Including the source operand, the destination operand, the operation to be performed and the command information.

204. After the source operand of the instruction waiting in the issue queue is ready, the processor sends the instruction to the functional unit for calculation.

Specifically, it can be achieved by the following methods:

When the instruction is waiting in the emission queue, if the latest source operand has been saved in the register file or the latest value has been calculated by the functional unit, but it has not been written back to the register file, it indicates that the source operand of the instruction has been prepared Ready, send the instruction to the functional unit for operation.

Optionally, after calculation, the following steps may also be included:

205. If the result of the first instruction is only used once by the second instruction after the first instruction, when the result is calculated by the first instruction, the result is not sent to the register file, but is cached in the functional unit, waiting for the second instruction When the second instruction is executed, the result is used as a source operand.

Specifically, it can be achieved by the following methods:

For two instructions that only have a general relationship, the result after the calculation of the functional unit is directly written back to the register file and notified to the reordering buffer. When an instruction calculates a result, the result is not sent to the register file, but is cached in the functional unit, and when waiting for the second instruction to be executed, the result is used as a source operand;

If the two instructions are consecutive, the result of the first instruction execution can be directly passed to the second instruction through the forward path for calculation without caching, and the reordering buffer needs to be notified when the execution of the first instruction ends, when the second instruction At the end of execution, the result needs to be written back to the register file and the reorder buffer notified.

Exemplarily, for two instructions A and B whose intermediate results are used once, when the A instruction calculates the result, the result is not sent to the register file, but is cached in the functional unit, and when the B instruction is executed , as the source operand of the B instruction;

In fact, if instruction A and instruction B are continuous, the result of instruction A execution can be directly passed to instruction B for calculation through the forward path without caching. For instruction A, it needs to be notified after the calculation of the functional unit is completed. For the reordering buffer, after the execution of the B instruction is completed, the execution result of the B instruction needs to be written back to the register file, and the reordering buffer is notified.

206. If the result of the first instruction is only used once by the second instruction following the first instruction, the reordering buffer needs to be submitted simultaneously after both instructions are executed.

Specifically, it can be achieved by the following methods:

If the result of the first instruction is only used once by the second instruction after the first instruction, in order to avoid the situation that an exception suddenly occurs and enters the exception handler when the first instruction is executed, resulting in the loss of the result of the first instruction, the reorder buffer It is necessary to submit the first instruction and the second instruction when the execution of the second instruction is completed, that is, to ensure that they are submitted at the same time. , neither the first nor the second command can be submitted and needs to wait for re-execution.

Exemplarily, for the two instructions A and B, the reordering buffer needs to submit the A instruction and the B instruction only when the B instruction is completed, that is, in order to ensure simultaneous submission, so as to avoid a sudden exception when A is executed and enter exception processing When the program causes the result of instruction A to be lost, if an exception suddenly occurs when the execution of instruction A is completed and the execution of instruction B is not completed, then at this time, neither instruction A nor instruction B can be submitted, and it needs to wait for re-execution.

An embodiment of the present invention provides a CPU instruction processing method. When the result of the first instruction is only used once by the second instruction after the first instruction, the intermediate results of the first instruction and the second instruction are not written back to the register file and are The register renaming stage does not rename the registers storing the intermediate results, that is, does not map the registers storing the intermediate results into physical registers, thereby saving register resources and reducing the cost of reading and writing the relay registers. power consumption.

An embodiment of the present invention provides a processor 01. As shown in FIG. 3, the processor 01 includes:

Judging unit 011, configured to judge whether the result of the first instruction is only used once by the second instruction after the first instruction;

The execution unit 012 is used to not write the result of the first instruction back to the register file if the result is only used once by the second instruction after the first instruction; and execute the first instruction and the second instruction;

The sending unit 013 is used to send the first instruction and the second instruction to the functional unit for calculation, so that the first instruction is executed before the second instruction, and the processing result of the first instruction is passed to the second instruction as the second instruction. The source operand for the instruction.

Further, the judgment unit 011 is specifically used for:

In the decoding stage, it is identified whether the first instruction and the second instruction have a special identifier, and if there is a special identifier, it is determined that the result of the first instruction is only used once by the second instruction after the first instruction.

Further, as shown in Figure 4, the processor 01 also includes:

The identification unit 014, in the decoding stage, identifies the first register as the storage register for the result of the first instruction, and at the same time only serves as the source operand of the second instruction, then it is determined that the result of the first instruction is only used once by the instruction after the first instruction , make a special mark for the first instruction and the second instruction.

Furthermore, the execution unit 012 is specifically used for:

The first register is replaced with a special register, and a special relationship mark is made between the first instruction and the second instruction.

Furthermore, the identification unit 014 is specifically used for:

A special bit is added after the first instruction and the second instruction to mark the relationship between the first instruction and the second instruction.

Furthermore, the transmitting unit 013 is specifically used for:

If the first instruction and the second instruction are two consecutive instructions, the result of the first instruction is directly passed to the second instruction through the forward path as the source operand of the second instruction;

If the first instruction and the second instruction are two discontinuous instructions, after the first instruction is executed, the result of the first instruction is cached in the functional unit, and when the second instruction is executed, the result of the first instruction is passed to the second instruction as the source operand of the second instruction.

Optionally, as shown in Figure 5, the processor 01 further includes:

The renaming unit 015 is configured to not rename the register where the result of the first instruction is located in the renaming stage if the result is only used once by the second instruction after the first instruction.

Preferably, as shown in Figure 6, the processor 01 also includes:

The notification unit 016 is the same as notifying the reordering buffer after the execution of the first instruction is completed, so that the first instruction is submitted according to the ordering rules in the reordering buffer; after the execution of the second instruction is completed, the The result is written back to the register file, and the reorder buffer is notified, so that the second instruction is submitted according to the ordering rule in the reorder buffer.

Preferably, as shown in Figure 7, the processor 01 also includes:

Submitting unit 017, configured to submit the first instruction and the second instruction simultaneously after the execution of the first instruction and the second instruction is completed;

The exception processing unit 018 is configured to re-execute the first instruction and the second instruction when an exception occurs in the execution of the first instruction and/or the second instruction.

An embodiment of the present invention provides a processor. When the result of the first instruction is only used once by the second instruction after the first instruction, the intermediate results of the first instruction and the second instruction are not written back to the register file and are rewritten in the register. In the naming stage, the registers storing intermediate results are not renamed, that is, the registers storing intermediate results are not mapped to physical registers, thereby saving register resources and reducing the power consumption required for reading and writing relay registers.

An embodiment of the present invention provides a processor 02. As shown in FIG. 8, the processor 02 includes:

Instruction fetcher 021, decoder 022, renaming unit 023, emission queue 024, reordering buffer 025, register file 026, and functional unit 027, wherein the renaming unit 023 is connected to the emitting queue 024 and reordering buffer 025 , the register file 026 is connected to the reordering buffer 025 and the launch queue 024, the register file 026 and the launch queue 024 are connected to the functional unit 027, the functional unit 027 is connected to the reordering buffer 025 and the register file 026, and the instruction first passes through The instruction fetcher 021 reaches the decoder 022; wherein, the decoder 022 is used for:

Determine whether the result of the first instruction is only used once by the second instruction after the first instruction;

If the result is only used once by the second instruction following the first instruction, the result of the first instruction is not written back to the register file 026 .

Further, the emission queue 024 is used for:

Send the first instruction and the second instruction to the functional unit 027 for calculation, make the first instruction execute before the second instruction, and transfer the processing result of the first instruction to the second instruction as the source operand of the second instruction .

Furthermore, the decoder 022 is specifically used for:

In the decoding stage, it is identified whether the first instruction and the second instruction have a special identifier, and if there is a special identifier, it is determined that the result of the first instruction is only used once by the second instruction after the first instruction.

Furthermore, the decoder 022 is specifically used for:

In the decoding stage, the first register is identified as the storage register for the result of the first instruction, and at the same time it is only used as the source operand of the second instruction, then it is determined that the result of the first instruction is only used once by the instruction after the first instruction. Instructions and second instructions are specially marked.

Furthermore, the decoder 022 is specifically used for:

The first register is replaced with a special register, and a special relationship mark is made between the first instruction and the second instruction.

Furthermore, the decoder 022 is specifically used for:

A special bit is added after the first instruction and the second instruction to mark the relationship between the first instruction and the second instruction.

Furthermore, the emission queue 024 is specifically used for:

If the first instruction and the second instruction are two consecutive instructions, the result of the first instruction is directly passed to the second instruction through the forward path as the source operand of the second instruction;

If the first instruction and the second instruction are discontinuous two instructions, then after the first instruction is executed, the result of the first instruction is cached in the functional unit 027, and when the second instruction is executed, the result of the first instruction is Passed to the second instruction as the source operand of the second instruction.

Furthermore, the renaming component 023 is specifically used for:

If the result is only used once by the second instruction after the first instruction, no renaming operation is performed on the register where the result of the first instruction is located in the renaming stage.

Furthermore, the functional unit 027 is specifically used for:

After the execution of the first instruction is completed, the reordering buffer 025 is notified so that the first instruction is submitted according to the ordering rules in the reordering buffer 025; after the execution of the second instruction is completed, the result of the second instruction is written back to the register Heap 026, and notify the reorder buffer 025, so as to submit the second instruction according to the sorting rules in the reorder buffer 025.

Furthermore, the reordering buffer 025 is also used for:

After the execution of the first instruction and the second instruction is completed, submit the first instruction and the second instruction at the same time;

When an exception occurs in the execution of the first instruction and/or the second instruction, the first instruction and the second instruction are re-executed.

An embodiment of the present invention provides a processor. When the result of the first instruction is only used once by the second instruction after the first instruction, the intermediate results of the first instruction and the second instruction are not written back to the register file and are rewritten in the register. In the naming stage, the registers storing intermediate results are not renamed, that is, the registers storing intermediate results are not mapped to physical registers, thereby saving register resources and reducing the power consumption required for reading and writing relay registers.

In the several embodiments provided in this application, it should be understood that the disclosed method, device and system can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or May be integrated into another system, or some features may be ignored, or not implemented. In another point, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.

In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, each unit may be physically included separately, or two or more units may be integrated into one unit. The above-mentioned integrated units can be implemented in the form of hardware, or in the form of hardware plus software functional units.

The above-mentioned integrated units implemented in the form of software functional units may be stored in a computer-readable storage medium. The above-mentioned software functional units are stored in a storage medium, and include several instructions to enable a computer device (which may be a personal computer, server, or network device, etc.) to execute some steps of the methods described in various embodiments of the present invention. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), magnetic disk or optical disc, etc., which can store program codes. medium.

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. Should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (18)

1. A method for processing CPU instructions, characterized in that the method comprises: judging whether the result of the first instruction is only used once by a second instruction following the first instruction; If the result is only used once by a second instruction following the first instruction, the result of the first instruction is not written back to the register file; Sending the first instruction and the second instruction to the functional unit for calculation, so that the first instruction is executed before the second instruction, and the processing result of the first instruction is transferred to the second instruction as the second instruction The source operand for the instruction. 2. The method according to claim 1, wherein said judging whether the result of the first instruction is only used once by the instruction after the first instruction comprises: In the decoding stage, it is identified whether the first instruction and the second instruction have a special identifier, and if there is a special identifier, it is determined that the result of the first instruction is only used once by the second instruction following the first instruction. 3. The method according to claim 1 or 2, wherein the judging whether the result of the first instruction is only used once by the instruction after the first instruction further comprises: If the first register is used as the storage register for the result of the first instruction and is only used as the source operand of the second instruction, then it is determined that the result of the first instruction is only used once by the instruction after the first instruction , specifically identify the first instruction and the second instruction. 4. The method according to claim 3, wherein the special identification of the first instruction and the second instruction comprises: The first register is replaced with a special register, and a special relationship mark is made between the first instruction and the second instruction. 5. The method according to claim 3, wherein the special identification of the first instruction and the second instruction comprises: A special bit is added after the first instruction and the second instruction to mark the relationship between the first instruction and the second instruction. 6. The method according to any one of claims 1 to 5, wherein the first instruction and the second instruction are sent to the functional unit for calculation, so that the first instruction is executed prior to the second instruction, And passing the processing result of the first instruction to the second instruction includes: If the first instruction and the second instruction are two consecutive instructions, the result of the first instruction is directly passed to the second instruction through the forward path as the source operation of the second instruction number; If the first instruction and the second instruction are two discontinuous instructions, after the execution of the first instruction, cache the result of the first instruction in the functional unit, when the second instruction When the second instruction is executed, the result of the first instruction is transferred to the second instruction as a source operand of the second instruction. 7. according to the method described in any one in claim 1 to 6, it is characterized in that, described method also comprises: If the result is only used once by the second instruction after the first instruction, no renaming operation is performed on the register where the result of the first instruction is located in the renaming stage. 8. The method according to any one of claims 1 to 7, wherein the reordering buffer is notified after the execution of the first instruction is completed, so that the first instruction is sorted according to the reordering buffer The collation in the commit; After the execution of the second instruction is completed, the result of the second instruction is written back to the register file, and the reordering buffer is notified, so that the second instruction is submitted according to the ordering rules in the reordering buffer . 9. The method according to any one of claims 1 to 8, wherein the method further comprises: After the execution of the first instruction and the second instruction is completed, submit the first instruction and the second instruction at the same time; When an exception occurs in the execution of the first instruction and/or the second instruction, the first instruction and the second instruction are re-executed. 10. A processor, characterized in that, comprising: a judging unit, configured to judge whether the result of the first instruction is only used once by a second instruction following the first instruction; An execution unit configured to not write the result of the first instruction back to the register file if the result is only used once by a second instruction following the first instruction; and execute the first instruction and the second instruction; an issuing unit, configured to transmit the first instruction and the second instruction to the functional unit for calculation, so that the first instruction is executed prior to the second instruction, and the processing result of the first instruction is transferred to the second instruction, as the source operand for the second instruction. 11. The processor according to claim 10, wherein the judgment unit is specifically configured to: In the decoding stage, it is identified whether the first instruction and the second instruction have a special identifier, and if there is a special identifier, it is determined that the result of the first instruction is only used once by the second instruction following the first instruction. 12. The processor according to claim 10 or 11, further comprising: The identification unit, in the decoding stage, identifies the first register as the storage register for the result of the first instruction, and at the same time only serves as the source operand of the second instruction, then it is determined that the result of the first instruction is only used by the first instruction Instructions following an instruction are used once, and the first instruction and the second instruction are specially identified. 13. The processor according to claim 12, wherein the identification unit is specifically used for: The first register is replaced with a special register, and a special relationship mark is made between the first instruction and the second instruction. 14. The processor according to claim 12, wherein the identification unit is specifically used for: A special bit is added after the first instruction and the second instruction to mark the relationship between the first instruction and the second instruction. 15. The processor according to any one of claims 10 to 14, wherein the transmitting unit is specifically used for: If the first instruction and the second instruction are two consecutive instructions, the result of the first instruction is directly passed to the second instruction through the forward path as the source operation of the second instruction number; If the first instruction and the second instruction are two discontinuous instructions, after the execution of the first instruction, cache the result of the first instruction in the functional unit, when the second instruction When the second instruction is executed, the result of the first instruction is transferred to the second instruction as a source operand of the second instruction. 16. The processor according to any one of claims 10 to 15, further comprising: The renaming unit is configured to not perform a renaming operation on the register where the result of the first instruction is located in the renaming stage if the result is only used once by a second instruction after the first instruction. 17. The processor according to any one of claims 10 to 16, further comprising: a notification unit, configured to notify the reordering buffer after the execution of the first instruction is completed, so as to submit the first instruction according to the ordering rules in the reordering buffer; Then write the result of the second instruction back to the register file, and notify the reordering buffer, so that the second instruction is submitted according to the ordering rules in the reordering buffer. 18. The processor according to any one of claims 10 to 17, wherein the processor further comprises: a submission unit, configured to submit the first instruction and the second instruction simultaneously after the execution of the first instruction and the second instruction is completed; The exception processing unit is configured to re-execute the first instruction and the second instruction when an exception occurs in the execution of the first instruction and/or the second instruction.