CN104201114A - Packaging method and packaging structure of chip with sidewall in insulating protection - Google Patents

Abstract

The invention discloses a side wall insulation protection chip packaging method and a packaging structure thereof, belonging to the technical field of semiconductor packaging. The chip electrode (102) is embedded on the upper surface of the silicon base body (101), the metal bump (300) is located on the upper surface of the silicon base body (101) and connected to the chip electrode (102), and the insulating layer I (202) Set on the side wall of the silicon base body (101), it is formed by laser and _O2 or _N2 during the process of cutting the wafer (100), and the insulating layer II (210) is set on the silicon base body (101) For parts other than the metal bumps (300) on the surface, the back protection layer (400) is arranged on the lower surface of the silicon base body (101). The invention forms the insulating layer I (202) by laser on the side wall of the silicon base body (101), which effectively eliminates the phenomenon of tin creeping on the side wall, overcomes the leakage problem of chip size packaging, and improves the yield rate of the chip. The encapsulation method is simple and environmentally friendly, and the production cost is reduced.

Description

Chip packaging method and packaging structure with sidewall insulation protection

technical field

The invention relates to a chip packaging method for side wall insulation protection and a packaging structure thereof, belonging to the technical field of semiconductor packaging.

Background technique

In the existing wafer-level CSP (Chip Scale Package) packaging structure, the silicon around the chip is exposed in the assembly environment. During the placement and reflow process, the solder ball or electrode area is prone to partial soldering due to excessive printing of solder paste. Climb to the exposed silicon on the side wall of the chip, causing chip leakage; or due to the relatively close chip spacing, after heating or reflow, the side wall of the chip contacts the metal bumps of other chips, resulting in failure.

At the same time, for extremely small-sized packaged products, such as 0402, 0210, 01005-sized packaged products, as shown in the left figure of Figure 1, their own weight is very light. There is a difference in the amount and the uneven heating temperature of the reflow, resulting in an imbalance between the two ends of the electrode, which can easily cause one end of the chip to lift up, forming a "tombstone" phenomenon, as shown in the right picture of Figure 1, resulting in poor chip placement.

Contents of the invention

The object of the present invention is to overcome the disadvantages of the above-mentioned packaging structure, and provide a chip packaging method and a packaging structure that can improve chip mounting defects and prevent chip leakage and side wall insulation protection.

The purpose of the present invention is achieved like this :

A chip packaging method for sidewall insulation protection of the present invention, its technological process is as follows:

Step 1, providing a wafer with chip electrodes and scribe lanes;

Step 2. Put the laser knife and wafer in a closed space, start the laser knife, make it travel along the scribing path of the wafer, cut the wafer, form grooves, and provide O ₂ or N ₂ at the same time to form silicon on the groove wall Insulating layer I of oxide or silicon nitride;

Step 3: Deposit SiO ₂ /SiN on the surface of the wafer by PECVD to form an insulating layer II, and form an opening of the insulating layer II above the chip electrode by etching or etching, and the opening of the insulating layer II exposes the surface of the chip electrode ;

Step 4, forming a metal bump on the surface of the chip electrode through an electroless plating or electroplating process;

Step 5. Cover the wafer with a film and turn it up and down 180°;

Step 6. Thinning the back of the wafer through the grinding process;

Step 7. Paste the back protective layer on the back of the wafer through the film sticking process;

Step 8: Singularize the wafer by splitting and removing the film to form a chip packaging structure with a single sidewall insulation protection.

Optionally, the groove depth h is ≥30 μm.

Optionally, the depth h of the groove is 100-250 μm.

The chip packaging structure for sidewall insulation protection formed by the above chip packaging method for sidewall insulation protection includes a silicon base body, chip electrodes, insulating layer I, insulating layer II, metal bumps and a back protection layer, wherein the chip The electrodes are embedded in the upper surface of the silicon base body, the metal bumps are located on the upper surface of the silicon base body and connected to the chip electrodes, the insulating layer I is arranged on the side wall of the silicon base body, and the insulating layer II is arranged on the silicon base body For parts other than the metal bumps, the back protection layer is provided on the lower surface of the silicon base body.

Optionally, the thickness of the insulating layer I is 0.5-5 μm.

Another chip packaging method for sidewall insulation protection of the present invention has a process as follows:

Step 1, providing a wafer with chip electrodes and scribe lanes;

Step 2: Deposit SiO ₂ /SiN or coat polyimide on the surface of the wafer by PECVD to form an insulating layer II, and form an opening of the insulating layer II above the chip electrode by etching or etching, and the insulating layer Ⅱ The opening exposes the surface of the chip electrode;

Step 3, forming a metal bump on the surface of the chip electrode through an electroless plating or electroplating process;

Step 4: Cover the wafer with a film and turn it up and down 180°;

Step 5. Thinning the back of the wafer through the grinding process;

Step 6. Paste the back protective layer on the back of the wafer through the film sticking process.

Step 7. Place the laser knife and the wafer to be cut in a closed space, start the laser knife, make it travel along the scribing path of the wafer, and cut the wafer, and provide O ₂ or N ₂ at the same time to form silicon on the groove wall. Insulating layer I of oxide or silicon nitride;

Step 8: Singularize the wafer by splitting and removing the film to form a chip packaging structure with a single sidewall insulation protection.

Optionally, the remaining thickness h2 of the wafer is ≥30 μm.

Optionally, the remaining depth h2 of the wafer is 100-250 μm.

The chip packaging structure for sidewall insulation protection formed by the above chip packaging method for sidewall insulation protection includes a silicon base body, chip electrodes, insulating layer I, insulating layer II, metal bumps and a back protection layer, wherein the chip The electrodes are embedded in the upper surface of the silicon base body, the metal bumps are located on the upper surface of the silicon base body and connected to the chip electrodes, the insulating layer I is arranged on the side wall of the silicon base body, and the insulating layer II is arranged on the silicon base body For parts other than the metal bumps on the surface, the back protection layer is provided on the lower surface of the silicon base body.

Optionally, the thickness of the insulating layer I is 0.5-5 μm.

The beneficial effects of the present invention are:

1. The chip packaging structure of the side wall insulation protection of the present invention, which is provided with an insulating layer I of silicon oxide and/or silicon nitride on the side wall of the silicon base body, which eliminates the phenomenon of tin climbing on the side wall of the silicon base body, It overcomes the leakage problem of chip size packaging and improves the placement yield of chips;

2. The insulating layer I of silicon oxide or silicon nitride of the present invention is formed in the process of laser cutting the wafer, the manufacturing process is simple and environmentally friendly, and the production cost is reduced.

Description of drawings

FIG. 1 is a schematic diagram of the tin-climbing phenomenon of the existing chip packaging structure;

Fig. 2 is a process flow diagram of a chip packaging method for sidewall insulation protection of the present invention;

3 is a schematic cross-sectional view of Embodiment 1 of a chip packaging structure with sidewall insulation protection according to the present invention;

4 to 12 are schematic diagrams of the process of the packaging method of Embodiment 1;

FIG. 13 is a schematic cross-sectional view of a modification of Embodiment 1 of a sidewall insulation-protected chip packaging structure of the present invention;

14 is another process flow chart of a chip packaging method for sidewall insulation protection according to the present invention;

15 is a schematic cross-sectional view of Embodiment 2 of a chip packaging structure with sidewall insulation protection according to the present invention;

16 to 21 are schematic diagrams of the process of the packaging method of the second embodiment;

Among them, the silicon base body 101

chip electrode 102

Insulation layer Ⅰ 202

Insulation layer Ⅱ 210

Insulation layer II opening 211

Metal bump 300

Back protection layer 400;

Wafer 100

chip 11

Dicing Lane 12

Groove 103

Film 500

Laser Knife 600.

Detailed ways

The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown so that this disclosure will fully convey the scope of the invention to those skilled in the art. However, this invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

Option One

Referring to Fig. 2, a chip packaging method for sidewall insulation protection of the present invention, the process flow is as follows:

Executing step S101: providing a wafer with a chip electrode array;

Execute step S102: Open a groove along the scribing lane of the wafer with a laser, and at the same time form an insulating layer I on the groove wall;

Executing step S103: forming an insulating layer II and metal bumps connected to the chip electrodes on the surface of the wafer;

Executing step S104: thinning the back of the wafer and covering it with a film;

Executing step S105: splitting to form a single chip packaging structure with sidewall insulation protection.

Using the above-mentioned process method, the first embodiment of the chip package structure of the single chip sidewall insulation protection of the present invention is formed, as follows:

As shown in FIG. 3 , a sidewall insulation-protected chip packaging structure includes a silicon base body 101 , chip electrodes 102 , insulating layer I 202 , insulating layer II 210 , metal bumps 300 and a back protection layer 400 . Wherein, the chip electrode 102 is embedded in the upper surface of the silicon base body 101, and the metal bump 300 is located on the upper surface of the silicon base body 101 and connected with the chip electrode 102. Generally, the metal bump 300 has excellent electrical conductivity, thermal conductivity and reliability. Copper pillars, pure tin pillars, tin-silver alloy pillars or multi-layer metal pillars such as Ni/Pd, Ni/Au, Ni/Pd/Au. The metal bump 300 is in the shape of a block, and may also be in the shape of a column. There may also be a metal anti-oxidation layer made of solder on the top of the metal bump 300 . The insulating layer I202 is arranged on the sidewall of the silicon base body 101, and is made of silicon oxide or silicon nitride, and generally has a thickness of 0.5-5 μm, which avoids the exposure of the side wall of the silicon base body 101 and can effectively eliminate tin creeping Phenomenon, reducing the damage of the chip during installation and use, and improving the placement yield of the chip. The insulating layer II 210 is disposed on the silicon substrate 101 other than the metal bump 300 . The back protection layer 400 is disposed on the lower surface of the silicon base body 101 , and its thickness is 5-40um. In use, the metal bump 300 of the present invention is flip-chip mounted on the substrate, and fixedly connected to the substrate through a reflow process; or the chip is fixed on the lead frame through a wire bonding process.

The technological process of above-mentioned embodiment one is as follows:

Step 1: Provide a wafer 100 with a chip electrode array, as shown in Figure 4 and Figure 5, which can form tens of thousands of chips 11, and there are usually dicing lanes 12 with a spacing of 40 μm to 100 μm between adjacent chips 11 , the silicon base body 101 is formed after the wafer 100 is cut into monomers. 4 is a front view of the wafer, and FIG. 5 is a partially enlarged cross-sectional view of the wafer passing through one row of chip electrodes.

Step 2. Place the laser knife 600 and the wafer 100 to be cut in a closed space. As shown in FIG. For the tall groove 103, the depth h of the groove 103 is ≥ 30 μm, preferably the depth h is 100-250 μm. Because the laser knife 600 does not cut through the wafer 100 , it provides support for subsequent processes.

When laser cutting the wafer 100, the laser equipment used can be an infrared laser with a laser wavelength of 1064nm. The laser beam emitted by the laser is focused by a lens and converged into a very small spot at the focal point. The spot size can be as small as 30-80 μm , the laser power density focused at the spot is as high as 10 ⁹ -10 ¹² W/mm ² . The silicon material at its focal point is irradiated by a high-power-density laser spot, which will generate a local high temperature above 10,000°C, making it vaporized instantly and blown away by the airflow to form a groove 103. At the same time, the silicon material at the edge of the focal point and The surrounding _O2 or _N2 reacts to form an insulating layer I202 attached to the wall of the trench 103 and composed of silicon oxide or silicon nitride. The thickness of the insulating layer I202 is 0.5-5 μm, which has the function of insulation protection .

Step 3: Deposit SiO ₂ /SiN on the surface of the wafer 100 by PECVD to form an insulating layer II 210, and form an insulating layer II opening 211 above the chip electrode 102 by etching or etching, and the insulating layer II opening 211 is exposed The surface of the chip electrode 102 is shown in FIG. 7 .

Step 4, forming a metal bump 300 on the surface of the chip electrode 102 through an electroless plating or electroplating process, as shown in FIG. 8 . the

Step 5: Cover the wafer 100 with a film 500, which is generally a UV film, and turn it upside down by 180°, as shown in FIG. 9 .

Step 6: Thinning the back of the wafer 100 through a grinding process, and the thickness of the thinning is determined according to actual needs. It can be thinned to the remaining thickness h1 of the bottom of the trench 103, can also be thinned to expose the bottom of the trench 103, and can also be thinned to remove the remaining thickness of the trench 103 and the insulating layer I202 and insulating layer II210 in the trench 103 thickness, as shown in Figure 10.

Step 7. Paste the back protective layer 400 on the back of the wafer 100 through the film sticking process to enhance the strength of the packaging structure, as shown in FIG. 11 .

Step 8: Divide the wafer 100 into individual pieces by splitting and removing the film 500 to form a single chip packaging structure with sidewall insulation protection, as shown in FIG. 12 .

Due to the different thinning thicknesses of the back side of the wafer 100, it is possible to form chip packaging structures with various sizes and thicknesses and slightly different packaging structures with sidewall insulation protection. As shown in FIG. 13 , the thickness of the silicon base body 101 is thinner. The insulating layer II 210 can also extend to the outside of the insulating layer I 202 .

Option II

Referring to Fig. 14, a chip packaging method for sidewall insulation protection according to the present invention, the process flow is as follows:

Executing step S101: providing a wafer with a chip electrode array;

Executing step S102: forming an insulating layer II and metal bumps connected to the chip electrodes on the surface of the wafer;

Executing step S103: thinning the back of the wafer and covering it with a film;

Execute step S104: Open a groove along the scribing lane of the wafer with a laser, and at the same time form an insulating layer I on the groove wall;

Executing step S105: splitting to form a single chip packaging structure with sidewall insulation protection.

Using the above process method, the second embodiment of the chip package structure of the single chip sidewall insulation protection of the present invention is formed, as follows:

As shown in Figure 15, a chip packaging structure with sidewall insulation protection includes a silicon base body 101, a chip electrode 102, an insulating layer I202, an insulating layer II210, a metal bump 300 and a back protection layer 400, wherein the chip electrode 102 is embedded in the upper surface of the silicon base body 101 , and the metal bump 300 is located on the upper surface of the silicon base body 101 and connected to the chip electrode 102 . The insulating layer I 202 is disposed on the sidewall of the silicon base body 101 and is made of silicon oxide or silicon nitride, generally with a thickness of 0.5-5 μm, which can effectively eliminate the phenomenon of tin creeping and improve the placement yield of chips. The insulating layer II 210 is disposed on the upper surface of the silicon base body 101 other than the metal bump 300 , and the back protection layer 400 is disposed on the lower surface of the silicon base body 101 .

The technological process of above-mentioned embodiment two is as follows:

Step 1, providing a wafer 100 with a chip electrode array, as shown in FIG. 16 .

Step 2: Deposit SiO ₂ /SiN or coat polyimide on the surface of the wafer 100 by PECVD to form an insulating layer II 210, and form an insulating layer II opening 211 above the chip electrode 102 by etching or etching , the insulating layer II opening 211 exposes the surface of the chip electrode 102 , as shown in FIG. 17 .

Step 3, forming a metal bump 300 on the surface of the chip electrode 102 through an electroless plating or electroplating process, as shown in FIG. 18 .

Step 4: Cover the wafer 100 with a film 500, the film 500 is generally a UV film, and turn it upside down by 180°, as shown in FIG. 19 .

Step 5. Thinning the backside of the wafer 100 through the grinding process, so that the remaining thickness h2 of the wafer 100 is ≥ 30 μm, preferably the depth h2 is 100-250 μm, as shown in FIG. 19 .

Step 6: Paste the back protective layer 400 on the back of the wafer 100 through the film sticking process, as shown in FIG. 20 .

Step 7. Place the laser knife 600 and the wafer 100 to be cut in a closed space, start the laser knife 600, make it travel along the scribing path 12 of the wafer 100, and cut the wafer 100, as shown in FIG. 20 , and provide O ₂ or N ₂ , an insulating layer I 202 with a thickness of 0.5-5 μm and made of silicon oxide or silicon nitride is formed on the wall of the trench 103 for insulation protection.

Step 8: Divide and remove the film 500 to singulate the wafer 100 , as shown in FIG. 21 .

A chip packaging method and its packaging structure for sidewall insulation protection of the present invention are not limited to the above-mentioned preferred embodiments. For example, when laser cutting the wafer 100, it can also be carried out in the air, and the material of the formed insulating layer I202 is silicon oxide. The mixture of silicon nitride and silicon nitride also plays the role of insulation protection. Or when laser cutting the wafer 100 , provide other gas or liquid that is easy to react with the silicon substance to form an insulating protective layer.

In addition, in addition to laser, other high-speed cutting methods or chemical etching methods can also form side insulation protection layers when processing wafers.

Therefore, without departing from the spirit and scope of the present invention, any modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention all fall within the scope of protection defined by the claims of the present invention. .

Claims (10)

1. A chip packaging method for sidewall insulation protection, its technological process is as follows: Step 1, providing a wafer (100) with chip electrodes (102) and dicing lanes (12); Step 2. Place the laser knife (600) and the wafer (100) in a closed space, start the laser knife (600), and make it travel along the scribing path (12) of the wafer (100) to cut the wafer (100), Forming a trench (103), while providing _O2 or _N2 , forming an insulating layer I (202) of silicon oxide or silicon nitride on the wall of the trench (103); Step 3: Deposit SiO ₂ /SiN on the surface of the wafer (100) by PECVD to form an insulating layer II (210), and form an opening of the insulating layer II ( 211), the insulating layer II opening (211) exposes the surface of the chip electrode (102); Step 4, forming a metal bump (300) on the surface of the chip electrode (102) through an electroless plating or electroplating process; Step 5. Cover the wafer (100) with a film (500), and turn it up and down 180°; Step 6. Thinning the back of the wafer (100) through a grinding process; Step 7. Paste the back protective layer (400) on the back of the wafer (100) through the film sticking process; Step 8: Dividing and removing the film (500) to singulate the wafer (100) to form a single chip packaging structure with sidewall insulation protection. 2. The chip packaging method according to claim 1 or 2, characterized in that: the depth h of the groove (103) is ≥ 30 μm. 3. The chip packaging method according to claim 2, characterized in that: the depth h of the groove (103) is 100-250 μm. 4. The chip packaging method according to claim 1, characterized in that: the side wall insulation protected chip packaging structure includes a silicon base body (101), chip electrodes (102), insulating layer I (202), Insulation layer II (210), metal bumps (300) and back protection layer (400), wherein chip electrodes (102) are embedded on the upper surface of the silicon base body (101), and the metal bumps (300) are located on the silicon base body ( 101) and connected to the chip electrode (102), the insulating layer I (202) is set on the sidewall of the silicon base body (101), and the insulating layer II (210) is set on the silicon base body (101) On the part other than the metal bump (300), the back protection layer (400) is arranged on the lower surface of the silicon base body (101). 5. The chip packaging method according to claim 1 or 4, characterized in that: the thickness of the insulating layer I (202) is 0.5-5 μm. 6. A chip packaging method for sidewall insulation protection, its technological process is as follows: Step 1, providing a wafer (100) with chip electrodes (102) and dicing lanes (12); Step 2: Deposit SiO ₂ /SiN or coat polyimide on the surface of the wafer (100) by PECVD to form an insulating layer II (210), and etch or etch the chip electrode (102) The method forms an insulating layer II opening (211), and the insulating layer II opening (211) exposes the surface of the chip electrode (102); Step 3, forming a metal bump (300) on the surface of the chip electrode (102) through an electroless plating or electroplating process; Step 4: Cover the wafer (100) with a film (500), and turn it up and down 180°; Step 5. Thinning the back of the wafer (100) through a grinding process; Step 6. Paste the back protective layer (400) on the back of the wafer (100) through the film sticking process, Step 7. Place the laser knife (600) and the wafer (100) to be cut in a closed space, start the laser knife (600), and make it travel along the scribing path (12) of the wafer (100) to cut the wafer ( 100), while providing _O2 or _N2 , forming an insulating layer I (202) of silicon oxide or silicon nitride on the wall of the trench (103); Step 8: Dividing and removing the film (500) to singulate the wafer (100) to form a single chip packaging structure with sidewall insulation protection. 7. The chip packaging method according to claim 6, characterized in that: the remaining thickness h2 of the wafer (100) is ≥30 μm. 8. The chip packaging method according to claim 7, characterized in that: the remaining depth h2 of the wafer (100) is 100-250 μm. 9. The chip packaging method according to claim 6, characterized in that: the chip packaging structure with side wall insulation protection includes a silicon base body (101), chip electrodes (102), insulating layer I (202), Insulation layer II (210), metal bumps (300) and back protection layer (400), wherein chip electrodes (102) are embedded on the upper surface of the silicon base body (101), and the metal bumps (300) are located on the silicon base body ( 101) and connected to the chip electrode (102), the insulating layer I (202) is set on the sidewall of the silicon base body (101), and the insulating layer II (210) is set on the silicon base body (101) For parts other than the metal bumps (300) on the upper surface, the back protection layer (400) is arranged on the lower surface of the silicon base body (101). 10. The chip packaging method according to claim 6 or 9, characterized in that: the thickness of the insulating layer I (202) is 0.5-5 μm.