CN104200178B - A kind of double method driving logical system and opposing power analysis along triggering - Google Patents

Abstract

The invention discloses a double-edge trigger drive logic system and a method for resisting energy analysis attacks, including a signal source, a control unit, a drive logic circuit and a drive logic compensation circuit, and the system replaces the standard signal source and the drive logic circuit. , while improving security, the control unit generates a reset signal with a length of half a clock cycle, thereby compressing two clock cycles for outputting a set of data into one clock cycle, so as not to reduce the work of the entire chip hardware device efficiency.

Description

A dual-edge trigger-driven logic system and a method for resisting energy analysis attacks

technical field

The invention relates to the field of computer security, in particular to a double-edge trigger driving logic system and a method for resisting energy analysis attacks.

Background technique

At present, with the advancement of science and technology, various chip hardware devices have been widely used due to their small size, fast computing speed, diverse shapes, applicable to various e-commerce scenarios and long service life. market prospects.

With the wide application of chip hardware devices, its side channel security issues are gradually exposed. Through the analysis of chip energy consumption, the information processed by the chip can be detected, which leads to information leakage accidents.

In information theory, the Hamming distance (HD) between two equal-length bit strings is the number of different bits in the corresponding positions of the two bit strings; The Hamming distance of the string, that is, the number of non-zero bits in the bit string. For the driving logic circuit used in the chip hardware device, the HW value of a clock cycle represents the number of 1s in the bit string output by the driving logic circuit in the clock cycle as the calculation result; two adjacent clock cycles The HD value of represents the number of different bit values (0 or 1) in the corresponding positions of the two bit strings output by the driving logic circuit in the two clock cycles as the calculation results. According to the energy analysis theory, in the working state, if the HW and HD values of the driving logic circuit are not constant, the energy consumption of the driving logic circuit will also change, and the energy analysis attack technology can be used to restore the calculated value of the chip hardware device. information.

Therefore, it is necessary to provide specific protection for the driving logic circuit in the chip hardware device, so that it has the ability to resist energy analysis attacks, and the specific implementation method is as follows.

On the chip hardware devices, a specific anti-energy analysis attack is used to drive the logic system, such as the drive logic system implemented with a double-gate precharge structure (DPL). This drive logic system is composed of two groups of drive logic circuits with the same function. When a clock cycle starts and data is input into the driving logic circuit group, the input data is stored in the first group of driving logic circuits, and the input data is reversed and then input to the second group of driving logic circuits; when the next clock cycle starts, the Two sets of driving logic circuits are set to zero.

Although the above method can prevent the information calculated in the driving logic circuit from leaking through the energy analysis method to a certain extent, this method also has certain problems in practical applications. For example, the standard driving logic circuit will output a set of data every clock cycle , and the DPL drive logic circuit must output a set of data every two clock cycles, which reduces the throughput rate of the entire chip hardware device by 50%. As shown in Figure 7, the timing diagram of the DPL structure-driven logic system is assigned the sequence "1,0,0,1,1". Although the DPL structure-driven logic system also has the ability to resist energy analysis attacks, it requires two It takes only one clock cycle to output one value in the sequence, that is, it takes 10 clock cycles to output all five sequence values, as shown in Figure 7. This approach results in half the throughput rate of the driving logic system and even the entire chip hardware device.

Contents of the invention

In view of this, the main purpose of the present invention is to provide a dual-edge trigger driving logic system and a method for resisting energy analysis attacks, so as to maintain the ability to resist energy analysis attacks without reducing the throughput rate of chip hardware devices and improving work efficiency. , improving security.

To achieve the above object, the present invention provides a dual-edge trigger drive logic system, including a signal source, a control unit, a drive logic circuit and a drive logic compensation circuit;

The control unit is used to receive an external reset signal and a clock signal, and when the external reset signal is valid, the signal source, the driving logic circuit and the driving logic compensation circuit are in a reset state; when the external reset signal is invalid and the clock signal is a rising edge , the signal source, the drive logic circuit and the drive logic compensation circuit are in the working state, and when the external reset signal is invalid and the clock signal is a falling edge, the signal source, the drive logic circuit and the drive logic compensation circuit are in the reset state;

The signal source is used to provide a first input signal to the driving logic circuit and a second input signal to the driving logic compensation circuit when it is in an operating state, and the first input signal is complementary to the second input signal ;

The drive logic circuit is used to receive the first input signal, and calculate and generate the first output signal according to the first input signal; the drive logic compensation circuit is used to receive the second input signal, and calculate and generate the first output signal according to the second input signal The input signal is calculated to generate a second output signal; the first output signal is complementary to the second output signal.

Further, the control unit includes an external clock signal input terminal CLK, an external reset signal input terminal RST, a low level terminal, a clock signal output terminal Work, a reset signal output terminal PreC, and a NOR gate, first, second, third or Door;

Wherein, the external clock signal input terminal CLK and the low level terminal are respectively connected to the input terminal of the NOR gate and the input terminal of the first OR gate OR1; the output terminal of the NOR gate and the external reset signal input terminal RST are connected to the second OR gate OR2 the input terminal of the first OR gate OR1; the output terminal of the first OR gate OR1 is connected to the input terminal of the third OR gate OR3; the output terminal of the second OR gate OR2 is connected to the reset signal output terminal PreC; the first OR gate OR2 is connected to the output terminal PreC of the reset signal; The output end of the three-OR gate OR3 is connected to the clock signal output end Work.

Further, the signal source includes a first signal source for generating the first input signal and a second signal source for generating the second input signal;

The first signal source includes a first reset signal receiving terminal RST1, a first clock signal receiving terminal CLK1 and a first input signal output terminal LS, the first reset signal receiving terminal RST1 is connected to the reset signal output terminal PreC, The first clock signal receiving end CLK1 is connected to the clock signal output end Work;

The second signal source includes a second reset signal receiving terminal RST2, a second clock signal receiving terminal CLK2 and a second input signal output terminal CLS, the second reset signal receiving terminal RST2 is connected to the reset signal output terminal PreC, The second clock signal receiving end CLK2 is connected to the clock signal output end Work.

Further, the driving logic circuit includes a first input signal receiving terminal LCin, a third reset signal receiving terminal RST3 and a driving logic circuit output terminal LCout; the driving logic compensation circuit includes a second input signal receiving terminal CLCin, a fourth reset signal receiving terminal The receiving end RST4 and the driving logic circuit output end CLCout;

The first input signal receiving end LCin is connected to the first input signal output end LS; the second signal input signal receiving end CLCin is connected to the second input signal output end CLS; the third reset signal receiving Terminal RST3 is connected to the reset signal output terminal PreC; the fourth reset signal receiving terminal RST4 is connected to the reset signal output terminal PreC.

Further, when the driving logic circuit is an exclusive OR gate circuit, the driving logic compensation circuit is an exclusive NOR gate circuit.

Further, when the driving logic circuit is a NOT gate circuit, the driving logic compensation circuit is a NOT gate circuit.

Further, when the driving logic circuit is an AND gate circuit, the driving logic compensation circuit is a NAND gate circuit.

Further, when the driving logic circuit is an OR gate circuit, the driving logic compensation circuit is a NOR gate circuit.

The present invention also provides a method for resisting energy analysis attacks based on the above system, which is characterized in that it includes:

When the external reset signal is valid, the control unit sends a valid reset signal to the signal source, the driving logic circuit and the driving logic compensation circuit;

When the external reset signal is invalid, when the clock signal is a rising edge, the control unit sends the clock signal and an invalid reset signal to the signal source, the driving logic circuit and the driving logic compensation circuit; The driving logic compensation circuit provides a second input signal, the first input signal is complementary to the second input signal; the driving logic circuit receives the first input signal, and generates a first output signal according to the first input signal ; The driving logic compensation circuit receives a second input signal, and calculates and generates a second output signal according to the second input signal; the first output signal is complementary to the second output signal;

When the external reset signal is invalid, the control unit sends a clock signal and an effective reset signal to the signal source, the driving logic circuit and the driving logic compensation circuit when the clock signal is at a falling edge.

Using the dual-edge trigger driving logic system provided by the present invention to replace the standard signal source and driving logic circuit, while providing the ability of the driving logic circuit to resist energy analysis attacks, the control unit generates a reset signal with a length of half a clock cycle , so that the two clock cycles for outputting a set of data are compressed into one clock cycle, so that the throughput rate of the entire chip hardware device will not be reduced.

Description of drawings

Fig. 1 is a schematic structural diagram of a dual-edge trigger drive logic system of the present invention;

Fig. 2 is the structural representation of the control unit of the double-edge trigger driving logic system of the present invention;

FIG. 3 is a schematic diagram of the timing sequence of each pin of the control unit in FIG. 2;

4 is a schematic diagram of the corresponding relationship between the driving logic circuit and the driving logic compensation circuit in the double-edge trigger driving logic system of the present invention;

FIG. 5 is a schematic diagram of a timing sequence of a standard drive logic input;

Fig. 6 is a timing schematic diagram of the input of the driving logic circuit and the input of the driving logic compensation circuit of the double-edge trigger driving logic system of the present invention;

FIG. 7 is a timing diagram of a DPL driving logic circuit in the prior art.

detailed description

In order to make the purpose, technical solution and advantages of the present invention more clear, the present invention will be further described in detail below with reference to the accompanying drawings and examples.

The invention provides a double-edge trigger drive logic system, including a signal source, a control unit, a drive logic circuit and a drive logic compensation circuit;

The control unit is used to receive an external reset signal and a clock signal, and when the external reset signal is valid, the signal source, the driving logic circuit and the driving logic compensation circuit are in a reset state; when the external reset signal is invalid and the clock signal is a rising edge , the signal source, the drive logic circuit and the drive logic compensation circuit are in the working state, and when the external reset signal is invalid and the clock signal is a falling edge, the signal source, the drive logic circuit and the drive logic compensation circuit are in the reset state;

The signal source is used to provide a first input signal to the driving logic circuit and a second input signal to the driving logic compensation circuit when it is in an operating state, and the first input signal is complementary to the second input signal ;

The drive logic circuit is used to receive the first input signal, and calculate and generate the first output signal according to the first input signal; the drive logic compensation circuit is used to receive the second input signal, and calculate and generate the first output signal according to the second input signal The input signal is calculated to generate a second output signal; the first output signal is complementary to the second output signal.

As a typical embodiment of the present invention, with reference to accompanying drawings 1 and 2, the double-edge trigger driving logic system provided by the present invention includes a signal source, a control unit, a driving logic circuit and a driving logic compensation circuit;

As shown in Figure 2, the control unit includes an external clock signal input terminal CLK, an external reset signal input terminal RST, a low level terminal, a clock signal output terminal Work, a reset signal output terminal PreC, and NOR gates, first, second, second Three OR gate;

The external clock signal input terminal CLK and the low level terminal are respectively connected to the input terminal of the NOR gate and the input terminal of the first OR gate OR1; the output terminal of the NOR gate and the external reset signal input terminal RST are connected to the input of the second OR gate OR2 terminal; the output terminal of the first OR gate OR1 is connected to the third OR gate OR3 with the low level terminal; the output terminal of the second OR gate OR2 is connected to the reset signal output terminal PreC; the output terminal of the third OR gate OR3 The output terminal is connected to the clock signal output terminal Work.

It should be noted that, as shown in FIG. 1, the first input signal output by the first signal source is the inversion of the second input signal output by the second signal source. Therefore, in the working state, there is In the reset state, there is LC _in =CLC _in ={0,0,...,0}, wherein, the number of bits of the first input signal and the second input signal can be determined according to the number of signal bits required by the driving logic circuit, and the driving The number of bits of the input signal of the logic circuit is the same as the number of bits of the input signal of the drive logic compensation circuit, therefore, assuming that the number of bits of the first and second input signals are both n, then LC _in ={LS ₁ ,LS ₂ ,. ..,LS _n }, CLC _in ={CLS ₁ ,CLS ₂ ,...,CLS _n }; the output LC _out of the driving logic circuit is the input LC _in of the driving logic circuit and is calculated by the function executed by the driving logic circuit The result, the output CLC _out of the driving logic compensation circuit is the result calculated by the input CLC _in of the driving logic compensation circuit through the function performed by the driving logic compensation circuit, and the output CLC _out of the driving logic compensation circuit is the driving logic circuit in the working state The output of LC _out is reversed, and the output of the driving logic compensation circuit and the output of the driving logic circuit are both set to zero in the reset state. Note that the driving logic circuit executes the Boolean function F ₁ , the driving logic compensation circuit executes the Boolean function F ₂ , and the driving logic circuit The output of the drive logic compensation circuit is LC _out , and the input of the driving logic compensation circuit is CLC _out , then LC _out = F ₁ (LC _in ) = F ₁ (LS ₁ ,LS ₂ ,...,LS _n ), CLC _out =F ₂ ( CLC _in )＝F ₂ (CLS ₁ ,CLS ₂ ,...,CLS _n ), there is There is LC _out =CLC _out in the reset state; the external clock signal CLK and the reset signal RST received by the control unit are respectively the clock signal and the reset signal of the drive logic circuit system, and the working signals Work produced by the control unit are respectively the first, The clock signal of the second signal source and the reset signal PreC produced by the control unit are respectively the reset signals of the first signal source, the second signal source, the driving logic circuit and the driving logic compensation circuit; as can be seen from the above structure, the driving logic circuit system The connection mode connected to the whole circuit is exactly the same as the original standard drive logic circuit, so it can meet the requirements of the standard circuit component library when used, and can be normally connected with the chip hardware device circuit, and has good compatibility.

In the following, the drive logic system with the first and second input signals being 1 bit is taken as an example, assuming that the reset signal is active at a high level, referring to the accompanying drawings 3 to 6, the working process of the drive logic system in the above-mentioned embodiment of the present invention is further detailed illustrate.

FIG. 3 is a schematic diagram of the timing of each pin in five clock cycles generated by the control unit. As can be seen:

A. When the first clock cycle, RST is high level, that is, the drive logic system is in the reset state at this time, and PreC is high level, that is, all signal sources, drive logic circuits, and drive logic compensation circuits are in the reset stage .

B. When the 2nd to 5th clock cycle, RST is low level, that is, the driving logic system is in the working stage at this time, and each signal source in the system, the driving logic circuit, and the driving logic compensation circuit are in the stage, including :

B1. On the rising edge of each clock cycle, Work is a rising edge, PreC is a low level, and the first signal source, the second signal source, the driving logic circuit and the driving logic compensation circuit enter the working stage;

B2. On the falling edge of each clock cycle, PreC is at a high level, and the first signal source, the second signal source, the driving logic circuit and the driving logic compensation circuit enter a reset phase.

To sum up, the stage entered by the first and second signal sources, the driving logic circuit, and the driving logic compensation circuit conforms to the definition of the CLK pin and the RST pin of the double-edge trigger driving logic system.

It can also be found from FIG. 3 that when the double-edge trigger driving logic system is in the working phase, the PreC signal is the inversion of the corresponding Work signal, and the Work signal is the same as the CLK signal of the double-edge trigger driving logic system, so Only knowing the CLK signal of the double-edge trigger driving logic system can calculate the stages of each signal source, driving logic circuit, and driving logic compensation circuit in the double-edge trigger driving logic system. All CLKs in the following are Indicates the CLK signal of the double-edge trigger driving logic system.

Since the driving logic circuit is a circuit component that realizes the circuit signal calculation function, the driving logic circuit can be abstracted as a Boolean function, denoted as F, the function input is LC _in , and the function output is LC _out , then the driving logic can be defined as LC _out = F(LC _in ). Therefore, when discussing the driving logic circuit later in this article, since the output is a function of the input, only the input of the driving logic circuit needs to be discussed.

In information theory, the Hamming distance (HD) between two equal-length bit strings is the number of different bits in the corresponding positions of the two bit strings; The Hamming distance of the string, that is, the number of non-zero bits in the bit string. For the driving logic used in the chip hardware device, the HW value of a clock cycle represents the number of 1s in the bit string calculated by the driving logic in this clock cycle; the HD value of two adjacent clock cycles represents the number of 1s in the drive logic The number of different bit values (0 or 1) at the corresponding positions of the two bit strings calculated by the logic in the two clock cycles. According to the energy analysis theory, in the working state, if the HW and HD values of the standard driving logic are not constant, the energy consumption of the driving logic will also change, and the standard driving logic and even chip hardware devices can be recovered through energy analysis attack technology The information calculated and stored in the

According to the definition and wiring of the driving logic system, it can be found that the input and output values of the driving logic circuit and the driving logic compensation circuit are complementary. Note that the abstract Boolean function of the driving logic circuit is F ₁ , the function input is LC _in , and the function output is LC _out , the abstract Boolean function of the compensation drive logic circuit is F ₂ , the function input is CLC _in , and the function output is CLC _out , then It can be seen that when discussing the HW value and HD value of the driving logic system, it is equivalent to consider the input or output of the driving logic system. Therefore, only the inputs driving the logic system are considered in the remainder of this paper.

FIG. 4 is a schematic diagram of the design of the driving logic compensation circuit of the driving logic system of the present invention. The drive logic system is the same as the standard drive logic, and is composed of standard logic elements. The most basic three types of standard logic elements are 1-input NOT gate (NOT), 2-input AND gate (AND), and 2-input OR gate (OR). Since other complex circuits are composed of these three types of standard logic elements, when the drive logic compensation circuit design of these three types of standard logic elements is obtained, the drive logic compensation circuit design corresponding to the complex drive logic circuit can be obtained. For NOT, the truth table is constructed according to the input and output, and it can be found that the corresponding driving logic circuit is NOT. For AND and OR, the logic can be simplified according to the 2-input Karnaugh map, and then it is found that the driving logic compensation circuit corresponding to AND is OR, and the driving logic compensation circuit corresponding to OR is AND, as shown in Figure 4. Based on the derivation of the same principle, the example is further extended. When the driving logic circuit is an XOR gate circuit, the driving logic compensation circuit is an XNOR gate circuit; Composed of AND gates and OR gates, the drive logic circuit and drive logic compensation circuit meeting the requirements of this embodiment can be derived based on the same principle.

Figure 5 shows the input of the driving logic circuit (named LC _{in in} the figure) in 5 consecutive clock cycles (cycles 1 to 5) when the driving logic circuit, the driving logic compensation circuit, and the first and second signal sources are in the working state. Changes in HW and HD values, where the initial state of all inputs is set to zero. As shown in FIG. 5 , the input of the driving logic circuit is assigned the sequence "1,0,0,1,1" in cycles 1-5. By observing the corresponding HW and HD values in Figure 5, it can be found that the HW and HD values corresponding to each clock cycle are not constant. According to the energy analysis theory, in the working stage, if the driving logic circuit input HW and HD values It is not constant, and the information stored and calculated in standard drive logic and even chip hardware devices can be recovered through energy analysis attack technology.

FIG. 6 is a timing diagram of the dual-edge trigger driving logic system of the present invention. Assume that the drive logic circuit input will still be assigned the sequence "1,0,0,1,1" in cycles 1-5. According to the structure of the control unit in Figure 2 and the timing analysis in Figure 3, it can be analyzed that the input of the driving logic circuit will be assigned the sequence "1,0,0,1,1" at the rising edge of cycle 1 to 5, and in cycle 1 The second half cycle of ~5 will be set to zero; in addition, it can be seen from Figure 1 that the value of the input of the driving logic compensation circuit (named CLC _{in in} the figure) is complementary to the input of the driving logic circuit, so the input of the driving logic compensation circuit is in the cycle 1~5 The rising edge of will be assigned the sequence "0,1,1,0,0", and the second half period of period 1~5 will be set to zero. This analysis is consistent with the timing shown in Figure 6. Since the value of the input of the driving logic compensation circuit is determined by the input of the driving logic circuit, that is, the two sets of input values are complementary in the working stage, so the sum of HW and HD of the driving logic circuit input and the driving logic compensation circuit input should be considered at this time, As shown in Figure 6. Among them, in each working phase, the sum clock of HW is 1; in each reset phase, the sum clock of HW is 0; when changing each phase, the sum clock of HD is 1. In this way, the purpose of keeping the HW and HD values constant is achieved, so that the driving logic circuit system has the ability to resist energy analysis attacks.

Of course, the above-mentioned driving logic system with only 1-bit input is an example. In practical applications, the multi-bit input driving logic system can be regarded as a generalization of the 1-bit input driving logic system, and the technical solution provided by the present invention is still valid.

Based on the above system composition, the present invention also provides a method for resisting energy analysis attacks, including:

When the external reset signal is valid, the control unit sends a valid reset signal to the signal source, the driving logic circuit and the driving logic compensation circuit;

When the external reset signal is invalid, when the clock signal is a rising edge, the control unit sends the clock signal and an invalid reset signal to the signal source, the driving logic circuit and the driving logic compensation circuit; The driving logic compensation circuit provides a second input signal, the first input signal is complementary to the second input signal; the driving logic circuit receives the first input signal, and generates a first output signal according to the first input signal ; The driving logic compensation circuit receives a second input signal, and calculates and generates a second output signal according to the second input signal; the first output signal is complementary to the second output signal;

When the external reset signal is invalid, the control unit sends a clock signal and an effective reset signal to the signal source, the driving logic circuit and the driving logic compensation circuit when the clock signal is at a falling edge.

To sum up, by using the double-edge trigger driving logic system to replace the standard driving logic, the ability of the driving logic system to resist energy analysis attacks is provided; at the same time, the standard driving logic system that supports double-edge triggering is implemented, so that the output of a group Two clock cycles of data are compressed into one clock cycle, which improves the throughput rate of the whole chip hardware device; moreover, the method of the present invention is simple and convenient to implement, and is easy to popularize; moreover, the double-edge trigger in the method of the present invention The components used in the drive logic system meet the requirements of the standard circuit component library, and can be normally connected with the chip hardware device circuit, and have good compatibility.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the present invention. within the scope of protection.

Claims (9)

1. A double-edge trigger driving logic system is characterized in that, comprising a signal source, a control unit, a driving logic circuit and a driving logic compensation circuit; The control unit is used to receive an external reset signal and a clock signal, and when the external reset signal is valid, the signal source, the driving logic circuit and the driving logic compensation circuit are in a reset state; when the external reset signal is invalid and the clock signal is a rising edge , the signal source, the drive logic circuit and the drive logic compensation circuit are in the working state, and when the external reset signal is invalid and the clock signal is a falling edge, the signal source, the drive logic circuit and the drive logic compensation circuit are in the reset state; The signal source is used to provide a first input signal to the driving logic circuit and a second input signal to the driving logic compensation circuit when it is in an operating state, and the first input signal is complementary to the second input signal ; The drive logic circuit is used to receive the first input signal, and calculate and generate the first output signal according to the first input signal; the drive logic compensation circuit is used to receive the second input signal, and calculate and generate the first output signal according to the second input signal The input signal is calculated to generate a second output signal; the first output signal is complementary to the second output signal. 2. The system according to claim 1, wherein the control unit comprises an external clock signal input terminal CLK, an external reset signal input terminal RST, a low level terminal, a clock signal output terminal Work, a reset signal output terminal PreC and NOR gate, first OR gate, second OR gate, third OR gate; Wherein, the external clock signal input terminal CLK and the low level terminal are respectively connected to the input terminal of the NOR gate and the input terminal of the first OR gate OR1; the output terminal of the NOR gate and the external reset signal input terminal RST are connected to the second OR gate OR2 the input terminal of the first OR gate OR1; the output terminal of the first OR gate OR1 is connected to the input terminal of the third OR gate OR3; the output terminal of the second OR gate OR2 is connected to the reset signal output terminal PreC; the first OR gate OR2 is connected to the output terminal PreC of the reset signal; The output end of the three-OR gate OR3 is connected to the clock signal output end Work. 3. The system according to claim 2, wherein the signal source comprises a first signal source for generating the first input signal and a second signal source for generating the second input signal; The first signal source includes a first reset signal receiving terminal RST1, a first clock signal receiving terminal CLK1 and a first input signal output terminal LS, the first reset signal receiving terminal RST1 is connected to the reset signal output terminal PreC, The first clock signal receiving end CLK1 is connected to the clock signal output end Work; The second signal source includes a second reset signal receiving terminal RST2, a second clock signal receiving terminal CLK2 and a second input signal output terminal CLS, the second reset signal receiving terminal RST2 is connected to the reset signal output terminal PreC, The second clock signal receiving end CLK2 is connected to the clock signal output end Work. 4. The system according to claim 3, wherein the driving logic circuit comprises a first input signal receiving terminal LCin, a third reset signal receiving terminal RST3 and a driving logic circuit output terminal LCout; the driving logic compensation circuit It includes a second input signal receiving terminal CLCin, a fourth reset signal receiving terminal RST4 and a drive logic circuit output terminal CLCout; The first input signal receiving end LCin is connected to the first input signal output end LS; the second signal input signal receiving end CLCin is connected to the second input signal output end CLS; the third reset signal receiving Terminal RST3 is connected to the reset signal output terminal PreC; the fourth reset signal receiving terminal RST4 is connected to the reset signal output terminal PreC. 5 . The system according to claim 4 , wherein when the driving logic circuit is an exclusive OR gate circuit, the driving logic compensation circuit is an exclusive NOR gate circuit. 6. The system according to claim 4, wherein when the driving logic circuit is a NOT gate circuit, the driving logic compensation circuit is a NOT gate circuit. 7. The system according to claim 4, wherein when the driving logic circuit is an AND gate circuit, the driving logic compensation circuit is a NAND gate circuit. 8. The system according to claim 4, wherein when the driving logic circuit is an OR gate circuit, the driving logic compensation circuit is a NOR gate circuit. 9. A method for resisting energy analysis attacks based on the system according to any one of claims 1-8, characterized in that it comprises: When the external reset signal is valid, the control unit sends a valid reset signal to the signal source, the driving logic circuit and the driving logic compensation circuit; When the external reset signal is invalid, when the clock signal is a rising edge, the control unit sends the clock signal and an invalid reset signal to the signal source, the driving logic circuit and the driving logic compensation circuit; The driving logic compensation circuit provides a second input signal, the first input signal is complementary to the second input signal; the driving logic circuit receives the first input signal, and generates a first output signal according to the first input signal ; The driving logic compensation circuit receives a second input signal, and calculates and generates a second output signal according to the second input signal; the first output signal is complementary to the second output signal; When the external reset signal is invalid, the control unit sends a clock signal and an effective reset signal to the signal source, the driving logic circuit and the driving logic compensation circuit when the clock signal is at a falling edge.