CN104183494B - Trench type power metal oxide semiconductor structure and forming method thereof - Google Patents
Trench type power metal oxide semiconductor structure and forming method thereof Download PDFInfo
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Abstract
Description
技术领域technical field
本发明是关于沟渠式功率金属氧化物半导体结构与其形成方法,尤指一种通过反复离子注入控制界面轮廓形状的沟渠式功率金属氧化物半导体结构与其形成方法。The present invention relates to a trench type power metal oxide semiconductor structure and its forming method, in particular to a trench type power metal oxide semiconductor structure and its forming method through repeated ion implantation to control the contour shape of the interface.
背景技术Background technique
在功率半导体的应用领域中,耐压能力及低阻抗表现是非常重要能力指标,传统的做法并无法控制界面轮廓(Junction Profile),因此无法制造更高耐压能力及具有低阻抗。In the application field of power semiconductors, withstand voltage capability and low impedance performance are very important performance indicators. Traditional methods cannot control the junction profile, so it is impossible to manufacture higher withstand voltage capability and low impedance.
发明内容Contents of the invention
本发明提供一种沟渠式功率金属氧化物半导体结构的形成方法,包括:首先形成一隔离沟槽,然后形成具有不同掺杂浓度的两个掺杂层,且两个掺杂层相连位于该隔离沟槽外围,以及形成一隔离结构位于隔离沟槽内。The present invention provides a method for forming a trench-type power metal oxide semiconductor structure, comprising: first forming an isolation trench, and then forming two doped layers with different doping concentrations, and the two doped layers are connected to each other on the isolation trench The periphery of the trench, and an isolation structure is formed in the isolation trench.
在一实施例中,本发明形成该隔离沟槽步骤的前还包括:形成一磊晶层,接着形成一栅极沟槽于磊晶层内,然后形成一栅极结构于栅极沟槽内,接着形成一本体区环绕该栅极结构外围,且该隔离沟槽位于该本体区外侧。In one embodiment, the step of forming the isolation trench in the present invention further includes: forming an epitaxial layer, then forming a gate trench in the epitaxial layer, and then forming a gate structure in the gate trench , and then forming a body region around the periphery of the gate structure, and the isolation trench is located outside the body region.
在一实施例中,本发明形成一隔离沟槽与形成具有不同掺杂浓度的两个掺杂层,是包括:形成一第一隔离沟槽;形成一第一掺杂层,位于第一隔离沟槽外围;蚀刻隔离沟槽下方的第一掺杂层,以形成一第二隔离沟槽;以及形成一第二掺杂层,位于第二隔离沟槽外围。In one embodiment, forming an isolation trench and forming two doped layers with different doping concentrations in the present invention includes: forming a first isolation trench; forming a first doped layer located at the first isolation The periphery of the trench; etching the first doped layer under the isolation trench to form a second isolation trench; and forming a second doped layer located at the periphery of the second isolation trench.
在一实施例中,本发明的第一隔离沟槽的截面积大于该第二隔离沟槽的截面积。In one embodiment, the cross-sectional area of the first isolation trench of the present invention is larger than the cross-sectional area of the second isolation trench.
在一实施例中,本发明的形成该两个掺杂层是使用不同斜角离子注入于不同位置上形成。In one embodiment, the two doped layers of the present invention are formed by ion implantation with different angles at different positions.
在一实施例中,本发明的两个掺杂层是由上而下形成且浓度为由淡到浓。In one embodiment, the two doped layers of the present invention are formed from top to bottom and the concentration is from light to thick.
本发明并提供一种沟渠式功率金属氧化物半导体结构,包括:一隔离沟槽;一隔离结构,位于隔离沟槽内;以及具有不同掺杂浓度的两个掺杂层,且两个掺杂层相连位于隔离沟槽外围。The present invention also provides a trench type power metal oxide semiconductor structure, comprising: an isolation trench; an isolation structure located in the isolation trench; and two doped layers with different doping concentrations, and the two doped layers The layer connection is located at the periphery of the isolation trench.
在一实施例中,本发明还包括:一磊晶层;一栅极沟槽,位于磊晶层内;一栅极结构,位于栅极沟槽内;一本体区,环绕栅极结构外围;其中该隔离沟槽,位于该本体区外侧,该隔离沟槽的深度高于栅极结构的深度。In an embodiment, the present invention further includes: an epitaxial layer; a gate trench located in the epitaxial layer; a gate structure located in the gate trench; a body region surrounding the periphery of the gate structure; Wherein the isolation trench is located outside the body region, and the depth of the isolation trench is higher than that of the gate structure.
在一实施例中,本发明的隔离沟槽包括相连的一第一隔离沟槽与一第二隔离沟槽,该两个掺杂层对应形成于该第一隔离沟槽与该第二隔离沟槽外围。In one embodiment, the isolation trench of the present invention includes a first isolation trench and a second isolation trench connected to each other, and the two doped layers are correspondingly formed in the first isolation trench and the second isolation trench Groove perimeter.
在一实施例中,本发明的第一隔离沟槽的截面积大于该第二隔离沟槽的截面积。In one embodiment, the cross-sectional area of the first isolation trench of the present invention is larger than the cross-sectional area of the second isolation trench.
在一实施例中,本发明的该两个掺杂层形成是使用不同斜角离子注入于不同位置上形成。In one embodiment, the two doped layers of the present invention are formed at different positions by ion implantation with different angles.
在一实施例中,本发明的两个掺杂层是由上而下形成且浓度为由淡到浓。In one embodiment, the two doped layers of the present invention are formed from top to bottom and the concentration is from light to thick.
本发明的沟渠式功率金属氧化物半导体结构及其形成方法,反复制作形成沟槽侧壁外的界面轮廓。此界面轮廓可通过注入离子量的控制,形成宽窄形状的设计变化,当回填氧化物至沟槽内部后,金属氧化物半导体(MOSFET)在逆偏压操作时将利用此区的电位效应形成电荷平衡(Charge Balance)与降低表面电场效果(RESURF),如此便可以在沟槽与侧壁电场形成较和缓的电场分布,借此利用较少空间而更有效率的获得更高的电位积分及更低的导通损失(RON)特性表现,另亦可借此原理将所需磊晶层阻值与厚度做最佳化调整,使导通损失更有效的降低,进而降低元件导通损失。In the trench type power metal oxide semiconductor structure and its forming method of the present invention, the interface profile outside the sidewall of the trench is formed repeatedly. This interface profile can be controlled by the amount of implanted ions to form a wide and narrow design change. When the oxide is backfilled to the inside of the trench, the metal oxide semiconductor (MOSFET) will use the potential effect of this region to form charges during reverse bias operation. Balance (Charge Balance) and reduce the surface electric field effect (RESURF), so that a gentler electric field distribution can be formed in the trench and sidewall electric field, so as to use less space and more efficiently obtain higher potential integration and more Low conduction loss (RON) performance, and this principle can also be used to optimize the resistance and thickness of the required epitaxial layer to reduce the conduction loss more effectively, thereby reducing the conduction loss of components.
以上的概述与接下来的详细说明皆为示范性质,是为了进一步说明本发明的申请专利范围。而有关本发明的其他目的与优点,将在后续的说明与附图加以阐述。The above summary and the following detailed description are exemplary in nature, and are intended to further illustrate the patent scope of the present invention. Other purposes and advantages of the present invention will be described in the subsequent description and accompanying drawings.
附图说明Description of drawings
图1A~1J所示为本发明的沟渠式功率金属氧化物半导体结构的形成方法的一实施例;1A to 1J show an embodiment of a method for forming a trench power metal oxide semiconductor structure of the present invention;
图2所示本发明另一沟渠式功率金属氧化物半导体结构;Another trench type power metal oxide semiconductor structure of the present invention shown in FIG. 2 ;
图3所示本发明另一沟渠式功率金属氧化物半导体结构;Another trench type power metal oxide semiconductor structure of the present invention shown in FIG. 3 ;
图4所示本发明的沟渠式功率金属氧化物半导体结构以斜角度进行离子注入方式;The trench type power metal oxide semiconductor structure of the present invention shown in FIG. 4 performs ion implantation at an oblique angle;
图5所示本发明另一沟渠式功率金属氧化物半导体结构;Another trench type power metal oxide semiconductor structure of the present invention shown in FIG. 5;
图6所示本发明另一沟渠式功率金属氧化物半导体结构。FIG. 6 shows another trench power metal oxide semiconductor structure of the present invention.
具体实施方式detailed description
本发明的主要技术特征在于反复制作至少两个掺杂层相连以形成沟槽侧壁外的界面轮廓。且此界面轮廓可通过注入离子量(即浓度)的控制,形成宽窄形状的设计变化,而达到在沟槽与侧壁电场形成较和缓的电场分布,使导通损失更有效的降低,进而降低元件导通损失。此部分的设计可应用在金属氧化物半导体结构的元件区或终端区(Termination)的沟槽,以控制注入离子量来达到特定界面轮廓以有效达到耐压能力及低阻抗效果。The main technical feature of the present invention is that at least two doped layers are connected repeatedly to form the interface profile outside the side wall of the trench. And this interface profile can be controlled by the amount of implanted ions (i.e. concentration) to form a design change in width and shape, so as to achieve a gentler electric field distribution in the trench and sidewall electric field, so that the conduction loss can be more effectively reduced, and then reduced. Component conduction loss. The design of this part can be applied to the device region or the trench of the termination region of the metal oxide semiconductor structure to control the amount of implanted ions to achieve a specific interface profile to effectively achieve the withstand voltage and low impedance effect.
如图1A~1J所示为本发明的沟渠式功率金属氧化物半导体结构的形成方法的一实施例。其应用在元件区的一个实施例,在例如外围或两侧的终端区的沟槽也可以有类似应用。1A-1J show an embodiment of the method for forming the trench power metal oxide semiconductor structure of the present invention. In an embodiment where it is applied to the device area, the grooves in the peripheral or both sides of the terminal area can also have similar applications.
首先,如图1A所示先在一基材(Substrate)10上成长一磊晶层(Epi)12。接着,在图1B中于磊晶层12内形成一栅极沟槽14,并于栅极沟槽14内侧成长一栅极介电层16。然后于图1C中形成一栅极结构18于栅极沟槽14内部,在此例如以多晶硅沉积(Poly Depostion)到栅极沟槽14内部与磊晶层12上部,然后再透过回蚀(Etch back)方式将磊晶层12上部沉积多晶硅去除,只保留栅极沟槽14内部多晶硅,而形成栅极结构18于栅极沟槽14内部。First, as shown in FIG. 1A , an epitaxial layer (Epi) 12 is grown on a substrate (Substrate) 10 . Next, a gate trench 14 is formed in the epitaxial layer 12 in FIG. 1B , and a gate dielectric layer 16 is grown inside the gate trench 14 . Then, a gate structure 18 is formed inside the gate trench 14 in FIG. 1C, where polysilicon is deposited (Poly Depostion) to the inside of the gate trench 14 and the upper part of the epitaxial layer 12, and then etched back ( Etch back) removes the deposited polysilicon on the epitaxial layer 12 , only retains the polysilicon inside the gate trench 14 , and forms the gate structure 18 inside the gate trench 14 .
接着,如图1D所示形成一本体区20,环绕栅极结构18外围,其中本体区20例如一P型导电型离子注入方式,相异于使用N型导电型的磊晶层12。接着,如图1E所示,形成一第一隔离沟槽22,位于本体区20外侧,其中第一隔离沟槽22的形成,例如可先行成一遮罩层24覆盖到栅极结构18与本体区20部分,然后再蚀刻本体区20以形成第一隔离沟槽22。第一隔离沟槽22接着以第一浓度(例如在此为P-代表),透过离子注入方式到磊晶层12内以形成第一掺杂层26,接着如垂直向下箭头27方向以驱动(Drive-In;D/I)方式,使得P-的第一掺杂层26向左右上下扩散,将P-的第一掺杂层26扩散到第一隔离沟槽22外围,外围部分例如为底部与底部侧边。Next, as shown in FIG. 1D , a body region 20 is formed around the periphery of the gate structure 18 , wherein the body region 20 is, for example, a P-type conductivity type ion implantation method, which is different from the use of the N-type conductivity type epitaxial layer 12 . Next, as shown in FIG. 1E , a first isolation trench 22 is formed, located outside the body region 20 , wherein the formation of the first isolation trench 22 , for example, can be preceded by a mask layer 24 covering the gate structure 18 and the body region. 20 , and then etch the body region 20 to form the first isolation trench 22 . The first isolation trench 22 is then ion-implanted into the epitaxial layer 12 with a first concentration (for example, represented by P − here) to form the first doped layer 26, and then as shown in the direction of the vertical downward arrow 27 Drive (Drive-In; D/I) mode, make the first doped layer 26 of P - diffuse to left and right up and down, the first doped layer 26 of P - is diffused to the periphery of the first isolation trench 22, the peripheral part is for example for the bottom and bottom sides.
接着,如图1F所示在原先第一隔离沟槽22向下蚀刻P-的第一掺杂层26,或再进一步蚀刻到磊晶层12,以扩大第一隔离沟槽22到第二隔离沟槽28,然后再以不同掺杂浓度进行离子注入,例如在此以第二浓度(P+)透过离子注入方式,到磊晶层12内形成第二掺杂层30,然后如垂直向下箭头31方向以驱动(Drive-In;D/I)方式,使得P+的第二掺杂层30向左右上下扩散,而使P+的第二掺杂层30扩散到第二隔离沟槽28外围,外围部分例如为底部与底部侧边。Next, as shown in FIG. 1F , the first doped layer 26 of P- is etched downward in the original first isolation trench 22, or further etched to the epitaxial layer 12, so as to expand the first isolation trench 22 to the second isolation trench 28, and then perform ion implantation with different doping concentrations, for example, the second concentration (P + ) is used here to form the second doped layer 30 in the epitaxial layer 12 through ion implantation, and then vertically The direction of the downward arrow 31 is driven (Drive-In; D/I), so that the second doped layer 30 of P + is diffused to the left, right, up and down, and the second doped layer 30 of P + is diffused to the second isolation trench 28. Periphery, such as the bottom and bottom sides.
接着,如图1G所示在第二隔离沟槽28向下蚀刻P+的第二掺杂层30,或进一步蚀刻到磊晶层12,以扩大第二隔离沟槽28到第三隔离沟槽32,然后再以不同掺杂浓度进行离子注入,例如在此以第三浓度(P+’)透过离子注入方式形成第三掺杂层34,其中第三掺杂层34例如可使用与第二浓度(P+)相同或大于的浓度进行,然后如垂直向下箭头31方向以驱动(Drive-In;D/I)方式,使得P+’的第三掺杂层34向左右上下扩散,而使P+’的第三掺杂层34位于第三隔离沟槽32外围,例如为底部与底部侧边。Next, as shown in FIG. 1G, etch the second doped layer 30 of P + downwards in the second isolation trench 28, or further etch to the epitaxial layer 12, so as to expand the second isolation trench 28 to the third isolation trench 32, and then perform ion implantation with different doping concentrations, for example, the third doped layer 34 is formed by ion implantation at the third concentration (P +' ), wherein the third doped layer 34 can be used for example with the first The second concentration (P + ) is equal to or greater than the concentration, and then the drive (Drive-In; D/I) method is used in the direction of the vertical downward arrow 31, so that the third doped layer 34 of P +' diffuses to the left, right, up and down, And the third doped layer 34 of P +′ is located on the periphery of the third isolation trench 32 , such as the bottom and the side of the bottom.
接着,如图1H所示在第三隔离沟槽32向下蚀刻P+’的第三掺杂层34,或进一步蚀刻到磊晶层12,以扩大第三隔离沟槽32到第四隔离沟槽36,然后进行离子注入过程,例如在此以第四浓度(P++)透过离子注入方式形成第四掺杂层38,其中第四掺杂层38例如可使用大于第三浓度(P+’)的浓度进行,然后如垂直向下箭头39方向以热驱动(Drive-In;D/I)方式,使得P++的第四掺杂层38向左右上下扩散,而使P++的第四掺杂层38位于第四隔离沟槽36的外围,外围例如为底部与底部侧边。Next, as shown in FIG. 1H, the third doped layer 34 of P +' is etched downward in the third isolation trench 32, or further etched to the epitaxial layer 12, so as to expand the third isolation trench 32 to the fourth isolation trench Groove 36, and then carry out the ion implantation process, for example, the fourth doped layer 38 is formed through ion implantation at the fourth concentration (P ++ ), wherein the fourth doped layer 38 can use a concentration greater than the third concentration (P ++ ), for example +' ) concentration, and then thermally driven (Drive-In; D/I) in the direction of the vertical downward arrow 39, so that the fourth doped layer 38 of P ++ diffuses to the left, right, up and down, so that P ++ The fourth doped layer 38 is located at the periphery of the fourth isolation trench 36 , such as the bottom and the sides of the bottom.
接着,如图1I形成一隔离结构40,位于第四隔离沟槽36内,其中隔离结构40例如使用氧化层(Oxide)构成,接着如图1J所示,分别形成N+的源极区42于本体区20内,氧化层46于N+的源极区42与栅极结构18,重掺杂层48(例如使用P++)于本本体内,并连接到N+的源极区42与隔离结构40,具有降低阻抗效果,以及金属层44于隔离结构40、重掺杂层48以及氧化层46上。在形成过程如下:首先在图1I中蚀刻部分上面氧化层41,然后透过离子植入形成N+的源极区42于本体区20,接着对两侧蚀刻,包括部分隔离结构40上面、部分N+的源极区42以及部分本体区20来形成沟渠,再对本体区进行离子植入以形成重掺杂层48,最后才做金属层44沉积。Next, as shown in FIG. 1I, an isolation structure 40 is formed, located in the fourth isolation trench 36, wherein the isolation structure 40 is made of, for example, an oxide layer (Oxide). Then, as shown in FIG. 1J, N+ source regions 42 are respectively formed on the body In the region 20, the oxide layer 46 is in the N+ source region 42 and the gate structure 18, and the heavily doped layer 48 (for example using P ++ ) is in the body and connected to the N+ source region 42 and the isolation structure 40 , has the effect of reducing impedance, and the metal layer 44 is on the isolation structure 40 , the heavily doped layer 48 and the oxide layer 46 . The formation process is as follows: first, etch part of the upper oxide layer 41 in FIG. 1I, and then form an N+ source region 42 in the body region 20 through ion implantation, and then etch both sides, including part of the upper part of the isolation structure 40, part of the N+ The source region 42 and part of the body region 20 are used to form a trench, and then the body region is ion-implanted to form a heavily doped layer 48 , and finally the metal layer 44 is deposited.
另外,如图1J所形成沟渠式功率金属氧化物半导体结构,其中第一掺杂层26、第二掺杂层30、第三掺杂层34以及第四掺杂层38为全部相连接,当然在设计上我们可以根据实际需求做部分相连接架构,例如控制具有不同掺杂浓度的至少两个掺杂层相连位于该隔离沟槽外围而得到的界面轮廓(Junction Profile),都是属于本发明可能变化的实施例。In addition, as shown in FIG. 1J , the trench type power metal oxide semiconductor structure is formed, wherein the first doped layer 26, the second doped layer 30, the third doped layer 34 and the fourth doped layer 38 are all connected, of course In terms of design, we can make part of the connection structure according to actual needs, such as controlling at least two doped layers with different doping concentrations to be connected to the interface profile (Junction Profile) obtained at the periphery of the isolation trench, all of which belong to the present invention Examples of possible variations.
另外,在图1J实施例中,由上而下的第一掺杂层26、第二掺杂层30、第三掺杂层34以及第四掺杂层38,为浓度由淡转浓而形成梯形的界面轮廓。如图2所示本发明另一沟渠式功率金属氧化物半导体结构,其中多个掺杂层,例如P+的第三掺杂层54、P-’的第二掺杂层52以及P-的第一掺杂层50构成,由上而下的多个掺杂层,为浓度由浓转淡而形成倒梯形的界面轮廓。In addition, in the embodiment of FIG. 1J , the first doped layer 26 , the second doped layer 30 , the third doped layer 34 and the fourth doped layer 38 are formed from top to bottom in order to change the concentration from light to thick. Trapezoidal interface outline. As shown in FIG. 2, another trench type power metal oxide semiconductor structure of the present invention, wherein multiple doped layers, such as the third doped layer 54 of P + , the second doped layer 52 of P- ' , and the second doped layer 52 of P- The first doped layer 50 is composed of a plurality of doped layers from top to bottom, and the concentration changes from thick to light to form an inverted trapezoidal interface profile.
此外,如图3所示本发明另一沟渠式功率金属氧化物半导体结构,其中多个掺杂层,例如P-的第三掺杂层60、N-的第二掺杂层62以及P-的第一掺杂层64构成,即以不同导电型(P型与N型)的不同浓度也可以做出界面轮廓(Junction Profile),都是属于本发明可能变化的实施例。In addition, as shown in FIG. 3, another trench type power metal oxide semiconductor structure of the present invention, in which multiple doped layers, such as the third doped layer 60 of P- , the second doped layer 62 of N- and the P- The composition of the first doped layer 64, that is, different concentrations of different conductivity types (P-type and N-type) can also make the interface profile (Junction Profile), all of which belong to the possible variant embodiments of the present invention.
接着,如图4所示本发明的沟渠式功率金属氧化物半导体结构以斜角度进行离子注入方式。如图4所示,包括四个不同步骤210,220,230,240中以不同斜角度进行离子注入,在不同深度的隔离沟槽250,260,270,280的不同位置上形成多个掺杂层,若以对应到图1D后,就可以略过图1E且不用做垂直向下的驱动(Drive-In;D/I),直接到图1F以第一斜角度(如步骤210)进行离子注入来形成P-的第一掺杂层26,接着于图1G中以第二斜角度(如步骤220)进行离子注入来形成P+的第二掺杂层30,在图1H中则以第三斜角度(如步骤230)与第四斜角度(如步骤240)进行离子注入来形成P+’的第三掺杂层34与P++的第四掺杂层38。Next, as shown in FIG. 4 , ion implantation is performed at an oblique angle in the trench power metal oxide semiconductor structure of the present invention. As shown in FIG. 4 , four different steps 210, 220, 230, and 240 are used to perform ion implantation at different oblique angles, and multiple doped layers are formed at different positions of isolation trenches 250, 260, 270, and 280 with different depths. After corresponding to FIG. 1D , you can Skip FIG. 1E and do not need to do vertical downward drive (Drive-In; D/I), go directly to FIG. 1F to perform ion implantation at the first oblique angle (such as step 210) to form the first doped layer 26 of P- , and then perform ion implantation at the second oblique angle (such as step 220) in FIG. 1G to form the second doped layer 30 of P + , and in FIG. The third doped layer 34 of P + ' and the fourth doped layer 38 of P ++ are formed by performing ion implantation (eg step 240 ).
如图5所示本发明另一沟渠式功率金属氧化物半导体结构,其中由上而下所形成第一隔离沟槽502、第二隔离沟槽504、第三隔离沟槽506以及第四隔离沟槽508具有不同截面积(或底面积),例如在此由上而下,截面积越来越小,并在不同浓度控制下得到多个掺杂层为一较平顺的一界面轮廓,其中第一隔离沟槽502、第二隔离沟槽504、第三隔离沟槽506以及第四隔离沟槽508内壁可先行成一间隙壁(Spacer)510,其中任两个上下相连的间隙壁有部分重叠,然后隔离沟槽502、504、506以及508内再填入氧化层(Oxide)或多晶硅(Poly)。As shown in FIG. 5, another trench-type power metal-oxide-semiconductor structure of the present invention, wherein a first isolation trench 502, a second isolation trench 504, a third isolation trench 506, and a fourth isolation trench are formed from top to bottom. Groove 508 has different cross-sectional areas (or bottom areas), for example, from top to bottom, the cross-sectional areas become smaller and smaller, and a plurality of doped layers are obtained under different concentration control as a smoother interface profile, wherein the first The inner walls of the first isolation trench 502, the second isolation trench 504, the third isolation trench 506, and the fourth isolation trench 508 can be formed into a spacer (Spacer) 510, wherein any two spacers connected up and down are partially overlapped, Then the isolation trenches 502 , 504 , 506 and 508 are filled with oxide or polysilicon.
如图6所示本发明另一沟渠式功率金属氧化物半导体结构,与图5相同具有不同截面积的第一隔离沟槽602、第二隔离沟槽604、第三隔离沟槽606以及第四隔离沟槽608,在不同浓度控制下所形成第一掺杂层616、第二掺杂层614、第三掺杂层612以及第四掺杂层610为一浓度由浓转淡而形成倒梯形的界面轮廓。As shown in FIG. 6, another trench power metal oxide semiconductor structure of the present invention has the same first isolation trench 602, second isolation trench 604, third isolation trench 606 and fourth isolation trench with different cross-sectional areas as in FIG. The isolation trench 608, the first doped layer 616, the second doped layer 614, the third doped layer 612 and the fourth doped layer 610 formed under different concentration control form an inverted trapezoid with a concentration changing from thick to light interface outline.
本发明的沟渠式功率金属氧化物半导体结构及其形成方法,并不限定元件区或终端区,只要具有沟槽透过注入离子浓度的控制,形成至少两个连接掺杂层,以反复制作形成沟槽侧壁外的界面轮廓来达到宽窄形状的设计变化,因此可形成电荷平衡(ChargeBalance)与降低表面电场效果(RESURF),在沟槽与侧壁电场形成较和缓的电场分布,因此提高耐压程度与降低元件导通损失。The trench-type power metal oxide semiconductor structure and its formation method of the present invention are not limited to the device area or the terminal area, as long as the trench can pass through the control of implanted ion concentration, at least two connection doped layers can be formed to form repeatedly. The interface profile outside the side wall of the trench is used to achieve the design change of the width and shape, so it can form a charge balance (ChargeBalance) and reduce the surface electric field effect (RESURF), and form a relatively gentle electric field distribution between the trench and the side wall electric field, thus improving the endurance. Voltage level and reduce component conduction loss.
如上所述,本发明完全符合专利三要件:新颖性、创造性和产业上的实用性。本发明在上文中已以较佳实施例揭露,然熟悉本项技术者应理解的是,该实施例仅用于描绘本发明,而不应解读为限制本发明的范围。应注意的是,举凡与该实施例等效的变化与置换,均应设为涵盖于本发明的范畴内。因此,本发明的保护范围当以所附的权利要求书所界定的范围为准。As mentioned above, the present invention fully complies with the three requirements of a patent: novelty, creativity and industrial applicability. The present invention has been disclosed above with preferred embodiments, but those skilled in the art should understand that the embodiments are only for describing the present invention, and should not be construed as limiting the scope of the present invention. It should be noted that all changes and substitutions equivalent to this embodiment should be included in the scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the appended claims.
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