CN104167407A - Integrated circuit assembly and packaging structure thereof - Google Patents

Abstract

An integrated circuit assembly and package construction thereof, comprising: a chip having an active surface and an electronic component formed by a semiconductor process; an electric lug, electrically connected to the electronic component through the active surface; a heat dissipation bump connected to the active surface; a lead frame electrically connected to the electrical bumps; and a sealant for coating the chip, the lead frame and the electric bump and exposing a part of the lead frame and the heat dissipation bump. The height of the heat dissipation lug relative to the active surface is not equal to the height of the electric lug relative to the active surface.

Description

Integrated circuit components and their packaging structures

【Technical field】

The invention relates to an integrated circuit component and its packaging structure, in particular to an integrated circuit component and its packaging structure suitable for heat dissipation flip-chip packaging structure.

【Background technique】

Due to the powerful functions of today's electronic products, high-speed computing and processing capabilities are required. Moreover, the size of electronic products is gradually reduced for portability. Therefore, the placement density of electronic components in devices is high, which poses challenges in heat dissipation design. In the manufacture of integrated circuits, chip-scale packaging (Chip-Scale Package, CSP) is an integrated circuit packaging technology developed in response to the reduction in the size of electronic products, of which flip-chip packaging (Flip-Chip Package) is currently quite popular packaging technology.

Please refer to the invention patent I254433 of the Republic of China (hereinafter referred to as the previous case I). The previous application I discloses a heat-dissipating flip-chip device, which has a chip, and bumps are formed on the active surface of the chip, and are connected to external solder balls through leads on the substrate. On the back of the chip, it is connected to a heat sink to provide the main heat dissipation path. The heat dissipation type flip-chip device disclosed in the previous case I, because the heat sink is stacked above the chip, it is difficult to achieve the purpose of thinning the integrated circuit, and there will be a limit in reducing the height of the device.

Please refer to the invention patent of the Republic of China I283447 (hereinafter referred to as the former case II). The previous case II discloses a chip-on-chip packaging structure, which has a flip chip disposed on the upper surface of a flexible substrate, a heat sink disposed on the lower surface of the flexible substrate, and the flip chip passes through the flexible substrate. The upper surface of the substrate and the thermal vias on the lower surface are connected to the heat sink. According to the disclosure of the previous application II, the heat sink can be disposed on the flexible substrate by sputtering. Since the metal layer formed by sputtering can be quite thin, up to the order of micro-meter (um), compared with the former case I, the height of the flip-chip package of the former case II can be further improved . However, from its structural analysis, the flip-chip chip needs to go through at least heterogeneous materials such as lead layers and thermal vias to reach the exposed heat sink. Moreover, the size of the thermal vias is also limited. These factors have affected The heat dissipation efficiency of the flip-chip package structure disclosed in the previous application II.

【New content】

In order to solve the above problems, the present invention proposes an integrated circuit assembly and its packaging structure, especially an integrated circuit assembly and its packaging structure suitable for a heat dissipation flip-chip packaging structure.

The invention provides an integrated circuit component, which includes a chip, an electrical bump, and a heat dissipation bump. The chip has an active surface and an electronic component formed by semiconductor process, and. The electrical bump is electrically connected to the electronic component through the active surface. The heat dissipation bump is connected to the active surface. Wherein, the height of the heat dissipation bump relative to the active surface is not equal to the height of the electrical bump relative to the active surface.

Moreover, the present invention further provides an integrated circuit assembly packaging structure, which includes a chip, an electrical bump, a heat dissipation bump, a lead frame, and a sealant. The chip includes an electronic component and an active surface formed by semiconductor process. The electrical bump is electrically connected to the electronic component through the active surface. The heat dissipation bump is connected to the active surface. The lead frame includes a lead, and the lead is electrically connected to the electrical bump. The sealant covers the chip, the lead frame, and the electrical bump, and exposes a part of the lead frame and the heat dissipation bump. Wherein, the height of the heat dissipation bump relative to the active surface is not equal to the height of the electrical bump relative to the active surface.

In an embodiment of the present invention, the height of the heat dissipation bump relative to the active surface is greater than the height of the electrical bump relative to the active surface.

In an embodiment of the invention, the volume of the heat dissipation bump is larger than that of the electrical bump.

In one embodiment of the present invention, it further includes an external protrusion, connected to the portion of the lead frame exposed to the sealant, and electrically connected to the lead.

In an embodiment of the present invention, the chip has a back surface opposite to the active surface, and the back surface is exposed to the sealant.

In an embodiment of the invention, the lead frame includes a lead layer.

The effect of the present invention is that in the integrated circuit assembly and its packaging structure disclosed in the present invention, the connection relationship between the heat dissipation bump and the chip forms a direct heat dissipation path to the outside, so it can cooperate with the design of the external heat dissipation mechanism to achieve a good cooling efficiency. Moreover, since the packaging structure of the integrated circuit package disclosed by the present invention is simplified in structure, its height can be further reduced, which is helpful for the thinning of its application device, so it is quite suitable for portable electronic devices.

Regarding the characteristics, implementation and effects of this creation, the best embodiment is described in detail as follows in conjunction with the drawings.

【Description of drawings】

FIG. 1 : A schematic cross-sectional view of an integrated circuit device disclosed in the present invention.

FIG. 2 is a schematic cross-sectional view of the package structure of an integrated circuit device disclosed by an embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view of the package structure of an integrated circuit device disclosed in another embodiment of the present invention.

FIG. 4 : a top perspective view of the packaging structure of the integrated circuit device disclosed in the present invention.

Description of main component symbols:

100 integrated circuit components 130 heat dissipation bumps

110 chip 131 heat conductor

111 active surface 200 package structure of integrated circuit components

115 Electronic assembly 240 Lead frame

116 Back side 245 Lead layer

120 electrical bumps 250 sealant

121 Conductor 260 External protrusion

【Detailed ways】

FIG. 1 is a schematic cross-sectional view of an integrated circuit device 100 disclosed in the present invention. The integrated circuit assembly 100 includes a chip 110 , electrical bumps 120 , and heat dissipation bumps 130 . The chip 110 has an active surface 111 and an electronic component 115 formed by a semiconductor process. The electrical bump 120 is electrically connected to the electronic component 115 through the active surface 111 . The heat dissipation bump 130 is connected to the active surface 111 . Wherein, the height of the heat dissipation bump 130 relative to the active surface 111 is not equal to the height of the electrical bump 120 relative to the active surface 111 .

The integrated circuit assembly 100 disclosed in the present invention is suitable for the flip-chip package structure described later, so that the formed integrated circuit package has the advantages of low height and good heat dissipation. Wherein the chip 110 is an integrated circuit chip formed by any semiconductor process, and may contain any active components, such as field-effect transistors (Field-Effect Transistor, FET), bipolar junction transistors (Bipolar Junction Transistor, BJT), etc., Or include any passive components such as resistors, capacitors, inductors, diodes, etc. The electrical bumps 120 are used for transmitting electrical signals, so that the circuits on the chip 110 can communicate electrically with external circuits. The heat dissipation bump 130 is used as a heat dissipation path of the chip 110 , so that the working heat generated by the chip 110 can be efficiently dissipated to the outside through the heat dissipation bump 130 .

In addition, in order to make the heat dissipation of the integrated circuit assembly 100 more efficient, the height of the heat dissipation bump 130 relative to the active surface 111 is not equal to the height of the electrical bump 120 relative to the active surface 111 . For example, in the embodiment disclosed in FIG. 1 , the height or distance from the heat dissipation bump 130 to the active surface 111 is designed to be greater than the height or distance from the electrical bump 120 to the active surface 111, so when the integrated circuit device 100 is flip-chip packaged. When the structure is formed, the heat dissipation bump 130 will be directly exposed on the surface of the package structure, and connected to the heat dissipation mechanism designed outside the flip chip package, so that the heat sink can be placed parallel to the integrated circuit assembly 100 on the circuit board, thereby reducing the overall size. The thickness of the electronic device.

In order to make the heights (or distances) of the heat dissipation bumps 130 and the electrical bumps 120 different from the active surface 111, the heat dissipation bumps 130 can be connected to the active surface 111 of the chip 110 through a heat conductor 131, and the electrical bumps The block 120 can be connected to the active surface 111 through a conductor 121 . The thermal conductor 131 is formed of a material with good thermal conductivity, such as metal. The conductor 121 is formed of a material with good electrical conductivity, such as metal. Utilizing the height difference formed by the heat conductor 131 and the conductor 121 , the height (or distance) of the heat dissipation bump 130 and the electrical bump 120 relative to the active surface 111 can be made different. Since the heat conductor 131 and the heat dissipation bump 130 directly form a heat dissipation path from the chip 110 to the outside, it has good heat dissipation efficiency. The formation of the heat conductor 131 and the conductor 121 can be formed by methods such as etching, sputtering, exposure and development known in the general semiconductor manufacturing process. This is a person with ordinary knowledge in the art who fully understands the spirit disclosed in the present invention. Afterwards, it can be implemented and completed by utilizing known technologies in the art and according to the requirements of its application, so details will not be repeated here.

In addition, in another embodiment of the present invention, the heat dissipation bumps 130 and the electrical bumps 120 can also be directly connected to the active surface 111 of the chip 110, and the heat dissipation bumps 130 and the electrical bumps 120 are different in size. The heights of the two are different, for example, the volume of the heat dissipation bump 130 is greater than that of the electrical bump 120 , and the heights of the heat dissipation bump 130 and the electrical bump 120 relative to the active surface 111 are different.

FIG. 2 is a schematic cross-sectional view of an integrated circuit device packaging structure 200 according to an embodiment of the present invention. The IC device package structure 200 includes a chip 110 , an electrical bump 120 , a heat dissipation bump 130 , a lead frame 240 , and a sealant 250 . The chip 110 includes an electronic component 115 and an active surface 111 formed by semiconductor process. The electrical bump 120 is electrically connected to the electronic component 115 through the active surface 111 . The heat dissipation bump 130 is connected to the active surface 111 . The lead frame 240 is electrically connected to the electrical bump 120 . The sealant 250 covers the chip 110 , the lead frame 240 , and the electrical bump 120 , and exposes a part of the lead frame 240 and the heat dissipation bump 130 . Wherein, the height of the heat dissipation bump 130 relative to the active surface 111 is not equal to the height of the electrical bump 120 relative to the active surface 111 .

The structure formed by the chip 110 , the electrical bump 120 , and the heat dissipation bump 130 is the integrated circuit device 100 disclosed in FIG. 1 . The sealant 250 can be formed by, for example, molding to protect the chip 110 from moisture, oxidation or direct impact, and to seal the chip 110, the electrical bumps 120, the heat dissipation bumps 130, and the chip 110. The lead frame 240 forms a unitary structure.

In addition, in yet another embodiment of the present invention, the integrated circuit assembly package structure 200 may further include an external protrusion 260 connected to the portion of the lead frame 240 exposed to the sealant 250 . The external bump 260 can be electrically connected with the external circuit conveniently, such as by soldering, so that the circuit on the chip 110 can communicate electrically with the external circuit.

In yet another embodiment of the present invention, the lead frame 240 includes a lead layer 245 (as shown in FIG. 3 ).

FIG. 3 is a schematic cross-sectional view of an integrated circuit device packaging structure 300 according to another embodiment of the disclosure. The difference between the integrated circuit assembly packaging structure 300 and the integrated circuit assembly packaging structure 200 shown in FIG. Glue 250. The back surface 116 of the chip 110 is exposed to the sealant 250 , so that a heat sink can be further added to the outside of the package structure 300 of the integrated circuit assembly to enhance the heat dissipation function, thus contributing to the miniaturization of high-power circuit applications.

FIG. 4 is a top perspective view of an integrated circuit device packaging structure 200 disclosed in the present invention. In this embodiment, the electrical bumps 120 can be respectively connected to a set of lead frames 240 , and the electrical bumps 120 can be directly connected to the lead frames 240 , or electrically connected to the lead frames 240 through a lead layer 245 . The portion of the bottom of the integrated circuit package structure 200 that is not overlapped by the lead frame 240 can be used to form the heat dissipation bump 130 to form a heat conduction path. The heat dissipation bump 130 can be made into various shapes according to the capability of the process technology, such as being made into a square shape and so on. It should be noted that the structure disclosed in FIG. 4 is only used to illustrate the spirit of the present invention and is not intended to limit the scope of the present invention. Those skilled in the art, after fully understanding the spirit of the present invention, can make different design changes according to the application requirements, such as the arrangement design of the external protrusions 260, or the sharing of multiple electrical protrusions 120 The same lead frame 240 and so on, so it will not be repeated here.

In the integrated circuit assembly package structure 200 disclosed in the present invention, the connection relationship between the heat dissipation bump 130 and the chip 110 forms a direct heat dissipation path from the chip 110 to the outside, so it can cooperate with the design of the external heat dissipation mechanism to achieve good heat dissipation efficiency. Moreover, due to the simplification of the structure of the integrated circuit assembly packaging structure 200 itself, the substrate assembly in the conventional flip-chip packaging is omitted, so that the height of the integrated circuit assembly packaging structure 200 can be further reduced, which contributes to the thinning of its application device. Therefore, it is quite suitable for portable electronic devices.

Although the embodiment of this creation is disclosed as above, it is not intended to limit this creation. Anyone who is familiar with related skills can use the shapes, structures, and features described in the scope of this creation without departing from the spirit and scope of this creation. Slight changes can be made in the number and quantity, so the scope of patent protection for this creation must be defined by the scope of patent application attached to this specification.

Claims (11)

1. An integrated circuit assembly, characterized in that the integrated circuit assembly comprises: A chip has an active surface and an electronic component formed by semiconductor manufacturing process; an electrical bump electrically connected to the electronic component through the active surface; and a heat dissipation bump connected to the active surface; Wherein, the height of the heat dissipation bump relative to the active surface is not equal to the height of the electrical bump relative to the active surface. 2. The integrated circuit assembly as claimed in claim 1, wherein the height of the heat dissipation bump relative to the active surface is greater than the height of the electrical bump relative to the active surface. 3. The integrated circuit assembly according to claim 1 or 2, wherein the volume of the heat dissipation bump is larger than the volume of the electrical bump. 4. The integrated circuit assembly according to claim 1 or 2, wherein the heat dissipation bump is connected to the active surface through a heat conductor, and the electrical bump is connected to the active surface through a conductor active side. 5. The integrated circuit assembly as claimed in claim 4, wherein the material of the thermal conductor and the conductor is metal. 6. An integrated circuit assembly packaging structure, characterized in that the integrated circuit assembly packaging structure comprises: A chip has an active surface and an electronic component formed by semiconductor manufacturing process; an electrical bump electrically connected to the electronic component through the active surface; a heat dissipation bump connected to the active surface; a lead frame electrically connected to the electrical bump; and A sealant, covering the chip, the lead frame, and the electrical bump, and exposing a part of the lead frame and the heat dissipation bump; Wherein, the height of the heat dissipation bump relative to the active surface is not equal to the height of the electrical bump relative to the active surface. 7 . The package structure of an integrated circuit device as claimed in claim 6 , wherein the height of the thermal bump relative to the active surface is greater than the height of the electrical bump relative to the active surface. 8. The package structure of an integrated circuit device as claimed in claim 6 or 7, wherein the volume of the heat dissipation bump is larger than the volume of the electrical bump. 9. The package structure of an integrated circuit device as claimed in claim 6 or 7, further comprising an external protrusion connected to a portion of the lead frame exposed to the sealant. 10. The package structure of an integrated circuit device as claimed in claim 6 or 7, wherein the chip has a back surface opposite to the active surface, and the back surface is exposed to the sealant. 11. The package structure of an integrated circuit device as claimed in claim 6, wherein the lead frame comprises a lead layer.