CN104124168A - Method for forming semiconductor structure - Google Patents

Abstract

A method for forming a semiconductor structure, comprising: providing a base, the surface of the base has fins; forming a first dummy gate layer on the base and the surface of the fins, the surface of the first dummy gate layer is higher than the the top surface of the fin; planarize the first dummy gate layer until the top surface of the fin is exposed; after the planarization process, form the first dummy gate layer and the surface of the fin Two dummy gate layers; etching part of the first dummy gate layer and the second dummy gate layer until the top and sidewall surfaces of the fin are exposed, forming a dummy gate across the sidewall and top surface of the fin pole. In the formed semiconductor structure, the uniformity and precision of the thickness dimension of the gate structure on the top surface of the fin are improved.

Description

Formation method of semiconductor structure

technical field

The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure.

Background technique

With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher element density and higher integration. As the most basic semiconductor device, transistors are currently being widely used. Therefore, with the increase of component density and integration of semiconductor devices, the gate size of planar transistors is getting shorter and shorter. The ability of traditional planar transistors to control channel current Weakened, resulting in short channel effect, resulting in leakage current, and ultimately affecting the electrical performance of semiconductor devices.

In order to overcome the short-channel effect of the transistor and suppress the leakage current, the prior art proposes a Fin Field Effect Transistor (Fin FET), which is a common multi-gate device, please refer to Figure 1, Figure 1 is A schematic diagram of a three-dimensional structure of a fin field effect transistor in the prior art, including: a semiconductor substrate 10; a protruding fin 14 located on the semiconductor substrate 10; covering the surface of the semiconductor substrate 10 and the side walls of the fin 14 A part of the dielectric layer 11, the surface of the dielectric layer 11 is lower than the top of the fin 14; a gate structure 12 across the top and sidewall of the fin 14, the gate structure 12 includes a gate A dielectric layer (not shown) and a gate electrode (not shown) on the gate dielectric layer. It should be noted that, for a fin field effect transistor, the top of the fin 14 and the sidewalls on both sides in contact with the gate structure 12 become the channel region, that is, there are multiple gates, which is beneficial to increase the driving current. Improve device performance.

In the prior art, in order to further improve the performance of the fin field effect transistor, the gate dielectric layer is made of a high-k dielectric material, and the gate electrode layer is made of metal, that is, the fin field effect transistor forms a high-k metal gate (High-k Metal Gate, HKMG) transistor, the high-K metal gate structure of the fin field effect transistor can be formed using a gate last (Gate Last) process.

However, in the prior art, when a fin field effect transistor with a high-K metal gate structure is formed by a post-gate process, the thickness of the gate structure on the top surface of several fins on the same semiconductor substrate is not uniform, and the gate structure It is difficult to control the thickness of the fin field effect transistors, so that the electrical properties of the formed fin field effect transistors are inconsistent, and it is difficult to control the performance of the formed semiconductor devices.

Contents of the invention

The problem to be solved by the present invention is to provide a method for forming a semiconductor structure, which improves the uniformity and accuracy of the thickness dimension of the gate structure on the top surface of the fin.

In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the surface of the substrate has fins; forming a first dummy gate layer on the substrate and the surface of the fins, and the first dummy The surface of the gate layer is higher than the top surface of the fin; the first dummy gate layer is planarized until the top surface of the fin is exposed; after the planarization process, the first dummy gate Form the second dummy gate layer on the electrode layer and the surface of the fin; etch part of the first dummy gate layer and the second dummy gate layer until the top and sidewall surfaces of the fin are exposed, forming a gate across the fin Dummy gates on sidewalls and top surface.

Optionally, it also includes: a mask layer located on the top surface of the fin, the first dummy gate layer is also deposited on the surface of the mask layer, and the surface of the first dummy gate layer is equal to or higher than the mask layer surface.

Optionally, the process of planarizing the first dummy gate layer is: using a chemical mechanical polishing process to planarize the first dummy gate layer until the top surface of the mask layer is exposed; After the gate layer, etch back the first dummy gate layer until the surface of the first dummy gate layer is flush with the surface of the fin; after the etch back process, remove the mask layer.

Optionally, the etch-back process is an anisotropic dry etching process, and the process parameters are: the bias power is less than 100W, and the etching gas includes CF ₄ , SF ₆ or NF ₃ .

Optionally, the etch depth of the etch-back process is controlled by an advanced process control device.

Optionally, the formation process of the fins includes: providing a semiconductor substrate, and the semiconductor substrate is a bulk substrate; forming a mask layer on the surface of the bulk substrate; Etching the bulk substrate and forming openings, the bulk substrate between adjacent openings forms fins; forming a first dielectric layer at the bottom of the openings, and the first dielectric layer covers part of the side wall surfaces of the fins.

Optionally, the material of the bulk substrate is silicon, germanium or silicon germanium.

Optionally, the forming process of the fin portion is: providing a semiconductor substrate, the semiconductor substrate is a semiconductor-on-insulator substrate, and the semiconductor-on-insulator substrate includes an insulating layer and a semiconductor layer located on the surface of the insulating layer, The material of the semiconductor layer is silicon or germanium; a mask layer is formed on the surface of the semiconductor layer; the semiconductor layer is etched using the mask layer as a mask until the surface of the insulating layer is exposed to form a mask layer located on the insulating layer. of the fins.

Optionally, the method further includes: after forming the fin, forming a first silicon oxide layer on the sidewall surface of the fin by using a thermal oxidation process, and the thickness of the first silicon oxide layer is 1 nanometer to 5 nanometers.

Optionally, the formation process of the mask layer is a multiple patterned mask process.

Optionally, when the formation process of the mask layer is a double patterned mask process, the formation process of the mask layer is: forming a sacrificial film on the surface of the semiconductor substrate; forming patterned layer; using the patterned layer as a mask to etch the sacrificial film until the semiconductor substrate is exposed to form a sacrificial layer; depositing a mask film on the surface of the semiconductor substrate and the sacrificial layer; etching back the The mask film is formed until the semiconductor substrate is exposed to form a mask layer, and the sacrificial layer is removed.

Optionally, after the fins are formed, a thermal annealing process is performed, and the temperature of the thermal annealing process is 900 degrees Celsius to 1100 degrees Celsius.

Optionally, the material of the mask layer is silicon nitride, silicon oxide or silicon oxynitride.

Optionally, when the material of the mask layer is silicon nitride, the method further includes: forming a second silicon oxide layer between the top of the fin and the mask layer.

Optionally, the material of the first dummy gate layer is the same as or different from that of the second dummy gate layer.

Optionally, the formation process of the first dummy gate layer or the second dummy gate layer is a chemical vapor deposition process or a physical vapor deposition process; the material of the first dummy gate layer or the second dummy gate layer It is doped polysilicon, undoped polysilicon, amorphous silicon, silicon germanium or amorphous carbon.

Optionally, the chemical vapor deposition process parameters for forming the second dummy gate layer are as follows: the temperature is 200-800 degrees Celsius, the gas pressure is 1 Torr-100 Torr, the power is 300 watts to 600 watts, and the gas includes HCl and H ₂ , the flow rate of HCl is 1 sccm ~ 1000 sccm, the flow rate of H ₂ is 0.1 slm ~ 50 slm; when the material of the second dummy gate layer is undoped polysilicon, the gas also includes silicon source gas SiH ₄ or SiH ₂ Cl ₂ , the flow rate of the silicon source gas is 1sccm～1000sccm; when the material of the second dummy gate layer is silicon germanium, the gas also includes silicon source gas SiH ₄ or SiH ₂ Cl ₂ and germanium source gas GeH ₄ , so The flow rate of the silicon source gas is 1 sccm-1000 sccm, and the flow rate of the germanium source gas is 1 sccm-1000 sccm.

Optionally, the forming process of the dummy gate is: forming a dummy gate mask on the surface of the second dummy gate layer, the dummy gate mask defines the pattern of the dummy gate, and the material of the dummy gate mask It is silicon nitride or silicon oxynitride; the second dummy gate layer and the first dummy gate layer are etched using the dummy gate mask until the top and sidewall surfaces of the fins are exposed.

Optionally, before forming the first dummy gate layer, a third silicon oxide layer is deposited on the surface of the base and the sidewall and top surface of the fin.

Optionally, it also includes: after forming the dummy gate, forming a source region and a drain region in the fins on both sides of the dummy gate; after forming the source region and the drain region, forming The sidewall and the top surface of the part form a second dielectric layer, and the surface of the second dielectric layer is flush with the top surface of the dummy gate; after forming the second dielectric layer, after removing the dummy gate and An opening is formed in the second dielectric layer; a gate dielectric layer is formed in the opening, and a gate electrode layer filling the opening is formed on the surface of the gate dielectric layer.

Compared with the prior art, the technical solution of the present invention has the following advantages:

After depositing the first dummy gate layer on the base and the surface of the fin, planarize the first dummy gate layer until the top of the fin is exposed, and then form a second dummy gate layer on the first dummy gate layer and the surface of the fin. dummy gate layer, the thickness of the second dummy gate layer can be accurately controlled through the process, and the thickness of the second dummy gate layer at different positions on the substrate can be made uniform. Subsequently, by etching the second dummy gate layer and the first dummy gate layer to form a dummy gate across the sidewall and top surface of the fin, the thickness dimension of the dummy gate formed on the top surface of the fin can be made Accurate, and the thickness of dummy gates at the tops of different fins is uniform, which improves the stability of the formed semiconductor device.

Further, the top surface of the fin part also has a mask layer, the mask layer is used to define the pattern of the fin part in the previous process, and the fin part is formed by etching with the mask layer, and the first dummy gate The pole layer is also deposited on the surface of the mask layer. The process of planarizing the first dummy gate layer is: using a chemical mechanical polishing process to polish the first dummy gate layer until the mask layer is exposed, and the mask layer is used as a polishing stop layer and protects the fins. The top is not damaged. Then, an etch-back process is used to make the surface of the first dummy gate layer flush with the surface of the fin; the etch-back process can precisely control the etching depth by adjusting the etching rate and etching time, so that the first The surface of the dummy gate layer is flush with the surface of the fin.

Further, the etch depth of the etch-back process is controlled by an advanced process control (APC, Advanced Process Control) device; the advanced process control device can detect the surface of the first dummy gate layer located at different positions on the substrate, and obtain The surface height state of the first dummy gate layer after polishing; the measured surface state of the first dummy gate layer, combined with the parameters of the etch-back process, such as etching rate and etching time, can obtain the different positions of the substrate. The depth of etching back required for the first dummy gate layer; ensure that the surface of the first dummy gate layer after etch back is uniform, and then make the second dummy gate layer formed on the surface of the first dummy gate layer subsequently The surface is uniform.

Further, when the materials of the first dummy gate layer and the second dummy gate layer are different, after etching the second dummy gate layer to expose the first dummy gate layer, it is necessary to replace the etching gas to Continue to etch the first dummy gate layer until the substrate is exposed, and the gas used to etch the first dummy gate layer is not easy to damage the etched second dummy gate layer, thereby ensuring the The appearance of the dummy gate is good, which is conducive to the stable performance of the formed device.

Description of drawings

FIG. 1 is a schematic diagram of a three-dimensional structure of a fin field effect transistor formed in the prior art;

2 to 4 are schematic cross-sectional structural views of the process of forming a fin field effect transistor in the prior art;

5 to 12 are schematic cross-sectional structure diagrams of the formation process of the semiconductor structure according to the embodiment of the present invention.

Detailed ways

As mentioned in the background, the thickness of the gate structure on the top surface of the fin in the prior art is non-uniform and imprecise.

In an embodiment, the formation process of forming the high-K metal gate structure on the surface of the fin is shown in FIGS. 2 to 4 .

Referring to FIG. 2, a semiconductor substrate 10, a protruding fin 14 located on the semiconductor substrate 10, and a dielectric layer 11 covering the surface of the semiconductor substrate 10 and part of the sidewall of the fin 14 are provided. 11 and the sidewalls and top surfaces of the fins 14 are deposited a dummy gate layer 15 , the dummy gate layer 15 fills the openings (not shown) between adjacent fins 14 .

Referring to FIG. 3 , a chemical mechanical polishing process is used to planarize the dummy gate layer 15 .

Please refer to FIG. 4, FIG. 4 is based on the cross section of FIG. 3 along the CC' direction, etching part of the dummy gate layer 15 until the top and sidewall surfaces of the fins 14 and the surface of the dielectric layer 11 are exposed, forming a cross section across the fins. The dummy gate 15a on the sidewall and top surface of the portion 14.

After forming the dummy gate 15a, a source region and a drain region are formed in the fins 14 on both sides of the dummy gate 15a, and on the surface of the dielectric layer 11, the sidewall and top surface of the fin 14, and the dummy An insulating layer is deposited on the surface of the gate 15a; the insulating layer is chemically mechanically polished until the top surface of the dummy gate 15a is exposed; after that, the dummy gate 15a is removed and a gate dielectric layer and a gate dielectric layer are formed at the position of the original dummy gate 15a. The gate electrode layer on the surface of the dielectric layer.

After depositing the insulating layer, it is necessary to planarize the insulating layer by chemical mechanical polishing until the dummy gate is exposed, so that the insulating layer can completely replicate the shape of the dummy gate and facilitate subsequent removal of the dummy gate. pole. In order to fully expose the top surface of the dummy gate after polishing the insulating layer, it is necessary to planarize the top surface of the dummy gate, so it is necessary to planarize the dummy gate layer after depositing the dummy gate layer. and etching the dummy gate layer to form a dummy gate. However, when using a chemical mechanical polishing process to planarize the dummy gate layer, it is difficult to control the thickness of the remaining dummy gate layer on the top of the fin after polishing; There is a difference in the height of the dummy gate layer, which results in poor uniformity in thickness and size of the dummy gate layer formed on the top surface of the fin at different positions on the same semiconductor substrate. Therefore, the FinFET with the high-K metal gate structure formed by the prior art has poor feature size uniformity and poor accuracy.

After further research by the inventors of the present invention, the prior art has been improved. After depositing the first dummy gate layer on the substrate and the surface of the fin, planarize the first dummy gate layer until the top surface of the fin is exposed. , and then form a second dummy gate layer on the first dummy gate layer and the surface of the fin, the thickness of the second dummy gate layer can be precisely controlled by the process, and the first dummy gate layer located at different positions on the substrate can be The thickness of the two dummy gate layers is uniform. Subsequently, by etching the second dummy gate layer and the first dummy gate layer to form a dummy gate across the sidewall and top surface of the fin, the thickness dimension of the dummy gate formed on the top surface of the fin can be made Accurate, and the thickness of dummy gates at the tops of different fins is uniform, which improves the stability of the formed semiconductor device.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

5 to 12 are schematic cross-sectional structure diagrams of the formation process of the semiconductor structure according to the embodiment of the present invention.

Referring to FIG. 5 , a substrate 200 is provided, the surface of the substrate 200 has fins 201 , and a top surface of the fins 201 has a mask layer 202 .

In this embodiment, the base 200 and the fins 201 are part of the provided semiconductor substrate, wherein the base 200 provides a platform for subsequent processes, and the fins 201 are formed by etching the semiconductor substrate. Forming; the semiconductor substrate includes a bulk substrate or a semiconductor-on-insulator substrate; the material of the bulk substrate includes silicon, germanium, and silicon germanium; the semiconductor-on-insulator substrate includes a substrate, an insulating layer positioned on the surface of the substrate layer and a semiconductor layer on the surface of the insulating layer, the material of the semiconductor layer includes silicon or germanium.

When the semiconductor substrate is a bulk substrate, the forming process of the fin portion 201 is as follows: forming a mask layer 202 on the surface of the bulk substrate; etching the bulk substrate using the mask layer 202 as a mask. The substrate forms openings, the bulk substrate between adjacent openings forms the fins 201 , and the rest of the bulk substrate at the bottom of the fins 201 forms the base 200 . In this embodiment, the fin 201 is formed by etching the bulk substrate, and the remaining bulk substrate at the bottom of the fin 201 forms the base 200 .

It should be noted that, when the semiconductor substrate is a bulk substrate and the fins 201 are formed by etching the bulk substrate, after the fins 201 are formed by etching, the first substrate 200 and the surfaces of the fins 201 are deposited. A dielectric film; etch back the first dielectric film until the top and part of the sidewall surface of the fin 201 are exposed, and form a first dielectric layer 203 at the bottom of the opening, the surface of the first dielectric layer 203 is lower on the top surface of the fin portion 201 and cover part of the sidewall surface of the fin portion 201 .

When the semiconductor substrate is a semiconductor-on-insulator substrate, the forming process of the fin portion is as follows: forming a mask layer 202 on the surface of the semiconductor layer; using the mask layer 202 as a mask to etch the semiconductor layer until Fins located on the insulating layer are formed until the surface of the insulating layer is exposed. Wherein, the insulating layer in the semiconductor-on-insulator substrate serves as a dielectric layer for isolating the fins, and the substrate in the semiconductor-on-insulator substrate serves as a base.

In other embodiments, the fins can also be formed on the surface of the provided semiconductor substrate, and the formation process is as follows: forming a dielectric layer with openings on the surface of the semiconductor substrate, and the openings define the pattern and position of the fins, and exposing the surface of the semiconductor substrate; forming a fin in the opening by using an epitaxial deposition process, and etching back the dielectric layer so that the surface of the dielectric layer is lower than the surface of the fin.

In addition, after the fin portion 201 is formed, a thermal annealing process is performed to eliminate defects in the fin portion 201, so that the channel region of the formed fin field effect transistor has good performance; the temperature of the thermal annealing process is 900 degrees Celsius to 1100 degrees Celsius, the annealing gas is hydrogen or helium.

The mask layer 202 is used as a mask when etching the semiconductor substrate to form the fin portion 201, and the mask layer 202 can also protect the first dummy gate layer during subsequent polishing and etching back. The tops of the fins 201 are protected from damage. The material of the mask layer 202 is silicon nitride, silicon oxide or silicon oxynitride; when the material of the mask layer 202 is silicon nitride, in order to enhance the bonding ability between silicon nitride and the surface of the semiconductor substrate, A second silicon oxide layer 210 will be formed between the surface of the semiconductor substrate and the mask layer 202 as a transition between the semiconductor substrate and the mask layer 202, that is, there is a gap between the formed fin 201 and the mask layer 202. The second silicon oxide layer 210 ; the formation process of the second silicon oxide layer 210 is a thermal oxidation process or a deposition process, and the thickness of the second silicon oxide layer 210 is 1 nanometer to 5 nanometers. In this embodiment, a second silicon oxide layer 210 is formed on the top surface of the fin portion 201 , and a mask layer 202 made of silicon nitride is formed on the surface of the second silicon oxide layer 210 .

It should be noted that the number of fins 201 is single or multiple, and three adjacent fins 201 are shown in this embodiment; in order to make the size of the formed fins 201 small, and The size between the parts 201 is small, and the formation process of the mask layer 202 is a multiple patterned mask process, such as a self-aligned double patterned (Self-aligned Double Patterned, SaDP) process, a self-aligned triple patterned ( Self-aligned Triple Patterned) process, or self-aligned quadruple patterning (Self-aligned DoubleDouble Patterned, SaDDP) process.

In this embodiment, the formation process of the mask layer 202 is a double patterned mask process, the formation process is: forming a sacrificial film on the surface of the semiconductor substrate; forming a patterned layer on a part of the surface of the sacrificial film, so The patterned layer can be formed by a photolithography process, a nano-printing process, or a directed self-assembly process; in this embodiment, a photolithography process is used to form the patterned layer, and the material of the patterned layer is photoresist; The sacrificial layer is used as a mask to etch the sacrificial film until the semiconductor substrate is exposed to form a sacrificial layer; a mask film is deposited on the surface of the semiconductor substrate and the sacrificial layer; the mask film is etched back until the semiconductor substrate is exposed To the substrate, a mask layer is formed, and the sacrificial layer is removed.

In addition, after the fin portion 201 is formed, a first silicon oxide layer 211 is formed on the sidewall surface of the fin portion 201 by a thermal oxidation process, the thickness of the first silicon oxide layer 211 is 1 nm to 5 nm, and the first The silicon oxide layer 211 can protect the sidewall surface of the fin portion 201 from damage when the first dummy gate layer and the second dummy gate layer are subsequently etched to form dummy gates.

Please refer to FIG. 6 , a first dummy gate layer 204 is formed on the surface of the first dielectric layer 203 , the fin portion 201 and the mask layer 202 , and the surface of the first dummy gate layer 204 is equal to or higher than the The top surface of the mask layer 202 .

The first dummy gate layer 204 and the subsequently formed second dummy gate layer are jointly used to form a dummy gate, and the dummy gate occupies a space for the high-K metal gate structure to be formed; the first dummy gate The formation process of the electrode layer 204 is a deposition process, including a chemical vapor deposition process or a physical vapor deposition process, and the material of the first dummy gate layer 204 is doped polysilicon, undoped polysilicon, amorphous silicon, silicon germanium or inorganic Shaped carbon; in addition, before forming the first dummy gate layer 204, a third silicon oxide layer (not shown) is deposited on the surface of the substrate 200 and the sidewalls and top surfaces of the fins 201, the third silicon oxide layer can further protect the sidewall surface of the fin portion 201 from damage in subsequent processes, such as etching to form a dummy gate layer.

In the subsequent process, in order to ensure that the thickness of the dummy gate formed on the top of the fin 201 is accurate and uniform, the first dummy gate layer 204 needs to be polished to the surface of the mask layer 202 and etched back to the top surface of the fin 201 , in order to subsequently deposit a second dummy gate layer with a uniform and precise thickness on the first dummy gate layer 204 and the surface of the fin portion 201, so the surface of the first dummy gate layer 204 that needs to be deposited is higher than the top of the fin portion 201 , and equal to or higher than the top surface of the mask layer 202; while the fins 201 protrude from the surface of the first dielectric layer 203, it is easy to make the surface of the formed first dummy gate layer 204 have a difference in height, in order to ensure The surface of the first dummy gate layer 204 after the process is not lower than the top surface of the fin portion 201 , and it needs to be ensured that the lowest point of the surface of the first dummy gate layer 204 is not lower than the top of the mask layer 202 .

Referring to FIG. 7 , the first dummy gate layer 204 is planarized until the top surface of the mask layer 202 is exposed.

The planarization process is a chemical mechanical polishing process. In the chemical mechanical polishing process, the mask layer 202 defines the stop position of the polishing process, and due to the protection of the mask layer 202, the fins The top of portion 201 will not be damaged during the polishing process.

However, since the polishing process stops at the mask layer 202, the surface of the first dummy gate layer 204 after polishing is still higher than the top of the fin portion 201; The polishing uniformity of the first dummy gate layer 204 is not uniform, and it is easy to cause the height of the first dummy gate layer 204 at different positions on the surface of the substrate 200 to be inconsistent after the polishing process; Etching the layer 204 to form a dummy gate will lead to inconsistency in the feature size of the formed fin field effect transistor, and the stability of the formed device will be deteriorated.

Therefore, after the chemical mechanical polishing process, it is necessary to use an etch-back process to make the surface of the first dummy gate layer 204 flush with the surface of the fin portion 201, and then form a The second dummy gate layer with a uniform thickness can make the size of the dummy gate formed by etching uniform, and the distance from the surface of the dummy gate to the top of the fin 201 is precise.

Referring to FIG. 8 , after the first dummy gate layer 204 is planarized, the first dummy gate layer 204 is etched back until the surface of the first dummy gate layer 204 is flush with the surface of the fin portion 201 .

The etch-back process is an anisotropic dry etching process, and the process parameters are: the bias power is less than 100W, and the etching gas includes CF ₄ , SF ₆ or NF ₃ ; the anisotropic dry etching process The process controls the etching depth by controlling the etching time, and the etching depth of the etching back process can also be precisely controlled by an advanced process control (APC, Advanced Process Control) device.

The advanced process control device includes a detection device, an arithmetic device and a control device; wherein the detection device is used to detect the surface state of the first dummy gate layer 204 after polishing on the entire surface of the substrate 200; specifically for the first dummy gate layer 204 The height difference on the surface of the gate layer 204 is detected to determine the height distribution state of the first dummy gate layer 204 on the entire substrate 200; the height distribution state of the overall first dummy gate layer 204, and the Input the various parameters of the above-mentioned anisotropic dry etching process into the computing device to obtain the etching depth required for different positions of the entire first dummy gate layer 204, so as to ensure that the first dummy gate after etching back The surface of the layer 204 can be flush with the top surface of the fin portion 201; the control device performs the etching back process according to the etching depth data of different positions of the first dummy gate layer 204 obtained by the computing device, and the etched second The top surfaces of a dummy gate layer 204 can be flush with the top surfaces of the fins 201 . Using the advanced process control device to control the etch-back process can ensure that the surface of the first dummy gate layer 204 after etch-back is uniform, so that the second dummy gate layer 204 with a uniform thickness subsequently formed on the surface of the first dummy gate layer The surface of the gate layer is also kept uniform, and the thickness of the dummy gates subsequently formed on the top surface of the fin portion at different positions of the substrate 200 is uniform, which ensures stable performance of the formed device.

It should be noted that, in this embodiment, a second silicon oxide layer 210 is further formed between the fin portion 201 and the mask layer 203, and the thickness of the second silicon oxide layer 210 is 1 nanometer to 5 nanometers; In this embodiment, the surface of the first dummy gate layer 204 after etching back is flush with the surface of the second silicon oxide layer 210. Since the thickness of the second silicon oxide layer 210 is extremely thin, the first The surface of the dummy gate layer 204 is flush with the top surface of the fin 201 . The second silicon oxide layer 210 can also protect the top surface of the fin portion 201 to reduce damage when the dummy gate is formed by subsequent etching.

Referring to FIG. 9 , after the etch-back process, the mask layer 202 (as shown in FIG. 8 ) is removed to expose the second silicon oxide layer 210 on the top surface of the fin portion 201 .

The process of removing the mask layer 202 is an etching process, including dry etching and wet etching; the material of the mask layer 202 is silicon nitride, silicon oxide or silicon oxynitride. When etching and removing the mask layer 202, the etching solution for wet etching includes: phosphoric acid (etching silicon nitride) and/or hydrofluoric acid (etching silicon oxide), when the mask layer is removed by dry etching layer 202, the etching gas includes CHF ₃ (etching silicon oxide) and/or CF ₄ (etching silicon nitride), and the dry etching can be anisotropic or isotropic; by adjusting the wet etching The ratio of the etching liquid for etching, or the ratio of the etching gas for dry etching, controls the selectivity ratio of the etching process, so as to remove silicon nitride, silicon oxide or silicon oxynitride.

In this embodiment, a second silicon oxide layer 210 is formed on the top of the fin, the mask layer 202 is formed on the surface of the second silicon oxide layer 210, the mask layer 202 is removed by wet etching and The second silicon oxide layer 210 is retained, the wet etching process has less damage to the second silicon oxide layer 210, and the removal of the mask layer 202 is fast and complete, and the second silicon oxide layer 210 can also be used in subsequent The top surface of the fin 201 is protected during etching to form the dummy gate.

Moreover, in this embodiment, etch back the first dummy gate layer 204 to be flush with the surface of the second silicon oxide layer 210, after removing the mask layer, the first dummy gate layer 204 and the fin portion 201 The overall surface formed by the second silicon oxide layer 210 on the surface is flat, and after depositing a second dummy gate layer with a uniform thickness on the first dummy gate layer 204 and the fin portion 201, the second dummy gate layer The surface of the fin portion 201 is flat, which is beneficial to make the thickness of the dummy gate formed on the top surface of the fin portion 201 accurate and uniform.

Please refer to FIG. 10 and FIG. 11. FIG. 11 is a schematic cross-sectional structure diagram of FIG. 10 along the BB' direction. After removing the mask layer 202 (as shown in FIG. A second dummy gate layer 205 is formed on the surface of the fin portion 201 .

The material of the second dummy gate layer 205 is doped polysilicon, undoped polysilicon, amorphous silicon, silicon germanium or amorphous carbon; the material of the first dummy gate layer 204 is the same as that of the second dummy gate layer 205 are made of the same or different materials; especially, when the materials of the first dummy gate layer 204 and the second dummy gate layer 205 are different, it is more beneficial to make the morphology of the dummy gate formed by subsequent etching good: Specifically, when the second dummy gate layer 205 is subsequently etched to expose the first dummy gate layer 204, the etching gas needs to be replaced to continue etching the first dummy gate layer 204 until the first dielectric layer is exposed. 203, when the materials of the first dummy gate layer 204 and the second dummy gate layer 205 are different, the gas used to etch the second dummy gate layer 205 is less likely to damage the etched second dummy gate layer 205, so as to ensure the morphology of the dummy gate located on the top surface of the fin portion 201, which is beneficial to the stable performance of the formed device.

The formation process of the second dummy gate layer 205 is a chemical vapor deposition process or a physical vapor deposition process, preferably a chemical vapor deposition process; the chemical vapor deposition process parameters for forming the second dummy gate layer 205 include: The temperature is 200-800 degrees Celsius, the air pressure is 1 torr-100 torr, the power is 300 watts to 600 watts, the gas includes HCl and H ₂ , the flow rate of HCl is 1 sccm to 1000 sccm, and the flow rate of H ₂ is 0.1slm to 50slm; When the material of the second dummy gate layer is undoped polysilicon, the gas also includes silicon source gas SiH ₄ or SiH ₂ Cl ₂ , and the flow rate of the silicon source gas is 1 sccm to 1000 sccm; when the second dummy gate layer When the material is silicon germanium, the gas also includes silicon source gas SiH ₄ or SiH ₂ Cl ₂ and germanium source gas GeH ₄ , the flow rate of the silicon source gas is 1 sccm to 1000 sccm, and the flow rate of the germanium source gas is 1 sccm- 1000 sccm. The deposition rate of the chemical vapor deposition process is controllable, so the thickness of the formed second dummy gate layer 205 can be precisely controlled by controlling the deposition time. In addition, during the chemical vapor deposition process, the polysilicon material can be doped with P-type ions or N-type ions through an in-situ doping process.

The thickness of the second dummy gate layer 205 formed by the deposition process is uniform, while the etched back first dummy gate layer 204 on the entire substrate 200 is flush with the surface of the second silicon oxide layer 210, Therefore, the surface of the second dummy gate layer 205 is flat and uniform. After the dummy gate formed by the second dummy gate layer 205 and the first dummy gate layer 204 is subsequently etched, the dummy gate located on the top surface of the fin portion 201 Grid thickness is uniform and precise.

On the basis of FIG. 11 , please refer to FIG. 12 , etch part of the first dummy gate layer 204 and the second dummy gate layer 205 until the top and sidewall surfaces of the fin 204 are exposed, forming a 201 sidewalls and dummy gates (not shown) on the top surface.

The forming process of the dummy gate is as follows: a dummy gate mask 212 is formed on the surface of the second dummy gate layer 205, and the dummy gate mask 212 defines the pattern of the dummy gate; Etching the second dummy gate layer 205 and the first dummy gate layer 204 (as shown in FIG. 10 ) until the top and sidewall surfaces of the fin 201 and the first dielectric layer 203 are exposed, forming a 201 on the sidewall and top surface, and the dummy gate on the surface of the first dielectric layer 203 . Wherein, the material of the dummy gate mask 212 is silicon nitride or silicon oxynitride.

The first dummy gate layer 204 has undergone a chemical mechanical polishing process and an etch-back process, and its surface is flush with the second silicon oxide layer 210, and the first dummy gate layer 204 and the second silicon oxide layer on the overall substrate 200 The surface of 210 is flat; the thickness of the second dummy gate layer 205 can be precisely controlled and uniform through the deposition process, and the second dummy gate layer 205 located on the surface of the first dummy gate layer 204 and the second silicon oxide layer 210 on the entire substrate 200 The surface can also be kept flat; the top surface of the dummy gate formed by etching the second dummy gate layer 205 and the first dummy gate layer 204 is uniform, and the size higher than the top of the fin portion 201 is precisely and easily controllable.

It should be noted that, after forming the dummy gate, a source region and a drain region (not shown) are formed in the fins 204 on both sides of the dummy gate; The surface of the first dielectric layer 203 and the side walls and top surfaces of the fins 201 form a second dielectric layer (not shown), and the surface of the second dielectric layer is flush with the top surface of the dummy gate; After the dielectric layer, the dummy gate is removed and an opening (not shown) is formed in the second dielectric layer; a gate dielectric layer (not shown) is formed in the opening, and a filling is formed on the surface of the gate dielectric layer. A gate electrode layer (not shown) fills the opening.

In this embodiment, the first dummy gate layer 204 is formed on the surface of the first dielectric layer 203, the fin portion 201 and the mask layer 202, and the first dummy gate layer 204 is polished by a chemical mechanical polishing process until the mask is exposed. layer 202, etch back the first dummy gate layer 204 until it is flush with the top surface of the fin portion 201, then remove the mask layer 202 and deposit the first dummy gate layer 204 with a uniform thickness on the surface of the fin portion 201 and the first dummy gate layer 204. Two dummy gate layers 205, the surface of the second dummy gate layer 205 is uniform and flat, and the thickness above the top of the fin portion 201 is precisely uniform, and the second dummy gate layer 205 and the first dummy gate layer 204 are carved The thickness of the dummy gate formed by etching is higher than the fin portion 201 and has a precise and uniform thickness, which is beneficial to stabilizing the performance of the formed device.

To sum up, after depositing the first dummy gate layer on the surface of the base and the fin, planarize the first dummy gate layer until the top of the fin is exposed, and then deposit the first dummy gate layer and the fin If the second dummy gate layer is formed on the surface of the substrate, the thickness of the second dummy gate layer can be precisely controlled by the process, and the thickness of the second dummy gate layer at different positions on the substrate can be made uniform. Subsequently, by etching the second dummy gate layer and the first dummy gate layer to form a dummy gate across the sidewall and top surface of the fin, the thickness dimension of the dummy gate formed on the top surface of the fin can be made Accurate, and the thickness of dummy gates at the tops of different fins is uniform, which improves the stability of the formed semiconductor device.

Further, the top surface of the fin part also has a mask layer, the mask layer is used to define the pattern of the fin part in the previous process, and the fin part is formed by etching with the mask layer, and the first dummy gate The pole layer is also deposited on the surface of the mask layer. The process of planarizing the first dummy gate layer is: using a chemical mechanical polishing process to polish the first dummy gate layer until the mask layer is exposed, and the mask layer is used as a polishing stop layer and protects the fins. The top is not damaged. Then, an etch-back process is used to make the surface of the first dummy gate layer flush with the surface of the fin; the etch-back process can precisely control the etching depth by adjusting the etching rate and etching time, so that the first The surface of the dummy gate layer is flush with the surface of the fin.

Further, the etching depth of the etch-back process is controlled by an advanced process control device; the advanced process control device can detect the surface of the first dummy gate layer located at different positions on the substrate, and obtain the first dummy gate after polishing. The surface height state of the layer; the measured surface state of the first dummy gate layer, combined with the parameters of the etch-back process, such as etching rate and etching time, can obtain the results of the first dummy gate layer at different positions on the substrate. The depth to be etched back ensures that the surface of the first dummy gate layer after the etch back is uniform, and then the surface of the second dummy gate layer subsequently formed on the surface of the first dummy gate layer is uniform.

Further, when the materials of the first dummy gate layer and the second dummy gate layer are different, when the second dummy gate layer is etched to expose the first dummy gate layer, the etching gas needs to be replaced to continue Etching the first dummy gate layer until the substrate is exposed, and the gas used to etch the first dummy gate layer is not easy to damage the etched second dummy gate layer, thereby ensuring the dummy across the fin. The good shape of the grid is conducive to the stable performance of the formed device.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (20)

1. A method for forming a semiconductor structure, comprising: providing a base having fins on a surface of the base; forming a first dummy gate layer on the base and the surface of the fin, the surface of the first dummy gate layer is higher than the top surface of the fin; planarizing the first dummy gate layer until the top surface of the fin is exposed; After the planarization process, forming a second dummy gate layer on the first dummy gate layer and the surface of the fin; Etching part of the first dummy gate layer and the second dummy gate layer until the top and sidewall surfaces of the fin are exposed, forming a dummy gate across the sidewall and top surface of the fin. 2. The method for forming a semiconductor structure according to claim 1, further comprising: a mask layer located on the top surface of the fin, the first dummy gate layer is also deposited on the surface of the mask layer, the The surface of the first dummy gate layer is equal to or higher than the surface of the mask layer. 3. The method for forming a semiconductor structure according to claim 2, wherein the process of planarizing the first dummy gate layer is: using a chemical mechanical polishing process to planarize the first dummy gate layer until exposed the top surface of the mask layer; after planarizing the first dummy gate layer, etch back the first dummy gate layer until the surface of the first dummy gate layer is flush with the surface of the fin; After the etching process, the mask layer is removed. 4. The method for forming a semiconductor structure according to claim 3, wherein the etch-back process is an anisotropic dry etching process, and the process parameters are: the bias power is less than 100W, and the etching gas includes CF _4. SF ₆ or NF ₃ . 5. The method for forming a semiconductor structure according to claim 3, wherein the etching depth of the etch-back process is controlled by an advanced process control device. 6. The method for forming a semiconductor structure according to claim 2, wherein the forming process of the fin portion is as follows: providing a semiconductor substrate, the semiconductor substrate being a bulk substrate; forming on the surface of the bulk substrate a mask layer; use the mask layer as a mask to etch the bulk substrate to form openings, and the bulk substrate between adjacent openings forms fins; form a first dielectric layer at the bottom of the opening, the The first dielectric layer covers part of the side wall surface of the fin. 7. The method for forming a semiconductor structure according to claim 6, wherein the material of the bulk substrate is silicon, germanium or silicon germanium. 8. The method for forming a semiconductor structure according to claim 2, wherein the forming process of the fin portion comprises: providing a semiconductor substrate, the semiconductor substrate being a semiconductor-on-insulator substrate, and the semiconductor-on-insulator substrate The bottom includes an insulating layer and a semiconductor layer located on the surface of the insulating layer, the material of the semiconductor layer is silicon or germanium; a mask layer is formed on the surface of the semiconductor layer; the semiconductor layer is etched using the mask layer as a mask layer until the surface of the insulating layer is exposed to form fins on the insulating layer. 9. The method for forming a semiconductor structure according to claim 6 or 8, further comprising: after forming the fin, forming a first silicon oxide layer on the sidewall surface of the fin by using a thermal oxidation process, the first The silicon monoxide layer has a thickness of 1 nm to 5 nm. 10. The method for forming the semiconductor structure according to claim 6 or 8, wherein the formation process of the mask layer is a multiple patterned mask process. 11. The method for forming a semiconductor structure according to claim 10, wherein when the formation process of the mask layer is a double patterned mask process, the formation process of the mask layer is: forming a sacrificial film on the surface; forming a patterned layer on a part of the surface of the sacrificial film; using the patterned layer as a mask to etch the sacrificial film until the semiconductor substrate is exposed to form a sacrificial layer; Depositing a mask film on the bottom and the surface of the sacrificial layer; etching back the mask film until the semiconductor substrate is exposed, forming a mask layer, and removing the sacrificial layer. 12. The method for forming the semiconductor structure according to claim 6 or 8, characterized in that after forming the fins, a thermal annealing process is performed, and the temperature of the thermal annealing process is 900 degrees Celsius to 1100 degrees Celsius. 13. The method for forming the semiconductor structure according to claim 2, wherein the material of the mask layer is silicon nitride, silicon oxide or silicon oxynitride. 14. The method for forming a semiconductor structure according to claim 13, further comprising: forming a second oxide layer between the top of the fin and the mask layer when the material of the mask layer is silicon nitride. silicon layer. 15. The method for forming the semiconductor structure according to claim 1, wherein the material of the first dummy gate layer is the same as or different from the material of the second dummy gate layer. 16. The method for forming a semiconductor structure according to claim 15, wherein the forming process of the first dummy gate layer or the second dummy gate layer is a chemical vapor deposition process or a physical vapor deposition process; The material of a dummy gate layer or the second dummy gate layer is doped polysilicon, undoped polysilicon, amorphous silicon, silicon germanium or amorphous carbon. 17. The method for forming a semiconductor structure according to claim 16, wherein the chemical vapor deposition process parameters for forming the second dummy gate layer are as follows: a temperature of 200-800 degrees Celsius, an air pressure of 1 Torr-100 Torr, The power is 300 watts to 600 watts, the gas includes HCl and H ₂ , the flow rate of HCl is 1 sccm to 1000 sccm, and the flow rate of H ₂ is 0.1 slm to 50 slm; when the material of the second dummy gate layer is undoped polysilicon, the The gas also includes silicon source gas SiH ₄ or SiH ₂ Cl ₂ , and the flow rate of the silicon source gas is 1 sccm to 1000 sccm; when the material of the second dummy gate layer is silicon germanium, the gas also includes silicon source gas SiH ₄ or SiH ₂ Cl ₂ and germanium source gas GeH ₄ , the flow rate of the silicon source gas is 1 sccm-1000 sccm, and the flow rate of the germanium source gas is 1 sccm-1000 sccm. 18. The method for forming a semiconductor structure according to claim 1, wherein the forming process of the dummy gate is: forming a dummy gate mask on the surface of the second dummy gate layer, and the dummy gate mask defines The pattern of the dummy gate, the material of the dummy gate mask is silicon nitride or silicon oxynitride; the second dummy gate layer and the first dummy gate layer are etched with the dummy gate mask until the fins are exposed top and side wall surfaces. 19 . The method for forming the semiconductor structure according to claim 1 , wherein before forming the first dummy gate layer, a third silicon oxide layer is deposited on the surface of the base and the sidewalls and top surfaces of the fins. 20. The method for forming a semiconductor structure according to claim 1, further comprising: after forming the dummy gate, forming a source region and a drain region in the fins on both sides of the dummy gate; After the source region and the drain region, a second dielectric layer is formed on the base surface and the sidewall and top surface of the fin, and the surface of the second dielectric layer is flush with the top surface of the dummy gate; After removing the dummy gate and forming an opening in the second dielectric layer; forming a gate dielectric layer in the opening, and forming a gate electrode layer filling the opening on the surface of the gate dielectric layer.