CN104049203B - Pin with boundary scanning and testing function and integrated circuit with same - Google Patents

Abstract

A pin with a boundary scan test function and an integrated circuit including the pin are disclosed. The pins include at least one boundary scan register, a boundary scan signal input pin, a boundary scan signal output pin, and a TAP control signal terminal receiving a boundary scan control signal from a TAP controller. Because the boundary scan register is integrated in the pins provided according to the present invention, thereby reducing the input, output and JTAG test logic of the pins in the chip implementation process outside the pins. Avoiding the negative impact on the timing caused by the position of the input, output and control signal of the JTAG test logic of the pins is conducive to the rapid convergence of the timing.

Description

Pin with boundary scan test function and integrated circuit including the pin

technical field

The invention relates to the field of integrated circuits, more specifically, to a pin with a built-in boundary scan register and an integrated circuit including the pin.

Background technique

Boundary scan technology is a test structure design method applied to digital integrated circuit devices. The so-called "boundary" means that the test circuit is arranged around the logic function circuit of the integrated circuit device, and is located near the boundary of the input, output and control pins of the device. The so-called "scanning" means that the test circuit connecting the input, output and control pins of the device is actually a set of serial shift registers. This serial shift register is called "scanning path". Input various codes composed of "0" and "1", perform "scanning" detection on the circuit, and judge whether it is correct from the output result.

FIG. 1 is a schematic diagram showing the top-level structure of an integrated circuit chip based on the prior art. As shown in Figure 1, a boundary scan register (BSR: boundary scan register) composed of registers and combinational logic is arranged near each pin (PAD) to be tested. At the same time, according to the pin is a single input, a single Output, input and output or tri-state pins and the number of boundary scan registers arranged near them are also different. For example, for a three-state pin with an input pin input, an output pin output and a control pin control as shown in FIG. 2, three boundary scan registers should be arranged near it.

As shown in FIG. 1 , all boundary scan registers are connected to the internal logic (Core) of the integrated circuit signal, and all boundary scan registers are connected in order of movement to form a JTAG scan chain. The test data input (TDI), test clock input (TCK), test mode select (TMS), test reset input (TRST) and test data output (TDO) related signals for the JTAG scan test are provided by the test access port (TAP) The controller provides or inputs to the TAP controller, so that the TAP controller realizes the control of the JTAG scan chain, thereby realizing the input, output and control signal testing of the pins. The external stimulus is sequentially shifted into each boundary scan register through the TDI of the TAP controller, and then the test is applied to the input pin of the PAD under test for testing, and finally the test results are sequentially shifted from TDO or output from the output pin of the PAD under test in parallel. . By observing the output results of TDO and the output pin of the PAD under test, it is judged whether there is a problem with the connection of the PAD.

As mentioned above, each boundary-scan register is composed of a register and combinational logic. The combinational logic separates the functional path from the test path, and the path can be switched between the functional mode and the test mode. The functional path is the connection path between the pin and the internal logic. Due to the insertion of the boundary scan register, there are multiple boundary scan register units between the pin and the internal logic, so the functional path is affected by the position of the boundary scan register.

For better timing and without affecting the functional path, the boundary scan register must be placed next to each pin to be tested during the layout and routing of the integrated circuit, especially the combinational logic inside the boundary scan register, because the combinational logic will Switching between the functional path and the test path, the position of the combinatorial logic directly affects the functional path. If the combinatorial logic of the path selection is placed far away from the pins, the functional path will be greatly affected.

Contents of the invention

In view of the above-mentioned problems in the prior art, the present invention provides a pin integrated with a boundary scan test function and an integrated circuit including the pin.

According to one aspect of the present invention, there is provided a pin for an integrated circuit, the pin includes at least one boundary scan register, a boundary scan signal input pin, a boundary scan signal output pin, and a slave test access port (TAP ) The controller receives the TAP control signal terminal of the boundary scan control signal.

Preferably, the TAP control signal terminal includes a test clock input terminal receiving a clock signal from the TAP controller and a test mode selection terminal receiving a test mode selection signal from the TAP controller.

Preferably, when the pin is an input pin, the pin includes a signal input pin for receiving a signal, and the at least one boundary scan register includes an input boundary scan connected to the input pin register.

Preferably, when the pin is an output pin, the pin also includes a signal output pin for outputting a signal, and the at least one boundary scan register includes an output boundary connected to the output pin scan registers.

Preferably, when the pins are input/output pins, the pins also include signal input pins for receiving signals and signal output pins for outputting signals, and the at least one boundary scan register Consists of an input boundary-scan register and an output boundary-scan register connected to input pins and output pins, respectively.

Preferably, when the pins are tri-state pins, the pins also include signal input pins for receiving signals, signal output pins for outputting signals, and control signal pins for receiving control signals. pins, and the at least one boundary-scan register includes an input boundary-scan register, an output boundary-scan register, and a control boundary-scan register respectively connected to the input pin, the output pin, and the control signal pin.

Preferably, the at least one boundary-scan register is a boundary-scan register based on a JTAG scan test.

Preferably, at least one boundary scan register is connected to other pins via the boundary scan signal input pin and the boundary scan signal output pin to form a JTAG scan chain.

According to another aspect of the present invention, there is provided an integrated circuit having pins as described above.

Because the boundary scan register is integrated in the pin provided according to the present invention, thereby reducing the input, output and JTAG test logic of the pin in the chip implementation process, and the insertion of the control signal outside the pin. Avoiding the negative impact on the timing caused by the position of the input, output and control signal of the JTAG test logic of the pins is beneficial to the fast convergence of the timing.

Description of drawings

These and/or other aspects and advantages of the present invention will become clearer and easier to understand through the following description of embodiments in conjunction with the accompanying drawings, wherein:

Fig. 1 is a schematic diagram showing the top-level structure of an integrated circuit chip based on the prior art;

Fig. 2 is a schematic diagram showing three-state discipline;

3 is a diagram illustrating pins integrating a boundary scan register according to an exemplary embodiment of the present invention;

4A, FIG. 4B and FIG. 4C are schematic diagrams respectively showing a control boundary scan register, an output boundary scan register and an input boundary scan register;

FIG. 5 is a diagram illustrating a top-level structure of an integrated circuit having pins integrated with a boundary scan register according to an exemplary embodiment of the present invention.

detailed description

Embodiments of the invention will now be described in detail, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like parts throughout. The embodiments are described below in order to explain the present invention by referring to the figures.

According to technical scheme of the present invention, in designing integrated circuit or pin (PAD) library unit design process, boundary scan register (BSR) is integrated in the PAD, and the BSR inside the PAD completes the connection of local JTAG scanning connection, therefore in During the chip design process, it is only necessary to insert the position-insensitive TAP control logic and connect the BSR related signals of the PAD to realize the boundary scan test circuit.

FIG. 3 is a diagram illustrating pins integrating a boundary scan register according to an exemplary embodiment of the present invention. The pin PAD shown in FIG. 3 is a three-state pin, that is, it includes an input pin input, an output pin output and a control pin control.

In addition, the pin PAD shown in FIG. 3 also integrates a boundary scan register, that is, the pin PAD also includes a first boundary scan register 110 connected to the control pin control, a second boundary scan register 110 connected to the output pin output A boundary scan register 120 and a third boundary scan register 130 connected to the input pin input.

The first boundary-scan register 110, the second boundary-scan register 120 and the third boundary-scan register 130 in FIG. 3 can be respectively implemented as a control boundary-scan register as shown in FIG. 4C shows the input boundary scan register. Since the control boundary scan register shown in FIG. 4A, the output boundary scan register shown in FIG. 4B, and the input boundary scan register shown in FIG. The structures of the registers are similar, so they are not repeated here.

In addition, the pin PAD shown in FIG. 3 may also include a boundary scan signal input pin SI and a boundary scan signal output pin SO. The boundary-scan signal input pin SI and the boundary-scan signal output pin SO are used for signal exchange by other pins, that is, signals are received from other pins via the boundary-scan signal input pin SI to the pin PAD and Signals are output from the pin PAD to other pins via the boundary scan signal output pin SO.

In addition, the pin PAD shown in FIG. 3 may further include a TAP control signal terminal CLOCK/MODE for receiving a boundary scan control signal from the TAP controller. For example, the TAP control signal terminal CLOCK/MODE includes a test clock input pin receiving a clock signal from the TAP controller and a test mode selection pin receiving a test mode selection signal from the TAP controller.

The embodiment of the tri-state pin integrated with the boundary scan register has been described above with reference to FIG. 3 . The technical solution described in conjunction with FIG. 3 is applicable to pins with only input pins, only output pins, and both input and output pins.

For example, when the pin is a pin having only input pins, it may only include an input boundary scan register connected to the input pin as the third boundary scan register 130 shown in FIG. 3 .

For example, when the pin is a pin having only an output pin, it may only include an output boundary scan register connected to the output pin as the second boundary scan register 120 shown in FIG. 3 .

For example, when the pin is a pin having an input pin and an output pin, it may include an input boundary scan register of the third boundary scan register 130 as shown in FIG. 3 connected to the input pin and an input boundary scan register connected to the output pin The pin is the output boundary scan register of the second boundary scan register 120 shown in FIG. 3 .

Next, an integrated circuit with integrated boundary scan registers will be described with reference to FIG. 5 . FIG. 5 is a schematic diagram illustrating an integrated circuit with integrated boundary scan registers according to an embodiment of the present invention.

As shown in FIG. 5 , the integrated circuit according to the embodiment of the present invention includes an internal logic CORE, a test access port (TAP) controller 200, and a plurality of pins, wherein the plurality of pins include the above described with reference to FIG. 3 Input pins, output pins, input and output pins, and tri-state pins.

Here, the TAP controller 200 has a test input input (TDI) pin, a test clock input (TCK) pin, a test mode select (TMS) pin, a test reset input (TRST) pin and a test reset input (TRST) pin for JTAG scan testing. Data Out (TDO) Pin. Since the TAP controller 200 and its pins can be implemented by a prior art TAP controller and its pins, description thereof is omitted.

Meanwhile, as mentioned above, each of the plurality of pins PAD integrated with the boundary scan register includes a boundary scan signal input pin SI and a boundary scan signal output pin SO.

The boundary-scan registers included in the multiple pins of the integrated circuit shown in Figure 5 are serially connected in sequence through their respective boundary-scan signal input pins SI and boundary-scan signal output pins SO, thereby forming a JTAG scan chain, that is, forming The TDI pin of the TAP controller → SI → SO → SI………… → SO → SI → SO → the JTAG scan chain of the TDO of the TAP controller, where SI and SO represent the scan input to the boundary scan register or Scan output from boundary scan register.

Since the JTAG scanning technology of the prior art can be applied to the JTAG scanning of the integrated circuit shown in FIG. 5 , the description of the JTAG scanning scheme of the integrated circuit shown in FIG. 5 is omitted.

According to the technical scheme of the present invention, since the boundary scan register (BSR) is integrated into the pin (PAD), the position of the boundary scan register and its internal combinatorial logic is limited in the PAD, so the layout and wiring process of the integrated circuit In , there is no need to consider the placement of BSR-related logic, and the functional path will not be affected by the location of the combinational logic, which is more conducive to fast timing convergence.

While certain embodiments of the present invention have been shown and described, it should be understood by those skilled in the art that modifications may be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents. to modify.

Claims (9)

1. a kind of pin for integrated circuit is it is characterised in that include：

At least one boundary scan register；

Boundary scan signal input pin；

Boundary scan signal output pin；And

Receive the test access port control signal end of boundary scan control signal from test access port controller.

2. pin according to claim 1 is it is characterised in that described test access port control signal end is included from test Access port controller receives the test clock input of clock signal and receives test pattern from test access port controller The test pattern of selection signal selects end.

3. pin according to claim 1 is it is characterised in that when described pin is input pin, described pin includes For the signal input pin of receipt signal, and at least one boundary scan register described includes being connected to described input pin One input boundary scan register.

4. pin according to claim 1 is it is characterised in that when described pin is output pin, described pin also wraps Include the signal output pin for output signal, and at least one boundary scan register described includes being connected to described output and draws One output boundary scan register of pin.

5. pin according to claim 1 it is characterised in that when described pin be input/output pin when, described pin Also include the signal input pin for receipt signal and the signal output pin for output signal, and at least one side described Boundary's scan register includes being connected respectively to input pin and the input boundary scan register of output pin and output boundary is swept Retouch register.

6. pin according to claim 1 is it is characterised in that when described pin is tri-state pin, described pin also wraps Include the signal input pin for receipt signal, the signal output pin for output signal and the control for receiving control signal Signal pins processed, and at least one boundary scan register described include being connected respectively to described input pin, output pin and The input boundary scan register of control signal pin, output boundary scan register and control boundary scan register.

7. pin according to claim 1 is it is characterised in that at least one boundary scan register described is based on JTAG The boundary scan register of sweep test.

8. pin according to claim 7 is it is characterised in that at least one boundary scan register is swept via described border Retouch signal input pin to be connected with other pins with boundary scan signal output pin and formed for JTAG scan chain.

9. a kind of integrated circuit of the pin having as described in any claim in claim 1-8.