CN104011848A - A through-silicon via interconnection structure and manufacturing method thereof - Google Patents

Abstract

Provided is a method for manufacturing a through silicon via interconnection structure, the method comprising the steps of: providing a semiconductor substrate (200); forming a recess hole (202) from a first surface of the semiconductor substrate (200), and forming a first insulating layer (203) on a side wall and a bottom surface of the recess hole (202), and forming a sacrificial layer (204) on the first insulating layer (203); filling a through-silicon-via conductor (205) in the recess (202), and forming a first contact pad (207) on the first surface of the semiconductor substrate (200) in electrical connection with the through-silicon-via conductor (205); thinning the semiconductor substrate (200) from a second surface of the semiconductor substrate (200) until the through-silicon via conductor (205) is exposed; removing the sacrificial layer (204) and forming a gap layer (211) between the silicon through hole conductor (205) and the first insulating layer (203); and stacking a plurality of the semiconductor substrates (200) and then bonding the semiconductor substrates. Accordingly, a through silicon via interconnect structure is provided. The manufacturing method and the interconnection structure can effectively reduce the parasitic capacitance between the silicon through hole and the semiconductor substrate (200) and effectively reduce the stress effect of the silicon through hole conductor (205) on the semiconductor substrate (200) in thermal expansion.

Description

A through-silicon via interconnection structure and manufacturing method thereof Technical field

[0001] The present invention relates to semiconductor packaging technology, in particular to a through-silicon via interconnection structure and a manufacturing method thereof. Background technique

[0002] Through-Silicon-Via (TSV) packaging technology is the latest technology for interconnection between chips by making vertical conduction between chips. Different from previous IC package bonding and stacking technologies using bumps, TSV packaging technology can maximize the density of chips stacked in three dimensions, minimize the size of the chip, and greatly improve the performance of chip speed and low power consumption. Among them, the TSV package generally includes the following steps: forming a through hole from one surface of the semiconductor substrate, and depositing an insulating layer in the through hole; filling the through hole with metal (such as copper, tungsten, etc.) to form a through silicon via; The semiconductor substrate is thinned until the TSV is exposed from the other surface of the semiconductor substrate; finally, multiple thinned semiconductor substrates are bonded together. Please refer to FIG. 1 for the TSV interconnection structure formed based on the above steps. As shown in the figure, two semiconductor substrates are taken as an example. More than two semiconductor substrates 100 are connected by TSV conductors 101, wherein the material of TSV conductors 101 is copper. There is an insulating layer 102 between the semiconductor substrate 100 and the TSV conductor 101, which is used to isolate the semiconductor substrate 100 and the TSV conductor 101, so as to prevent the two from being short-circuited. In addition, there is a filling material 103 between the two interconnected semiconductor substrates 100, and the filling material is generally an insulator, which can help to bond two adjacent semiconductor substrates 100.

[0004] The paper "3D stacked ICs using Cu TSVs and Die to Wafer Hybrid Collective" published by G. Katti et al. on the International Electron Device Meeting (International Electron Device Meeting) in Washington D.C. In bonding", the author pointed out that with the increase of TSV packaging density, the parasitic capacitance between TSV conductor and silicon substrate will cause serious RC delay; in addition, the reliability of TSV packaging technology based on copper filling The study found that the thermal expansion coefficient of copper used to interconnect chips in the through-silicon via interconnection structure is different from that of silicon. It will expand outward, causing stress on the area around the copper, and in severe cases, it will cause the chip to break

[0005] Therefore, there is an urgent need to propose a through-silicon via interconnection structure and a manufacturing method thereof that can solve the above-mentioned problems. Contents of the invention

A through-silicon via interconnection structure and its manufacturing method, through

The deformed material effectively reduces the stress effect of the TSV conductor on the semiconductor substrate during thermal expansion.

[0007]# In one aspect of the present invention, a method for manufacturing TSV interconnection is provided, the method includes the following steps:

a) providing a semiconductor substrate, the semiconductor substrate has a first surface and a second surface corresponding to the first surface;

b) forming a concave hole from the first surface of the semiconductor substrate, forming a first insulating layer on the sidewall and bottom surface of the concave hole, and forming a sacrificial layer on the first insulating layer, wherein the concave hole The cross-sectional shape of the hole can be various shapes such as circle, square, bar, polygon;

c) filling the concave hole with a conductive material to form a TSV conductor, and forming a first contact pad electrically connected to the TSV conductor on the first surface of the semiconductor substrate; d) from the Thinning the semiconductor substrate on the second surface of the semiconductor substrate until the TSV conductor and the sacrificial layer are exposed; e) removing the sacrificial layer to form a gap layer between the TSV conductor and the first insulating layer;

f) performing bonding after stacking a plurality of said semiconductor substrates.

[0008] According to another aspect of the present invention, there is also provided a method for manufacturing a TSV interconnection structure, the method comprising the following steps:

a) providing a semiconductor substrate, the semiconductor substrate has a first surface and a second surface corresponding to the first surface;

b) forming a concave hole from the first surface of the semiconductor substrate, and forming a first insulating layer on the sidewall and bottom surface of the concave hole, and forming a buffer layer on the first insulating layer; c) Filling the concave hole with a conductive material to form a TSV conductor, and forming a first contact pad electrically connected to the TSV conductor on the first surface of the semiconductor substrate; d) from the semiconductor substrate Thinning the semiconductor substrate on the second surface of the bottom until the TSV conductor and the buffer layer are exposed;

f) performing bonding after stacking a plurality of the semiconductor substrates.

[0009] Another aspect of the present invention also proposes a through-silicon via interconnection structure, which includes a semiconductor substrate, a through-silicon via conductor penetrating through the semiconductor substrate, and a A first insulating layer between the bottom and the TSV conductor, including: [0010] a buffer layer between the TSV conductor and the first insulating layer;

[0011] At least one contact pad, at least one end of the TSV is connected to the contact pad, and the contact pad is fixed on the semiconductor substrate. The substrate is interconnected by bonding between the TSV conductor and the contact pad or between two contact pads.

[0013] Wherein the buffer layer is a void, a low-K dielectric material, a porous material or a deformable material. The buffer layer has a lower Young's modulus than single crystal silicon, that is, is softer than single crystal silicon.

[0014] Compared with the prior art, the present invention has the following advantages: By forming a cavity or filling a low-K dielectric material between the TSV conductor and the semiconductor substrate, the TSV conductor and the semiconductor substrate are effectively reduced. The parasitic capacitance between the bottom, and by forming a cavity or filling a material that can absorb deformation between the TSV conductor and the semiconductor substrate, changes in temperature When the deformation of the TSV conductor is caused by the TSV, the deformation of the TSV conductor is effectively reduced to effectively reduce the stress effect of the deformation on the semiconductor substrate. Description of drawings

[0015] Other features, objects and advantages of the present invention will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:

1 is a schematic cross-sectional view of a TSV interconnection structure in the prior art;

2 is a flow chart of a method for manufacturing a TSV interconnection structure according to the present invention;

3 to 18 are schematic cross-sectional views of various stages of manufacturing a semiconductor structure according to a preferred embodiment of the present invention according to the process shown in FIG. 2 .

[0016] The same or similar reference numerals represent the same or similar components in the accompanying drawings. Detailed ways

[0017] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary, and are only used to explain the present invention, and cannot be construed as limiting the present invention.

[0018] The following disclosure provides many different embodiments or examples for implementing various configurations of the present invention. In order to simplify the disclosure of the present invention, the components and settings of specific examples are described below. Of course, they are only examples and are not intended to limit the invention. Furthermore, the present invention may repeat reference numerals and/or letters in different instances. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or arrangements discussed. In addition, the present invention provides examples of various specific processes and materials, but those of ordinary skill in the art may realize the applicability of other processes and/or the use of other materials. Additionally, configurations described below in which a first feature is "on" a second feature may include embodiments where the first and second features are formed in direct contact, and may include additional features formed between the first and second features. In an embodiment such that the first and second features may not be in direct contact. It should be noted that components illustrated in the figures are not necessarily drawn to scale. The present invention omits the modification of known components and processing techniques and processes The description is made so as not to unnecessarily limit the invention.

[0019] The present invention provides a method for manufacturing a through-silicon via interconnection structure, please refer to FIG. 2 , and FIG. 2 is a flowchart of a method for manufacturing a through-silicon via interconnection structure according to the present invention. In the following, the method shown in FIG. 2 will be specifically described in conjunction with FIGS. 3 to 18. It should be noted that, in the stage, the through-silicon vias completed before the Back End of Line (BEOL) step are generally referred to as through-first vias, and the through-silicon vias performed after the BEOL step are generally referred to as through-last through-holes. Hole, the method for manufacturing the TSV interconnection structure provided by the present invention will be described below only by taking the through hole as an example.

[0020] First, step S101 is performed to provide a semiconductor substrate 200, the semiconductor substrate 200 has a first surface and a second surface corresponding to the first surface.

[0021] Specifically, as shown in FIG. 3, in this embodiment, the semiconductor substrate 200 is a bulk silicon substrate on which an active region has been formed, wherein the semiconductor substrate 200 has a first surface and a The second surface corresponding to the first surface, the active region is located below the first surface of the semiconductor substrate 100 (as shown by the dotted line mark in the figure), which may include various NMOS devices, PMOS devices , and/or other integrated circuits. In other embodiments, the semiconductor substrate 200 may also be an SOI (silicon-on-insulator) substrate or a substrate containing III-V semiconductor materials. The thickness of the semiconductor substrate 200 ranges from 400 μm to 800 μm. In addition, there is usually a dielectric layer 201 on the first surface of the semiconductor substrate 200 for protecting the active region in the semiconductor substrate 200, and the material of the dielectric layer 201 includes silicon dioxide, silicon nitride One or any combination of them, and other suitable dielectric materials.

[0022] Next, step S102 is performed, forming a concave hole 202 from the first surface of the semiconductor substrate 200, and forming a first insulating layer 203 on the sidewall and bottom surface of the concave hole 202, and forming a first insulating layer 203 on the first surface of the semiconductor substrate 200. A sacrificial layer 204 is formed on an insulating layer 203 .

[0023] Specifically, as shown in FIG. 4, a recessed hole 202 is formed from the first surface of the semiconductor substrate 200 using, for example, deep plasma etching, KOH solution wet etching or laser processing, wherein, The cross section of the concave hole 202 (section parallel to the first surface of the semiconductor substrate 200) is generally circular, and the diameter of the concave hole 202 ranges from 2 μ ιη-10 μ ιη, the depth range is 20 μm-100 μm. The cross-section of the pit 202 may also be in other shapes such as square, strip, polygon, etc. as required.

[0024] After the concave hole 202 is formed, a first insulating layer 203 and a sacrificial layer 204 are sequentially deposited to cover the semiconductor substrate 200 and the sidewall and bottom surface of the concave hole 202, please refer to FIG. 5 . Wherein, the material of the first insulating layer 203 is preferably silicon nitride, and its thickness ranges from 10 nm to 150 nm. Since the sacrificial layer 204 will be removed in the subsequent process, the material of the sacrificial layer 204 is preferably easy to etch, and is compatible with the first insulating layer 203 and the TSV conductor (which will be processed in the subsequent process) Generate) different materials for removal by selective etching. Therefore, one of polysilicon, amorphous silicon, germanium-silicon alloy, oxide, silicon-carbon alloy or any combination thereof can be used as the material of the sacrificial layer 204. The sacrificial layer 204 has a thickness in the range of 0.2 μιη-1 μιη.

[0025] Then, step S103 is performed, filling the concave hole 202 with a conductive material to form a TSV conductor 205, and forming a first contact pad 207 electrically connected to the TSV conductor 205.

[0026] Specifically, first form a through-silicon via conductor, as shown in FIG. conductive material. In this embodiment, the conductive material is copper, and in other embodiments, the conductive material may also include one of nickel, tungsten or any combination thereof. After filling, at least planarize the conductive material until the upper surface of the conductive material is flush with the upper surface of the sacrificial layer 204 (in this document, the term "flush" means the gap between the two The height difference is within the allowable range of the process error), so as to form the TSV conductor 205 . In order to make the volume of the finally formed chip as small as possible, preferably, the conductive material, the sacrificial layer 204 and the first insulating layer 203 are planarized until the dielectric layer 201 is exposed (in other embodiments, if the semiconductor substrate If there is no dielectric layer on the first surface of the bottom 200, the conductive material and the sacrificial layer 204 are planarized until the first insulating layer 203 is exposed, and the first insulating layer 203 is reserved for isolating the semiconductor substrate 200 and protecting the existing source region), at this time, the sacrificial layer 204 only exists in the concave hole 202 (please refer to FIG. 6 ), and is located between the TSV conductor 205 and the first insulating layer 203.

[0027] Next, referring to FIG. 7, on the dielectric layer 201 by, for example, deposition, etc. A second insulating layer 206 is formed, wherein the material of the second insulating layer 206 is preferably one of silicon nitride, oxide or any combination thereof, and its thickness ranges from 1 μιη to 10 μιη. Referring to FIG. 8, the second insulating layer 206 is etched to form a first opening 300, wherein the first opening 300 exposes the TSV conductor 205, the sacrificial layer 204, and a partial area around the sacrificial layer 204. , In this embodiment, the cross section of the first opening 300 (the cross section parallel to the first surface of the semiconductor substrate 200) is circular, and its diameter ranges from 8 μm to 15 μm. The cross section of the first opening 300 may also be in other shapes such as square, strip, polygon, etc. as required. Referring to FIG. 9, preferably a seed layer (not shown) is first formed in the first opening 300, and then a conductive material is filled in the first opening 300 by, for example, electroplating, and the planarization operation is performed to make the The upper surface of the conductive material is flush with the upper surface of the second insulating layer 206 to form a first contact pad 207 electrically connected to the upper end of the TSV conductor 205, wherein, in this embodiment, the The material of the first contact pad 207 is the same as that of the TSV conductor 205, which is metal copper. In other embodiments, the material of the first contact pad 207 can also be the same as that of the TSV conductor 205. Different metals, such as aluminum, etc. The formation of the first contact pad 207 enables the TSV conductor 205 to be fixed to the semiconductor substrate 200.

[0028] In step S104, the semiconductor substrate 200 is thinned from the second surface of the semiconductor substrate 200 until the TSV conductor 205 is exposed.

[0029] Specifically, as shown in FIG. 10, the semiconductor substrate 200 is fixed on a carrier 208, wherein the carrier 208 can be a silicon wafer, glass or plastic. The first contact pad 207 on the first surface of the semiconductor substrate 200 is attached to the carrier 208, exposing the second surface of the semiconductor substrate 200. Then, the second surface of the semiconductor substrate 200 is ground or planarized until the TSV conductor 205 is exposed. Preferably, after the TSV conductor 205 is exposed, the semiconductor substrate 200, the first insulating layer 203 and the sacrificial layer 204 may be further etched by selective etching without etching the The TSV conductor 205 is such that a part of the TSV conductor 205 protrudes from the semiconductor substrate 200 , the first insulating layer 203 and the sacrificial layer 204 , wherein the selective etching depth ranges from 50 nm to 500 nm. After the planarization process exposes the TSV conductor 205, it is also possible to selectively only The semiconductor substrate 200 continues to be etched without etching the first insulating layer 203, the sacrificial layer 204 and the TSV conductor 205, so that part of the TSV conductor 205, the sacrificial layer 204 and the TSV The first insulating layer 203 protrudes from the semiconductor substrate 200 .

[0030] Next, as shown in FIG. 11, an insulating material is deposited to cover the second surface of the semiconductor substrate 200, the TSV conductor 205, the sacrificial layer 204 and the first insulating layer 203, and the insulating material is planarized until exposed The through-silicon via conductor 205, and then remove the insulating material located on the lower side of the sacrificial layer 204 by, for example, photolithography; or in the second case described above, the through-silicon via conductor 205 is flush with the lower end of the sacrificial layer 204 When the insulating material is planarized until the TSV conductor 205 is exposed, the sacrificial layer 204 is also exposed, and the insulating material on the underside of the sacrificial layer 204 does not need to be removed by photolithography, so that the semiconductor substrate A third insulating layer 209 is formed on the second surface of the bottom 200 . Wherein, the material of the third insulating layer 209 is the same as that of the first insulating layer 203, or may be different from the material of the first insulating layer 203. When a plurality of semiconductor substrates with TSV structures are subsequently bonded together, the third insulating layer 209 can effectively isolate two adjacent semiconductor substrates to prevent the second The surface is in contact with a first contact pad over another semiconductor substrate, thereby causing a short circuit.

[0031] Then, step S105 is performed, the sacrificial layer 204 is removed, and a gap layer 211 is formed between the TSV conductor 205 and the first insulating layer 203.

[0032] Specifically, since the material of the sacrificial layer 204 has different selectivity from the TSV conductor 205 and the first insulating layer 205, for example, wet etching can be used to selectively remove The sacrificial layer 204 between the conductor 205 and the first insulating layer 203, so as to form a gap layer 211 between the TSV conductor 205 and the first insulating layer 203, as shown in FIG. 12 . Because the TSV conductor 205 is fixed to the semiconductor substrate 200 through the first contact pad 207, after removing the sacrificial layer 204, the TSV conductor 205 will not be separated from the semiconductor substrate 200 .

[0033] In step S106, bonding is performed after forming the semiconductor substrate 200 stacked in the above steps.

[0034] Specifically, as shown in FIG. 13, firstly, the semiconductor substrate 200 and the carrier 208, and then accurately align a plurality of thinned semiconductor substrates 200, and connect the lower end of the TSV conductor 205 of one semiconductor substrate to the other semiconductor substrate through copper-copper bonding, etc. The first contact pad 207 above the bottom first surface is bonded, so that multiple semiconductor substrates 200 are connected to form a through-silicon via interconnection structure (Figure 13 only shows a schematic diagram of the interconnection of two semiconductor substrates , the dotted line represents the interconnection surface between two semiconductor substrates), wherein, bonding is a technology well known to those skilled in the art, and will not be repeated here.

[0035] Optionally, in order to make the two adjacent semiconductor substrates more firmly bonded, after forming the third insulating layer 209, it is also possible to further form an electrical connection with the lower end of the TSV conductor 205. The connected second contact pad 212, please refer to FIG. 14 to FIG. 17, its formation steps are as follows: Deposit an insulating material on the second surface of the thinned semiconductor substrate 200 to form a fourth insulating layer 210, wherein, the first The material of the four insulating layers 210 is preferably one of silicon nitride and silicon oxide or any combination thereof, and its thickness ranges from 1.5 μm to 10 μm. Etching the fourth insulating layer 210 and stopping at the third insulating layer 209 to form a second opening 301, wherein, similar to the first opening 300 (refer to FIG. 8 ), the second opening 301 exposes the The TSV conductor 205, the sacrificial layer 204, and a partial area around the sacrificial layer 204; Next, as shown in FIG. A gap layer 21 1 is formed between the insulating layers 203; after the gap layer 21 1 is formed, as shown in FIG. 16 , preferably a seed layer ( not shown), and fill the second opening 301 with a conductive material by, for example, electroplating, and select conditions that are not easy to fill holes through process control, so that the gap layer 21 1 can be basically not filled, and most of it remains as gap, and then through a planarization operation, the upper surface of the conductive material is flush with the upper surface of the fourth insulating layer 210 to form a second contact pad 212 electrically connected to the lower end of the TSV conductor 205, Wherein, the material of the second contact pad 212 may be the same as that of the first contact pad 207, or may be different from the material of the first contact pad 207; finally, as shown in FIG. 17, the A plurality of semiconductor substrates 200 are stacked and interconnected (FIG. 17 only shows a schematic diagram of the interconnection of two semiconductor substrates, and the dotted line indicates the interconnection surface between the two semiconductor substrates), wherein, two adjacent semiconductor substrates Bottom 200, half The second contact pad 212 below the second surface of the conductor substrate 200 is bonded to the first contact pad 207 above the first surface of another semiconductor substrate 200. The formation of the second contact pad 212 not only further fixes the TSV conductor 205 and the semiconductor substrate 200, but also effectively increases the bonding area between the TSV conductors of the two semiconductor substrates. , thereby ensuring the firmness of the TSV interconnection structure.

[0036] Optionally, after the void layer 211 is formed between the TSV conductor 205 and the first insulating layer 203, the void layer 211 can also be filled with low K dielectric material 213 or material 213 that can absorb deformation, as shown in FIG. 18 . Wherein, the low-K dielectric material 213 includes one of fluorine-doped silicon oxide, carbon-doped silicon oxide, porous silicon oxide, porous carbon-doped silicon oxide or any combination thereof. The material 213 capable of absorbing deformation includes one of porous silicon, porous silicon oxide, polymer or any combination thereof. The void layer 211 or the low-K dielectric material layer 213 filled in the void layer 211 or the material layer 213 capable of absorbing deformation can be referred to as buffer layers 211, 213.

[0037] After the above steps are completed, a gap layer is formed between the semiconductor substrate and the TSV conductor or a low-K dielectric material is filled, so that the semiconductor substrate and the TSV can be effectively lowered. The parasitic capacitance between the TSV conductors; and, a gap layer 211 is formed between the semiconductor substrate and the TSV conductors or filled with a material that can absorb deformation, so that the TSV can be caused by temperature changes When the hole conductor is deformed, the deformation of the TSV conductor is absorbed to effectively reduce the stress effect of the deformation on the semiconductor substrate.

[0038] In the embodiment described above, the step of forming the sacrificial layer 204 may also be replaced by forming a buffer layer 204 that is not subsequently removed, and the material of the buffer layer 204 may be a single-layer or multi-layer structure, Some of these materials use the aforementioned low-K dielectric materials, deformable materials or combinations thereof. In this way, the subsequent steps of removing the sacrificial layer to form a void layer and filling the low-K dielectric material or deformable material can be omitted.

[0039] Correspondingly, the present invention also provides a through-silicon via interconnection structure, please refer to FIG. 205 between the first insulating layer 203, wherein, in this embodiment, the TSV The material of the body 205 is copper. In other embodiments, the material of the TSV conductor 205 can also be one of nickel, tungsten or any combination thereof; between the TSV conductor 205 and the first There is a buffer layer between the insulating layers 203, such as a gap layer 211; there is a first contact pad 207, and one end of the TSV conductor 205 is electrically connected to the first contact pad 207, and passes through the first contact pad 207 Fixing with the semiconductor substrate 200, wherein the material of the first contact pad 207 is preferably the same as the material of the TSV conductor 205, and may also be other materials different from the material of the TSV conductor 205. Conductive material; the two or more semiconductor substrates are interconnected by bonding the TSV conductor 205 and the first contact pad 207, that is, two semiconductor substrates interconnected as shown in FIG. 13 As shown in the bottom 200, the lower end of the through-silicon via conductor 205 of one semiconductor substrate 200 is bonded to the first contact pad 207 above the first surface of the other semiconductor substrate 200 (the dotted line indicates the gap between the two semiconductor substrates 200 interconnection surface), thereby forming a through-silicon via interconnection structure.

[0040] Optionally, please refer to FIG. 17, the TSV interconnection structure provided by the present invention further includes a second contact pad 212, and the other end of the TSV conductor 205 is electrically connected to the second contact pad 212. connected, and further fixed with the semiconductor substrate 200 through the second contact pad 212 . In addition, the second contact pad 212 can also effectively increase the bonding area between the TSV conductors of the two interconnected semiconductor substrates, thereby ensuring the firmness of the TSV interconnection structure. The material of the second contact pad 212 may be the same as that of the first contact pad 207, or it may be different.

[0041] Optionally, please refer to FIG. 18, the buffer layer between the TSV conductor 205 and the first insulating layer 203 can also be, for example, a low-K dielectric material layer 213 that can absorb deformation Material layer 213, or a combination thereof, wherein the low-K dielectric material layer 213 includes one of fluorine-doped silicon oxide, carbon-doped silicon oxide, porous silicon oxide, porous carbon-doped silicon oxide, or any combination thereof ; The material layer 213 capable of absorbing deformation includes one of porous silicon, porous silicon oxide, polymer or any combination thereof.

[0042] The through-silicon via interconnection structure provided by the present invention is layered with the traditional through-silicon via interconnection structure, for example, a gap layer or a low-K dielectric material layer, thereby effectively reducing the contact between the semiconductor substrate and parasitic capacitance between TSV conductors; moreover, due to the semiconductor substrate and A gap layer is formed between the TSV conductors or a material that can absorb deformation is filled, so that when the temperature changes and the TSV conductor deforms, the deformation of the TSV conductor can be effectively reduced by absorbing the deformation. stress on the semiconductor substrate.

[0043] Wherein, the structural composition, materials, and forming methods of each part in each embodiment of the TSV interconnection structure can be the same as those described in the foregoing embodiment of the method for forming the TSV interconnection structure, and will not be repeated here.

[0044] Although the exemplary embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and modifications can be made to these embodiments without departing from the spirit of the present invention and the scope of protection defined by the appended claims . For other examples, those skilled in the art should easily understand that the sequence of process steps can be changed while maintaining the protection scope of the present invention.

[0045] In addition, the scope of application of the present invention is not limited to the process, mechanism, manufacture, material composition, means, methods and steps of the specific embodiments described in the specification. From the disclosure of the present invention, those of ordinary skill in the art will easily understand that for the processes, mechanisms, manufacturing, material compositions, means, methods or steps that currently exist or will be developed in the future, they are implemented in accordance with the present invention Corresponding embodiments described which function substantially the same or achieve substantially the same results may be applied in accordance with the present invention. Therefore, the appended claims of the present invention are intended to include these processes, mechanisms, manufacturing, material compositions, means, methods or steps within their protection scope.

Claims (18)

1. Claim

   1. a kind of manufacture method of silicon through hole interconnection structure, this method comprises the following steps：A) Semiconductor substrate (200) is provided, the Semiconductor substrate (200) has first surface and the second surface corresponding with the first surface；

   B) from the first surface formation shrinkage pool (202) of the Semiconductor substrate (200), and the first insulating barrier (203) is formed on the side wall of the shrinkage pool (202) and bottom surface, and form sacrifice layer (204) on first insulating barrier (203);The first engagement pad (207) being electrically connected with the silicon hole conductor (205) is formed on the first surface of the Semiconductor substrate (200);

   D) Semiconductor substrate (200) is thinned from the second surface of the Semiconductor substrate (200), until the exposure silicon hole conductor (205) and sacrifice layer（204 ) ；

   E) sacrifice layer (204) is removed, void layer (211) is formed between the silicon hole conductor (205) and the first insulating barrier (203);

   F) multiple Semiconductor substrates (200) are stacked into laggard line unit to close.

   2. manufacture method according to claim 1, wherein, also include after the step e)：G) low-K dielectric material (213) is filled in the void layer (211) or the material (213) of deformation can be absorbed.

   3. manufacture method according to claim 2, wherein：

   The low-K dielectric material (213) includes fluorine-doped silica, carbon doped silicon oxide, porous silica, one kind of porous carbon doped silicon oxide or its any combinations；

   The material (213) that deformation can be absorbed includes one kind or its any combination in porous silicon, porous silica, polymer.

   4. manufacture method according to claim 1, wherein：

   There is active area below the first surface of the Semiconductor substrate (200).

   5. manufacture method according to claim 1 or 2, wherein：

   The material of the sacrifice layer (204) include polysilicon, non-crystalline silicon, germanium-silicon alloy, oxide, One kind or its any combination in silicon-carbon alloy.

   6. manufacture method according to claim 1 or 2, wherein, the thickness range of the sacrifice layer (204) is 0.2 μm -1 μm.

   7. manufacture method according to claim 1 or 2, wherein, in the shrinkage pool（202) also include the step of filling conductive material formation silicon hole conductor in：

   In the surface deposited seed layer of the sacrifice layer (204)；

   Conductive material is filled to the shrinkage pool (202)；

   Planarize the conductive material and the Semiconductor substrate（200) first surface or the first insulating barrier (203) upper surface flush, form silicon hole conductor (205).

   8. manufacture method according to claim 1 or 2, wherein, the step of forming the first engagement pad being electrically connected with the silicon hole conductor also includes：

   The second insulating barrier (206) is formed to cover the first surface of the Semiconductor substrate (200)；Etch second insulating barrier (206) and form the first opening（300), with the region of the exposure silicon hole conductor (205), the sacrifice layer (204) and at least partly described sacrifice layer (204) periphery；In the described first opening（300) filling conductive material in；

   The conductive material is planarized, makes its upper surface and the second insulating barrier (206) upper surface flush, the first engagement pad (207) is formed.

   9. manufacture method according to claim 1, the step e) includes：

   The 4th insulating barrier (210) is formed to cover the second surface of the Semiconductor substrate (200)；Etch the 4th insulating barrier (210) and form the second opening（301), with the region of the exposure silicon hole conductor (205), the sacrifice layer (204) and at least partly described sacrifice layer (204) periphery；Remove the sacrifice layer (204) formation void layer（211 ) ；

   In the described second opening（301) filling conductive material in；

   The conductive material is planarized, makes its upper surface and the 4th insulating barrier (210) upper surface flush, the second engagement pad (212) being electrically connected with the silicon hole conductor (205) is formed.

   10. manufacture method according to claim 9, wherein removing the sacrifice layer (204) formation void layer（211) the step of and described second opening（301) also include between the step of conductive material is filled in：

   Low-K dielectric material (213) is filled in the void layer (211) or deformation can be absorbed Material (213).

   11. manufacture method according to claim 1, also includes between the step d) and the step e)：

   Dl) in second surface the 3rd insulating barrier (209) of formation of the Semiconductor substrate (200).

   12. manufacture method according to claim 1, also includes between the step d) and the step e)：

   D2) second surface of the Semiconductor substrate (200) to being exposed is performed etching so that the silicon hole conductor（205) second surface from the Semiconductor substrate (200) highlights.

   13. a kind of manufacture method of silicon through hole interconnection structure, this method comprises the following steps：A) Semiconductor substrate (200) is provided, the Semiconductor substrate (200) has first surface and the second surface corresponding with the first surface；

   B) from the first surface formation shrinkage pool (202) of the Semiconductor substrate (200), and the first insulating barrier (203) is formed on the side wall of the shrinkage pool (202) and bottom surface, and form Slow on first insulating barrier (203) and rush layer；The first engagement pad (207) being electrically connected with the silicon hole conductor (205) is formed on the first surface of the Semiconductor substrate (200);

   D) Semiconductor substrate (200) is thinned from the second surface of the Semiconductor substrate (200), until the exposure silicon hole conductor (205) and Slow rush layer；

   F) multiple Semiconductor substrates (200) are stacked into laggard line unit to close；

   The material that wherein described Slow rushes layer includes low-K dielectric material or can absorb the material of deformation.

   14. manufacture method according to claim 13, wherein：

   The low-K dielectric material includes fluorine-doped silica, carbon doped silicon oxide, porous silica, one kind of porous carbon doped silicon oxide or its any combinations；

   The material that deformation can be absorbed includes one kind or its any combination in porous silicon, porous silica, polymer.

   15. a kind of silicon through hole interconnection structure, the silicon through hole interconnection structure includes Semiconductor substrate (200), the silicon hole conductor (205) through the Semiconductor substrate (200) and positioned at the Semiconductor substrate (200) the first insulating barrier (203) between silicon hole conductor (205), it is characterised in that including：Slow between the silicon hole conductor (205) and first insulating barrier (203) rushes layer (211,213)；

   At least one engagement pad (207,212), at least one end of the silicon hole conductor (205) is connected with the engagement pad (207,212), and is fixed by the engagement pad (207,212) with the Semiconductor substrate (200)；And bond together to form interconnection between the engagement pad (207) or between two engagement pads (207).

   16. structure according to claim 15, wherein：

   The Slow rushes layer（211st, 213) be void layer (211), low-K dielectric material layer (213) or the material layer (213) of deformation can be absorbed.

   17. structure according to claim 16, wherein：

   The low-K dielectric material layer (213) includes fluorine-doped silica, carbon doped silicon oxide, porous silica, one kind in porous carbon doped silicon oxide or its any combinations.

   18. structure according to claim 16, wherein：

   The material layer (213) that deformation can be absorbed includes one kind or its any combination in porous silicon, porous silica, polymer.