CN104009032A - Cell and macro placement on fin grid - Google Patents
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- CN104009032A CN104009032A CN201410064299.7A CN201410064299A CN104009032A CN 104009032 A CN104009032 A CN 104009032A CN 201410064299 A CN201410064299 A CN 201410064299A CN 104009032 A CN104009032 A CN 104009032A
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Abstract
A die includes at least one standard cell, which includes a first boundary and a second boundary opposite to the first boundary. The first boundary and the second boundary are parallel to a first direction. The at least one standard cell further includes a first plurality of FinFETs including first semiconductor fins parallel to the first direction. The die further includes at least one memory macro, which has a third boundary and a fourth boundary opposite to the third boundary. The third boundary and the fourth boundary are parallel to the first direction. The at least one memory macro includes a second plurality of FinFETs including second semiconductor fins parallel to the first direction. All semiconductor fins in the at least one standard cell and the at least one memory macro have pitches equal to integer times of a minimum pitch of the first and the second semiconductor fins.
Description
The cross reference of related application
The present invention requires following in the 61/770th of interim submission on February 27th, 2013, the rights and interests of No. 224 U.S. patent applications, its title is " Cell and Macro Placement on Fin Grid ", and this patent application is hereby expressly incorporated by reference with its full content.
Technical field
The present invention relates to semiconductor applications, more specifically, the present invention relates to unit and grand layout on a kind of fin grid.
Background technology
Scaled all the more and more and more higher to the requirement of integrated circuit speed along with integrated circuit, requires transistor to have increasing drive current and more and more less size.In order to meet these conflicting requirements, develop fin formula field effect transistor (FinFET).FinFET has larger groove width than smooth transistor.The groove that comprises part on the sidewall that is positioned at semiconductor fin by formation and be positioned at the part on the end face of semiconductor fin increases groove width.Because transistorized drive current is directly proportional to groove width, so the drive current of FinFET is higher than the drive current of planar transistor.
It is more and more less that FinFET is also made, and the fin of FinFET is made more and more thinner.In order to form this less fin, use special optical technology, such as, diffraction and interference.This technique that causes forming fin is more complicated.
Summary of the invention
In order to solve existing problem in prior art, according to an aspect of the present invention, a kind of tube core is provided, comprise: at least one standard cell, comprise: the first border and the second boundary with respect to described the first border, wherein, described the first border and described the second boundary are parallel to first direction; Multiple the first fin formula field effect transistors (FinFET), comprise the first semiconductor fin that is parallel to described first direction; And at least one memory macro, comprising: the 3rd border and the 4th border with respect to described the 3rd border, wherein, described the 3rd border and described the 4th border are parallel to described first direction; With multiple the 2nd FinFET, comprise the second semiconductor fin that is parallel to described first direction, wherein, the spacing of all semiconductor fin in all semiconductor fin and described at least one memory macro in described at least one standard cell is equal to the integral multiple of the minimum spacing of described the first semiconductor fin and described the second semiconductor fin.
In described tube core, the second distance between the distance of first between described the first border and described the second boundary and described the 3rd border and described the 4th border equals the integral multiple of described minimum spacing.
In described tube core, also comprise: at least one simulation is grand, comprising: the 5th border and hexagon circle with respect to described the 5th border, wherein, described the 5th border and described hexagon circle are parallel to described first direction; And multiple the 3rd FinFET, comprise the 3rd semiconductor fin that is parallel to described first direction, wherein, the spacing of all semiconductor fin during described at least one simulation is grand is equal to the integral multiple of described minimum spacing.
In described tube core, also comprise:
(I/O) is grand at least one I/O, comprising: the 5th border and hexagon circle with respect to described the 5th border, and wherein, described the 5th border and described hexagon circle are parallel to described first direction; And multiple the 3rd FinFET, comprise the 3rd semiconductor fin that is parallel to described first direction, wherein, the spacing of all semiconductor fin during described at least one IO is grand is equal to the integral multiple of described minimum spacing.
In described tube core, the all semiconductor fin substantially of all FinFET in described tube core be longitudinally all parallel to described first direction, and all spacing substantially of all semiconductor fin of all FinFET in described tube core are equal to the integral multiple of described minimum spacing.
In described tube core, all semiconductor fin of all FinFET in described tube core be longitudinally all parallel to described first direction, and all spacing of all semiconductor fin of all FinFET in described tube core are equal to the integral multiple of described minimum spacing.
In described tube core, all semiconductor fin substantially of all FinFET in described tube core be longitudinally all not parallel to second direction, described second direction is perpendicular to described first direction.
According to a further aspect in the invention, provide a kind of tube core, having comprised: standard cell; Grand, be selected from substantially by memory macro, simulate group grand, that I/O is grand and their combination forms; And fin formula field effect transistor (FinFET), be arranged in described standard cell and described grand, wherein, the all semiconductor fin substantially that are used to form all FinFET in described tube core are all parallel to first direction, and the spacing of described all semiconductor fin is equal to the integral multiple of the minimum spacing in described spacing, wherein, described minimum spacing is spacing minimum in described all spacing of described all semiconductor fin.
In described tube core, describedly grandly comprise described memory macro, and described memory macro comprises static random access memory (SRAM) unit.
In described tube core, described memory macro comprises the first border and the second boundary that are parallel to described first direction, and distance between described the first border and described the second boundary equals the integral multiple of described minimum spacing.
In described tube core, describedly grandly comprise that described simulation is grand, and described simulation is grand comprises that operational amplifier is grand.
In described tube core, described simulation is grand comprises first border and the second boundary parallel with described first direction, and distance between described the first border and described the second boundary equals the integral multiple of described minimum spacing.
In described tube core, describedly grandly comprise that described IO is grand, and described IO is grand comprises that Electrostatic Discharge is grand.
In described tube core, in described tube core, substantially do not have semiconductor fin longitudinally perpendicular to described first direction.
According to another aspect of the invention, a kind of method is provided, comprise: standard cell is arranged in tube core layout, use computer to carry out the step of arranging described standard cell, wherein, the first border of described standard cell and the second boundary are aimed at first grid ruling and second gate ruling respectively, and grid is distributed in whole described tube core layout; And be arranged in described tube core layout grand, described the 3rd grand border and the 4th border align with the 3rd gridline and the 4th gridline respectively, and described first grid ruling, described second gate ruling, described the 3rd gridline and described the 4th gridline belong to the gridline of the grid with consistent spacing, and be describedly grandly selected from by memory macro, simulate group grand, that I/O is grand and their combination forms.
In described method, after arranging described standard cell and described grand step, all fins of described standard cell and described all fin formula field effect transistors (FinFET) in grand are all aimed at gridline.
In described method, in the time that the design of described tube core layout completes, all fins of all FinFET in described tube core layout are all aimed at gridline.
In described method, the described grand memory macro that comprises.
In described method, described grand comprise simulation grand.
In described method, describedly grandly comprise that I/O (IO) is grand.
Brief description of the drawings
For comprehend embodiment and advantage thereof, the existing description of carrying out in connection with accompanying drawing as a reference, wherein:
Fig. 1 shows the circuit in tube core layout according to the tube core layout of exemplary embodiment and layout;
Fig. 2 shows according to the semiconductor element of exemplary embodiment and is manufactured on the circuit in this tube core; And
Fig. 3 schematically shows computer for arranging tube core layout and for storing the layout storage medium of tube core layout.
Embodiment
Discuss manufacture and the use of various embodiments of the present invention below, in detail.But, should be appreciated that, the invention provides many applicable concepts that can realize in various specific environments.The specific embodiment of discussing only shows to be manufactured and uses concrete mode of the present invention, limits the scope of the invention and be not used in.
A kind of semiconductor element is provided and has been formed on integrated circuit wherein and forms the method for this semiconductor element according to multiple exemplary embodiments.Show the interstage that forms this tube core.Discuss the modification of embodiment.In multiple views and illustrative embodiment, similarly reference number is used to represent similar element.
Fig. 1 shows the deposition step in integrated circuit (IC) design.According to some embodiment, use computer 10(Fig. 3) carry out this deposition step, computer run be the software of designing integrated circuit.This software comprises circuit layout instrument, and this instrument has to be arranged and wiring function.Layout tool is configured to arrange standard cell and grand, and they are through pre-designed functional circuit.In whole explanation, term " standard cell " and " grand " refer to the complete pre-designed unit of process of layout.When term " standard cell " is used for relating to little unit substantially, and that term " grand " is used for relating to is substantially large while thering is no multi-purpose unit, also uses interchangeably term " standard cell " and " grand ".In standard cell and the grand circuit storehouse that is all stored in database form.In addition, standard cell and grand (and corresponding database) are all stored in Fig. 3 such as hard disk drive 12() tangible storage medium in.12 electrical connections of computer 10 and hard disk drive and signal are connected, and can be from hard disk drive 12 search criteria unit and grand in execution layout.
Fig. 1 shows the tube core layout 20 designing by circuit design insturment.Tube core layout 20 is the layout of tube core and operation in computer 10.Tube core layout 20 can be a part for wafer layout (not shown), and this wafer layout comprises multiple identical tube core layouts 20.As shown in Figure 2, in tube core/wafer 40, manufacture the design circuit in wafer/tube core layout 20.Again with reference to figure 1, layout 20 comprises the many lines that extend on directions X 24.Line 24 is distributed in whole tube core layout 20 and has same intervals P1.In whole explanation, interval (spacing) P1 is called spacing (pitch) P1.In certain embodiments, layout 20 also comprises the many lines 26 that extend in the Y direction, and Y-direction is perpendicular to directions X.Line 26 can also distribute and have consistent spacing P2 in whole layout 20.Spacing P1 can equal, be greater than or less than spacing P2.In optional embodiment, tube core layout 20 does not comprise line 26.Line 24 and 26 is hereinafter referred to as gridline.Line 24 and 26(Fig. 1) on the screen of computer 10, be visual.
Such as standard cell 100, memory macro 200, simulate grand 300 and the integrated circuit of I/O (IO) grand 400 arrange with layout 20 and aim at gridline 24.For example, standard cell 100 can comprise inverter, NOR door, NAND door, XOR gate etc.Memory macro 200 can comprise that static random access memory (SRAM) is grand, dynamic random access memory (DRAM) is grand etc.SRAM is grand or DRAM is grand comprises the sram cell or the DRAM unit that form array, and can comprise the support circuit for supporting memory array operation.Support that circuit for example can comprise, row decoder, sense amplifier, power control circuit and level shift circuit.Simulate grand 300 and can comprise phase-locked loop, operational amplifier, power amplifier etc.IO grand 400 can comprise high speed serializer/and change device (serial parallel and serializer), universal I/O piece, Electrostatic Discharge circuit etc.Circuit 100,200,300 and 400 can be pre-designed and be copied to the position of the needs of layout 20, but some in circuit 100,200,300 and 400 can be also that original place layout is in tube core layout 20 instead of pre-designed and arrange step by step.Fig. 1 shows the exemplary deposition step of one of memory cell 120.In certain embodiments, standard cell 100, memory macro 200 and simulate grand 300 and be included in core circuit region 500, and IO grand 400 can be configured in the IO region of layout 20.
In whole description, when standard cell or grand being called as with gridline 24 on time, corresponding standard cell or grand border also align with gridline 24.For example, standard cell 100, memory macro 200, simulate grand 300 and the border 102,202,302 and 402 of IO grand 400 align with gridline 24 respectively.Standard cell 100, memory macro 200, simulate grand 300 and IO grand 400 in transistor can be fin formula field effect transistor (FinFET), this transistor comprises semiconductor fin and is positioned at the gate electrode of semiconductor fin top.For example, standard cell 100 comprises transistor 100, this transistor comprises fin 112 and gate electrode 114, memory macro 200 comprises transistor 210, this transistor comprises fin 212 and gate electrode 214, and IO grand 300 comprises transistor 310, and this transistor comprises fin 312 and gate electrode 314, and IO grand 400 comprises transistor 410, this transistor comprises fin 412 and gate electrode 414.According to some embodiment, when standard cell or grand being called as while aligning with gridline 24, standard cell or grand in the fin of FinFET also can align with gridline 24.For example, the center line of fin 112,212,312 and 412 aligns with corresponding gridline 24, but the border of fin 112,212,312 and 412 also can align with gridline 24 in optional embodiment.Fin 112,212,312 and 412 can have the direction of the lengthwise parallel with directions X.
In a preferred embodiment, relative border 102 can be respectively the first border or the second boundary; Relative border 202 can be respectively the 3rd border or the 4th border; Retive boundary 302 can be respectively the 5th border and hexagon circle.In addition, relative border 402 can be respectively also the 5th border and hexagon circle.
Memory macro 200 also comprises multiple memory cells 120, and these memory cells for example can be, sram cell or DRAM unit.Fig. 1 shows a memory cell 120 is arranged in memory macro 200.In optional embodiment, construct in advance whole memory macro 200 and whole memory macro 200 be arranged in tube core layout 20 simultaneously.The border 122 of memory cell 120 also aligns with gridline 24.
Can find out, because fin 112,212,312 and 412 and the gridline 24 with equidistant from distance P1 align, so the spacing of fin 112,212,312 and 412 equals N*P1, wherein, N is equal to or greater than 0 integer.Spacing P1 is also the minimum spacing of all fins 112,212,312 and 412.Regulation alternatively, the spacing of all fins 112,212,312 and 412 is equal to the integral multiple of the spacing P1 of gridline 24.In order to determine the spacing of fin of not aiming in the Y direction, can be by extending fin (such as, fin 112) thus drawing line stretcher obtains line stretcher, so and because line stretcher is parallel and align with gridline 24 spacing that can determine line stretcher each other.For example, shown fin 112 and some fins 412 are not aimed in the Y direction.But their line stretcher (being also gridline 24) has the spacing that equals N*P1.
In certain embodiments, all fins of all FinFET in whole tube core layout 20 all have the longitudinal direction that is parallel to directions X, and there is no fin, or there is no that fin has the longitudinal direction extending along Y-direction.In addition, in whole tube core layout 20, there is no fin, or there is no that fin does not align with gridline 24.In optional embodiment, one or more standard cells 100, memory macro 200, simulate grand 300 and IO grand 400 in some fins do not align with gridline 24, and remaining standard cell 100, memory macro 200, simulate grand 300 and fin and the gridline 24 of IO grand 400 align.Gate electrode 114,214,314 and 414 is perpendicular to fin 112,212,312 and 412, and has the longitudinal direction that is parallel to Y-direction.
Due to standard cell 100, memory macro 200, simulate grand 300 and the border 102,202,302 and 402 of IO grand 400 align with gridline 24 respectively, so standard cell 100, memory macro 200, simulate grand 300 and width W 1, W2, W3 and the W4(retive boundary of IO grand 400 between distance) be respectively the integral multiple of spacing P1.
Standard cell 100, memory macro 200, simulate grand 300 and IO grand 400 also comprise respectively border 103,203,303 and 403, these borders are parallel to Y-direction.According to some embodiment, border 103,203,303 and 403 does not force to align with gridline 24.Therefore, border 103,203,303 and 403 can with arbitrary graphic pattern in gridline 26 align or do not align.In optional embodiment, border 103,203,303 and 403 is not forced to align with gridline 26.Standard cell 100, memory macro 200, simulate grand 300 and IO grand 400 in gate electrode 114,214,314 and 414 also can align with gridline 26, but in optional embodiment, they do not align with gridline 26.
Circuit design in Fig. 1 can be stored in the tangible storage medium 12 in Fig. 3.Can carry out manufacturing integration circuit by the circuit design of layout 20.Fig. 2 shows physics semiconductor element 40, on semiconductor crystal wafer, manufactures this physics semiconductor element by the circuit design in tube core layout 20.Therefore, the each parts shown in Fig. 2 all reflect the design in Fig. 1.Should be appreciated that, in tube core 40, cannot see again gridline 24 and 26.But, in Fig. 2, for still showing gridline with reference to object.But fin 112,212,312 and 412 is distinguishing.In addition, for example, can find standard cell 100, memory macro 200 by limiting feature, simulate grand 300 and IO grand 400 at least some border.For example, standard cell can comprise dummy poly (or the pseudo-gate electrode being formed by the other materials beyond polysilicon) line, and this line or electricity are floated or be bound to VDD or VSS.The center line of pseudo-silicon line can be aimed at the borderline phase of standard cell 100.In addition, due to standard cell 100, memory macro 200, simulate grand 300 and IO grand 400 can in tube core 40, repeat, so standard cell 100, memory macro 200, simulate grand 300 and the border of IO grand 400 also can determine by repeat patterns relatively.
Although gridline 24 and 26(Fig. 1) be not present in tube core 40, the line stretcher of fin 112,212,312 and 412 can be identical, and the spacing of line stretcher can determine, equals many times of spacing P1.In these embodiments, can determine minimum spacing P1 by the minimum spacing of finding fin 112,212,312 and 412.According to some embodiment, the line stretcher of one of fin 112,212,312 and 412 can be selected as line of reference, and can determine by measuring distance between line stretcher and the line of reference of other fins the spacing of every other fin.
In embodiment of the present disclosure, by standard cell, memory macro, simulation is grand and IO is grand fin and the gridline of tube core or wafer are aligned to form very narrow fin, its reason is, the formation of fin can be used some diffractive technologies, and can form thus all fins and their the shared identical processing steps aimed at identical gridline simultaneously.But if some fins do not align with the identical gridline of some other fin, and/or some fins have the longitudinal direction perpendicular with other fins, have to form respectively these fins and have increased manufacturing cost.
According to some embodiment, a kind of tube core comprises at least one standard cell, and this standard cell comprises the first border and the second boundary relative with the first border.The first border and the second boundary are parallel to first direction.At least one standard cell comprises more than first FinFET in addition, and it comprises the first semiconductor fin that is parallel to first direction.Tube core comprises at least one memory macro in addition, and it has the 3rd border and four border right with the 3rd borderline phase.The 3rd border and the 4th border are parallel to first direction.At least one memory macro comprises more than second FinFET, and it comprises the second semiconductor fin that is parallel to first direction.All semiconductor fin at least one standard cell and at least one memory macro all have the spacing of the integral multiple of the minimum spacing that equals the first semiconductor fin and the second semiconductor fin.
According to other embodiment, a kind of tube core comprises standard cell and is selected from substantially by memory macro, simulates grand in group grand, that I/O is grand and their combination forms.This tube core comprises in addition and is arranged in each standard cell and grand FinFET.Substantially all semiconductor fin that are used to form all FinFET in tube core are all parallel to first direction.The spacing of all semiconductor fin is equal to the integral multiple of the minimum spacing in spacing.Minimum spacing is the minimum spacing in all spacing of all semiconductor fin.
According to other other embodiment, a kind of method comprises standard cell is arranged in tube core layout, wherein, uses computer to carry out the step of this layout standard cell.The first border of standard cell and the second boundary align with first grid ruling and second gate ruling respectively.Grid is distributed in whole tube core layout.The method comprises in addition and being arranged in tube core layout grand, and wherein, the 3rd grand border and the 4th border align with the 3rd gridline and the 4th gridline respectively.First grid ruling, second gate ruling, the 3rd gridline and the 4th gridline belong to the gridline of the grid with consistent spacing.This is grand is selected from by memory macro, simulate group grand, that I/O is grand and their combination forms.
Although described the present invention and advantage thereof in detail, should be appreciated that, can, in the case of not deviating from the purport of the present invention and scope of claims restriction, make various change, replace and change.And the application's scope is not limited in the specific embodiment of technique, machine, manufacture, material component, device, method and the step described in this specification.Should understand as those of ordinary skill in the art, by the present invention, existing or Future Development for carry out with according to the essentially identical function of described corresponding embodiment of the present invention or obtain technique, machine, the manufacture of basic identical result, material component, device, method or step can be used according to the present invention.Therefore, claims should be included in the scope of such technique, machine, manufacture, material component, device, method or step.In addition, every claim forms independent embodiment, and the combination of multiple claim and embodiment within the scope of the invention.
Claims (10)
1. a tube core, comprising:
At least one standard cell, comprising:
The first border and with respect to the second boundary on described the first border, wherein, described the first border and described the second boundary are parallel to first direction;
Multiple the first fin formula field effect transistors (FinFET), comprise the first semiconductor fin that is parallel to described first direction; And
At least one memory macro, comprising:
The 3rd border and with respect to the 4th border on described the 3rd border, wherein, described the 3rd border and described the 4th border are parallel to described first direction; With
Multiple the 2nd FinFET, comprise the second semiconductor fin that is parallel to described first direction, wherein, the spacing of all semiconductor fin in all semiconductor fin and described at least one memory macro in described at least one standard cell is equal to the integral multiple of the minimum spacing of described the first semiconductor fin and described the second semiconductor fin.
2. tube core according to claim 1, wherein, the second distance between the distance of first between described the first border and described the second boundary and described the 3rd border and described the 4th border equals the integral multiple of described minimum spacing.
3. tube core according to claim 1, also comprises:
At least one simulation is grand, comprising:
The 5th border and with respect to hexagon circle on described the 5th border, wherein, described the 5th border and described hexagon circle are parallel to described first direction; And
Multiple the 3rd FinFET, comprise the 3rd semiconductor fin that is parallel to described first direction, and wherein, the spacing of all semiconductor fin during described at least one simulation is grand is equal to the integral multiple of described minimum spacing.
4. tube core according to claim 1, also comprises:
(I/O) is grand at least one I/O, comprising:
The 5th border and with respect to hexagon circle on described the 5th border, wherein, described the 5th border and described hexagon circle are parallel to described first direction; And
Multiple the 3rd FinFET, comprise the 3rd semiconductor fin that is parallel to described first direction, and wherein, the spacing of all semiconductor fin during described at least one IO is grand is equal to the integral multiple of described minimum spacing.
5. tube core according to claim 1, wherein, the all semiconductor fin substantially of all FinFET in described tube core be longitudinally all parallel to described first direction, and all spacing substantially of all semiconductor fin of all FinFET in described tube core are equal to the integral multiple of described minimum spacing.
6. tube core according to claim 5, wherein, the all semiconductor fin of all FinFET in described tube core be longitudinally all parallel to described first direction, and all spacing of all semiconductor fin of all FinFET in described tube core are equal to the integral multiple of described minimum spacing.
7. tube core according to claim 1, wherein, all semiconductor fin substantially of all FinFET in described tube core be longitudinally all not parallel to second direction, described second direction is perpendicular to described first direction.
8. a tube core, comprising:
Standard cell;
Grand, be selected from substantially by memory macro, simulate group grand, that I/O is grand and their combination forms; And
Fin formula field effect transistor (FinFET), be arranged in described standard cell and described grand, wherein, the all semiconductor fin substantially that are used to form all FinFET in described tube core are all parallel to first direction, and the spacing of described all semiconductor fin is equal to the integral multiple of the minimum spacing in described spacing, wherein, described minimum spacing is spacing minimum in described all spacing of described all semiconductor fin.
9. tube core according to claim 8, wherein, describedly grandly comprise described memory macro, and described memory macro comprises static random access memory (SRAM) unit.
10. a method, comprising:
Standard cell is arranged in tube core layout, use computer to carry out the step of arranging described standard cell, wherein, the first border of described standard cell and the second boundary are aimed at first grid ruling and second gate ruling respectively, and grid is distributed in whole described tube core layout; And
Be arranged in described tube core layout grand, described the 3rd grand border and the 4th border align with the 3rd gridline and the 4th gridline respectively, and described first grid ruling, described second gate ruling, described the 3rd gridline and described the 4th gridline belong to the gridline of the grid with consistent spacing, and be describedly grandly selected from by memory macro, simulate group grand, that I/O is grand and their combination forms.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201361770224P | 2013-02-27 | 2013-02-27 | |
| US61/770,224 | 2013-02-27 | ||
| US13/874,027 US9047433B2 (en) | 2013-02-27 | 2013-04-30 | Cell and macro placement on fin grid |
| US13/874,027 | 2013-04-30 |
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| Publication Number | Publication Date |
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| CN104009032A true CN104009032A (en) | 2014-08-27 |
| CN104009032B CN104009032B (en) | 2017-01-18 |
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| CN201410064299.7A Active CN104009032B (en) | 2013-02-27 | 2014-02-25 | Cell and macro placement on fin grid |
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| CN113937063A (en) * | 2020-09-28 | 2022-01-14 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of manufacturing integrated circuit |
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| CN108701653A (en) * | 2016-02-25 | 2018-10-23 | 株式会社索思未来 | semiconductor integrated circuit device |
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| CN111599803B (en) * | 2019-02-21 | 2023-08-29 | 台湾积体电路制造股份有限公司 | Integrated circuit structure and method for manufacturing the same |
| CN113937063A (en) * | 2020-09-28 | 2022-01-14 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of manufacturing integrated circuit |
| US12328860B2 (en) | 2020-09-28 | 2025-06-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with increased unity density |
| CN113937063B (en) * | 2020-09-28 | 2025-12-30 | 台湾积体电路制造股份有限公司 | Semiconductor devices and methods for manufacturing integrated circuits |
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