CN104008958A - Self-alignment double-layer graph semiconductor structure manufacturing method - Google Patents

Abstract

The invention provides a method for fabricating a self-aligned double-layer pattern semiconductor structure, comprising: providing a semiconductor substrate, forming a polysilicon layer, a silicon nitride layer, a core pattern layer, a hard mask layer, an anti- reflective layer and photoresist layer; using the photoresist layer as a mask, the antireflection layer, hard mask layer and core pattern layer are etched to form a positive trapezoidal core pattern layer, and remove all Described anti-reflection layer, photoresist layer and hard mask layer; Form silicon oxide layer; Carry out silicon oxide main etching process and silicon oxide over-etching process, reduce the thickness of described silicon oxide layer on both sides of core graphic layer , using the silicon oxide layer as a mask to etch the underlying silicon nitride layer, a self-aligned double-layer pattern structure with stable vertical shape and size can be formed. The method of the invention can form a double-layer pattern semiconductor structure with stable shape and size.

Description

Method for fabricating self-aligned double-layer patterned semiconductor structure

technical field

The invention relates to the technical field of semiconductors, in particular to a method for manufacturing a self-aligned double-layer pattern semiconductor structure.

Background technique

At the node of 20nm and below, self-aligned double-layer patterning (SADP) process has been applied to the production of key semiconductor layers such as active area (AA) and polysilicon (Poly).

Please refer to FIG. 1-FIG. 7 for the cross-sectional structure schematic diagrams of the fabrication method of the self-aligned double-layer patterned semiconductor structure in the prior art. Please refer to FIG. 1, first, a semiconductor substrate 10 is provided, on which a silicon nitride layer 11, a core pattern layer 13, a hard mask layer 17, an anti-reflection layer 14 and a photoresist layer 15 are sequentially formed , the material of the core pattern layer 13 is amorphous carbon (APF), and the material of the hard mask layer 17 is SiOC.

Then, with reference to FIG. 2 and in conjunction with FIG. 1, the photoresist layer 15 is used as a mask to carry out an etching process to remove the antireflection layer 14 not covered by the photoresist layer 15, and the remaining antireflection layer 14 is used as a follow-up A mask for the process, this process step will consume a part of the photoresist layer 15 . Then use the remaining anti-reflection layer 14 as a mask to perform an etching process, and perform an etching process on the hard mask layer 17, and remove the hard mask layer 17 that is not covered by the remaining anti-reflection layer 14. After removal, the remaining part of the hard mask layer 17 will be used as a mask for subsequent process steps. After this process step, the photoresist layer 15 and the anti-reflection layer 14 are completely consumed.

Next, continue to refer to FIG. 2, use the remaining part of the hard mask layer 17 as a mask to perform an etching process to remove the part of the core pattern layer 13 that is not covered by the remaining part of the hard mask layer 17, and the pattern transferred to the remaining part of the core pattern layer 13, and the remaining part of the core pattern layer 13 will be used as a mask layer for the subsequent etching process. When etching the core pattern layer 13, it is necessary to consider the etching selectivity ratio between the hard mask layer 17 and the core pattern layer 13, and the etching process needs to have a higher ratio for the core pattern layer 13 and the hard mask layer 17. The etching selectivity is such that the hard mask layer 17 has sufficient barrier to the etching process of the core pattern layer 13 . In order to obtain the above-mentioned etching selectivity ratio, the prior art usually utilizes SO ₂ and O ₂ mixed gas to etch the core pattern layer 13 in a relatively clean reaction chamber; utilize O ₂ and carbon plasma reaction to generate CO or CO ₂ to etch the core pattern layer 13. But the shortcoming of above-mentioned technological process is that the reaction of oxygen and carbon tends to the chemical reaction of isotropy; less, the O ₂ damage to the core pattern layer 13 decreases from top to bottom, and finally forms a core pattern layer 13 with a positive trapezoidal shape.

Next, please refer to FIG. 3 to remove the mask layer 17, and the remaining core pattern layer 13 will be used as a mask for the subsequent etching process.

Then, referring to FIG. 4 , the silicon oxide layer 16 covering the surface of the core pattern layer 13 and the silicon nitride layer 11 is formed by using an atomic layer deposition process. The silicon oxide layer 16 on both sides of the core pattern layer 13 remains to form sidewall structures, while the silicon oxide layer 16 covering the top of the core pattern layer 13 and the surface of the silicon nitride layer 11 is removed. Since the shape of the core pattern layer 13 is a regular trapezoid, the silicon oxide layer 16 on both sides of the core pattern layer 13 presents an inclined shape.

Next, referring to FIG. 5 , the silicon oxide layer 16 is etched to remove the silicon oxide layer 16 on the top of the core pattern layer 13 and the surface of the silicon nitride layer 11, and the silicon oxide layer on both sides of the core pattern layer remains. 16. The silicon oxide layer 16 remaining on both sides of the core pattern layer has an inclined shape. The silicon oxide layer 16 remaining on both sides of the core pattern layer serves as a mask for the subsequent etching process.

Next, please refer to FIG. 6 and in combination with FIG. 5 , an etching process is performed to remove the core pattern layer 13 . The morphology of the silicon oxide layer 16 remaining on both sides of the core pattern layer forms a trapezoid as shown in FIG. 6 . Next, using the silicon oxide layer 16 remaining on both sides of the core pattern layer as a mask, the silicon nitride layer 11 below is etched to remove the silicon oxide layer not retained on both sides of the core pattern layer 13 The silicon nitride layer 11 covered by the layer 16, and the remaining silicon nitride layer 11 is a self-aligned double-layer pattern structure. Because the silicon oxide layer 16 remaining on both sides of the core pattern layer is inclined, its shape affects the shape of the self-aligned double-layer pattern structure, so that the shape and size of the self-aligned double-layer pattern structure unstable.

Therefore, it is necessary to improve the prior art to obtain a self-aligned double-layer patterned semiconductor structure with stable shape and size.

Contents of the invention

The problem solved by the invention provides a method for fabricating a self-aligned double-layer pattern semiconductor structure, which can form a double-layer pattern semiconductor structure with stable shape and size.

In order to solve the above problems, the present invention provides a method for fabricating a self-aligned double-layer patterned semiconductor structure, comprising:

A semiconductor substrate is provided, and a polysilicon layer, a silicon nitride layer, and a core pattern layer are formed on the semiconductor substrate, and the material of the core pattern layer is amorphous carbon;

forming a hard mask layer on the core pattern layer, the material of the hard mask layer is SiOC;

forming an anti-reflection layer and a photoresist layer on the hard mask layer, the photoresist layer defines a core pattern;

Using the photoresist layer as a mask, the antireflection layer, hard mask layer and core pattern layer are etched to form a positive trapezoidal core pattern layer, and the antireflection layer, photolithography subbing layer and hard mask layer;

forming a silicon oxide layer, the silicon oxide layer covering the surface of the silicon nitride layer, both sides and the top of the core pattern layer;

Carry out the silicon oxide main etching process, remove the silicon oxide layer on the top of the core pattern layer and the surface of the silicon nitride layer, and keep the silicon oxide layer on both sides of the core pattern layer;

Performing a silicon oxide over-etching process to reduce the thickness of the silicon oxide layer on both sides of the core pattern layer;

performing an etching process to remove the core pattern layer;

After the silicon oxide over-etching process, a silicon nitride etching process is performed using the silicon oxide layer on both sides of the core pattern layer as a mask to remove nitrogen that is not covered by the oxide layer on both sides of the core pattern layer Silicon layer;

The remaining silicon oxide layer on top of the silicon nitride is removed to form a self-aligned double-layer pattern structure.

Optionally, the core pattern layer is removed using a dry etching process, and the dry etching process is performed using a mixed gas of SO ₂ and O ₂ .

Optionally, the silicon oxide layer is formed by an atomic layer deposition process, and the thickness of the silicon oxide layer is in the range of 10-30 angstroms.

Optionally, the silicon oxide over-etching process reduces the thickness of the silicon oxide layer on both sides of the core pattern layer by at least 1/3.

Optionally, the silicon oxide over-etching process reduces the thickness of the silicon oxide layer on both sides of the core pattern layer by 1/3 to 4/5.

Optionally, the silicon oxide main etching process is performed using a mixed gas of C ₄ F ₈ and O ₂ .

Optionally, the silicon oxide over-etching process is performed using a mixed gas of C ₄ F ₆ and O ₂ .

Optionally, the silicon nitride etching process is performed using a mixed gas of CH ₂ F ₂ and CHF ₃ .

Optionally, the remaining silicon oxide on top of the silicon nitride is removed by a plasma etching process, and the gas of the plasma etching process includes C ₄ F ₆ , O ₂ .

Compared with the prior art, the present invention has the following advantages:

On the basis of the core pattern layer of the positive trapezoidal shape, the present invention utilizes a gas with a higher selectivity ratio to carry out an over-etching process on the thickness of the silicon oxide layer on both sides of the core pattern layer of the positive trapezoidal shape, and the purpose is to Reduce the thickness of the silicon oxide layer on both sides of the core pattern layer. After the thickness of the silicon oxide layer on both sides of the core pattern layer is reduced, use the silicon oxide layer as a mask to etch the lower silicon nitride layer to form a Self-aligned bilayer patterned structures with stable vertical morphology and size.

Description of drawings

1-7 are schematic cross-sectional structural diagrams of a method for fabricating a self-aligned double-layer patterned semiconductor structure in the prior art;

Fig. 8 is a principle analysis diagram made by utilizing the semiconductor structure of Fig. 6 and Fig. 7;

9-16 are schematic cross-sectional structural diagrams of a method for fabricating a self-aligned double-layer patterned semiconductor structure according to an embodiment of the present invention.

Detailed ways

In the prior art, when the core pattern layer is etched with the photoresist layer as a mask, since the material of the core pattern layer is amorphous carbon, in order to ensure that the core pattern layer and the silicon nitride layer below and the hard layer above The etch selectivity ratio between the mask layers, using a mixed gas of SO ₂ and O ₂ as the etching gas, leads to the positive trapezoidal shape of the finally formed core pattern layer, and also leads to oxidation on both sides of the core pattern layer The inclined shape of the silicon layer finally makes the size and shape of the self-aligned double-layer pattern formed by using the silicon oxide layer on both sides of the core pattern layer as a mask unstable.

Please refer to FIG. 6 , due to the limitation of the positive trapezoidal shape of the core pattern layer, the silicon oxide layer 16 on both sides of the core pattern layer has an inclination angle, and the inclination angle of the oxide layer 16 is fixed. Referring to FIG. 7 , the underlying silicon nitride layer 11 is etched using the silicon oxide layer 16 as a mask, and the formed silicon nitride layer 11 (that is, a self-aligned double-layer pattern structure) has a positive trapezoidal shape.

The inventors found that the shape of the finally formed silicon nitride layer 11 is related to the shape of the mask layer (that is, the silicon oxide layer 16 remaining on both sides of the core pattern layer) during the etching process. Further, the silicon oxide layer 16 remaining on both sides of the core pattern layer has a diamond shape, and the width of the silicon oxide layer 16 remaining on both sides of the core pattern layer is larger than that of the silicon nitride layer after the subsequent etching process 11 The width of the upper base of the regular trapezoid, the width of the silicon oxide layer 16 remaining on both sides of the core pattern layer is smaller than the width of the lower base of the regular trapezoid of the silicon nitride layer 11 after the subsequent etching process. The etching process on the silicon nitride layer 11 is a pattern transfer process using the silicon oxide layer 16 remaining on both sides of the core pattern layer as a mask. During the etching process of the silicon nitride layer 11, the width B of the lower base of the silicon nitride layer 11 depends on the width of the largest area that the silicon oxide layer 16 can cover, while the width A of the upper base of the silicon nitride layer 11 depends on In the thickest width of the silicon oxide layer 16 as the barrier layer, the covered silicon nitride layer within this range is best protected by the silicon oxide layer 16 as the barrier layer, and this part will not be etched.

Please refer to FIG. 8 . FIG. 8 is a schematic analysis diagram made by using the semiconductor structure in FIG. 6 and FIG. 7 . For ease of analysis, the graphic labels in Fig. 8 are the same as those in Fig. 6 and Fig. 7, and the silicon oxide layer 16 located on both sides of the core graphic layer has an oblique appearance, its height is T, its width is L, and the slope The angle is α, the silicon nitride layer 11 formed by the etching process is a regular trapezoidal shape, the length of the upper base is A, the length of the lower base is B, the height of the regular trapezoid is H, and the length of the regular trapezoid is The bottom angle is β, then:

Referring to Figure 8, A=L-T/tangα,

B=L+T/tangα

tangβ=H/[(B-A)/2]

tangβ=H/[(L+T/tangα-L+T/tangα)/2]=(H*tangα)/T

According to the above analysis process: the silicon nitride layer is etched with the silicon oxide layer 16 remaining on both sides of the core pattern layer as a mask, and the inclination angle β (tang β) of the formed silicon nitride layer 11 is different from that of nitrogen The thickness H of the silicon oxide layer 11, the inclination angle α of the silicon oxide layer 16 remaining on both sides of the core pattern layer is proportional to the thickness T of the silicon oxide layer 16 remaining on both sides of the core pattern layer when performing the etching process Inversely proportional.

In conjunction with FIG. 2, the inventors also found that, after performing the steps in FIG. 2, the part of the core graphics layer 13 that is not covered by the reserved part of the hard mask layer 17 is removed, and the graphics are transferred to the reserved part of the core graphics layer. In 13, the etching process parameters in this step have an impact on the morphology of the remaining part of the core pattern layer 13, and when the etching process parameters in this step are relatively fixed, the morphology of the formed core pattern layer 13 is fixed, so The topography of the silicon oxide layer formed with the core pattern layer 13 as a mask is fixed in the follow-up, referring to FIG. 5 and FIG. The inclination angle α of the silicon oxide layer 16 on both sides of the core pattern layer 16 is fixed, and the thickness H of the silicon nitride layer 11 is also set by the process.

According to the formula: tangβ=H/[(L+T/tangα-L+T/tangα)/2]=(H*tangα)/T, it can be known that the inclination angle β (tangβ) of the formed silicon nitride layer 11 is related to the nitrogen The thickness H of the silicon oxide layer 11, the inclination angle α of the silicon oxide layer 16 remaining on both sides of the core pattern layer is proportional to the thickness T of the silicon oxide layer 16 remaining on both sides of the core pattern layer when performing the etching process Inversely proportional. Under the condition that H and α (tang α) are fixed, in order to make the inclination angle β (tang β) of the formed silicon nitride layer 11 as close as possible to the vertical angle, it is necessary to keep the core pattern layer 16 during the etching process. The height T of the silicon oxide layer 16 on both sides is reduced as much as possible.

Therefore, the inventor proposes that before etching the silicon nitride layer with the silicon oxide layer on both sides of the core pattern layer as a mask, the thickness of the silicon oxide layer should be reduced as much as possible to ensure that the subsequent oxidation The inclination angle of the silicon nitride layer (that is, the self-aligned double-layer pattern structure) formed by etching the silicon layer as a mask is close to the vertical angle. Specifically, the fabrication method of the self-aligned double-layer pattern semiconductor structure provided by the present invention includes:

A semiconductor substrate is provided, and a polysilicon layer, a silicon nitride layer, and a core pattern layer are formed on the semiconductor substrate, and the material of the core pattern layer is amorphous carbon;

forming a hard mask layer on the core pattern layer, the material of the hard mask layer is SiOC;

forming an anti-reflection layer and a photoresist layer on the hard mask layer, the photoresist layer defines a core pattern;

Using the photoresist layer as a mask, the antireflection layer, hard mask layer and core pattern layer are etched to form a positive trapezoidal core pattern layer, and the antireflection layer, photolithography subbing layer and hard mask layer;

forming a silicon oxide layer, the silicon oxide layer covering the surface of the silicon nitride layer, both sides and the top of the core pattern layer;

Carry out the silicon oxide main etching process, remove the silicon oxide layer on the top of the core pattern layer and the surface of the silicon nitride layer, and keep the silicon oxide layer on both sides of the core pattern layer;

Performing a silicon oxide over-etching process to reduce the thickness of the silicon oxide layer on both sides of the core pattern layer;

performing an etching process to remove the core pattern layer;

After the silicon oxide over-etching process, a silicon nitride etching process is performed using the silicon oxide layer on both sides of the core pattern layer as a mask to remove nitrogen that is not covered by the oxide layer on both sides of the core pattern layer Silicon layer;

The remaining silicon oxide layer on top of the silicon nitride is removed to form a self-aligned double-layer pattern structure.

The technical solutions of the present invention will be described in detail below in conjunction with specific embodiments. In order to better illustrate the technical solution of the present invention, please refer to FIGS. 9-16 , which are schematic cross-sectional structural diagrams of a method for fabricating a self-aligned double-layer patterned semiconductor structure according to an embodiment of the present invention.

First, referring to FIG. 9 , a semiconductor substrate 100 is provided, and a silicon nitride layer 101, a core pattern layer 103, a hard mask layer 107, an antireflection layer 104 and a photoresist layer 105 are sequentially formed on the semiconductor substrate 100. , the material of the core pattern layer 103 is amorphous carbon (APF), and the material of the hard mask layer 107 is SiOC.

Then, using the photoresist layer as a mask, the antireflection layer, hard mask layer and core pattern layer are etched to form a positive trapezoidal core pattern layer, and the antireflection layer, hard mask layer, and core pattern layer are removed. photoresist layer and hard mask layer.

Specifically, please refer to FIG. 10 in combination with FIG. 9 , use the photoresist layer 105 as a mask to perform an etching process, remove the antireflection layer 104 not covered by the photoresist layer 105, and keep the antireflection layer 104 As a mask for subsequent processes, this process step will consume a part of the photoresist layer 105 . Then use the remaining anti-reflection layer 104 as a mask to perform an etching process, and perform an etching process on the hard mask layer 107, and remove the hard mask layer 107 that is not covered by the retained anti-reflection layer 104 After removal, the remaining part of the hard mask layer 107 will be used as a mask for subsequent process steps. After this process step, the photoresist layer 105 and the anti-reflection layer 104 are completely consumed.

Next, continue referring to FIG. 10 , an etching process is performed using the remaining part of the hard mask layer 107 as a mask to remove the part of the core pattern layer 103 that is not covered by the remaining part of the hard mask layer 107, and the pattern Transfer to the reserved part of the core graphics layer 103, the reserved part of the core graphics layer 103 has a regular trapezoidal shape. The remaining part of the core pattern layer 103 will be used as a mask layer for the subsequent etching process.

As an embodiment, the present invention uses SO ₂ and O ₂ mixed gas to etch the core pattern layer 103 in a relatively clean reaction chamber; the plasma reaction of O ₂ and carbon generates CO or CO ₂ to the core pattern Layer 103 is etched. But the characteristic of above-mentioned technological process is that the reaction of oxygen and carbon is more inclined to the chemical reaction of isotropy; less, the O ₂ damage to the core pattern layer 103 decreases from top to bottom, and finally forms a core pattern layer 103 with a positive trapezoidal shape.

Next, referring to FIG. 11 , the mask layer 107 is removed, and the remaining core pattern layer 103 (with a positive trapezoidal shape) will be used as a mask for subsequent etching processes.

Then, referring to FIG. 12 , a silicon oxide layer 106 covering the surface of the core pattern layer 103 and the silicon nitride layer 101 is formed by using an atomic layer deposition process. The silicon oxide layer 106 on both sides of the core pattern layer 103 remains to form sidewall structures, while the silicon oxide layer 106 covering the top of the core pattern layer 103 and the surface of the silicon nitride layer 101 is removed. Since the shape of the core pattern layer 103 is a regular trapezoid, the silicon oxide layer 106 on both sides of the core pattern layer 103 presents an inclined shape. As an example, the thickness of the silicon oxide layer 103 ranges from 10-30 angstroms.

Next, please refer to FIG. 13 , the silicon oxide layer 106 is subjected to a silicon oxide main etching process, and the silicon oxide layer 106 located on the top of the core pattern layer 103 and the surface of the silicon nitride layer 101 is removed, and remains on both sides of the core pattern layer 103 silicon oxide layer 106 . So far, the shape of the silicon oxide layer 106 is determined, and its inclination angle is fixed. In subsequent process steps, by reducing the height of the silicon oxide layer 106, the morphology of the finally formed sub-optimal double-layer pattern structure will be adjusted. As an example, the silicon oxide main etching process is a dry etching process, and the silicon oxide main etching process is performed using a mixed gas of C ₄ F ₈ and O ₂ .

Next, referring to FIG. 14 , a silicon oxide over-etching process is performed to reduce the thickness of the silicon oxide layer 106 on both sides of the core pattern layer. As an embodiment, the silicon oxide over-etching process reduces the thickness of the silicon oxide layer 106 on both sides of the core pattern layer by at least 1/3. Preferably, the silicon oxide over-etching process reduces the thickness of the silicon oxide layer 106 on both sides of the core pattern layer by 1/3 to 4/5. As an example, the silicon oxide over-etching process is performed using a mixed gas of C ₄ F ₆ and O ₂ .

Through the silicon oxide over-etching process, the thickness of the silicon oxide layer 106 on both sides of the core pattern layer is reduced, which facilitates the etching process of the lower silicon nitride layer using the silicon oxide layer 106 as a mask in subsequent steps , which is more conducive to the formation of self-aligned double pattern structures with stable vertical morphology and size.

Next, referring to FIG. 15 , an etching process is performed to remove the core pattern layer 13 , and the height of the remaining silicon oxide layer 106 is significantly lower than that of the silicon oxide layer in FIG. 13 .

Next, please refer to FIG. 16 , using the silicon oxide layer 106 as a mask, an etching process is performed on the lower silicon nitride layer 101 to remove the silicon nitride layer 101 not covered by the silicon oxide layer 106, and the remaining The silicon nitride layer 101 is a self-aligned double-layer pattern structure. Since the remaining thickness of the oxide layer 106 has been reduced by the silicon oxide over-etching process, the silicon nitride layer 101 formed using the silicon oxide layer 106 as a mask has a shape closer to a vertical shape.

As an example, the silicon nitride etching process is performed using a mixed gas of CH ₂ F ₂ and CHF ₃ .

Then, continuing to refer to FIG. 16 , an etching process is performed to remove the remaining silicon oxide layer on top of the silicon nitride. The remaining silicon oxide layer on top of the silicon nitride is removed by plasma etching process, the gas of the plasma etching process includes C ₄ F ₆ , O ₂ .

To sum up, on the basis of the core pattern layer with positive trapezoidal shape, the present invention uses a gas with a relatively high selectivity ratio to perform an over-etching process on the thickness of the silicon oxide layer on both sides of the core pattern layer with positive trapezoidal shape. The purpose is to reduce the thickness of the silicon oxide layer on both sides of the core pattern layer. After the thickness of the silicon oxide layer on both sides of the core pattern layer is reduced, the silicon nitride layer below is etched using the silicon oxide layer as a mask. A self-aligned double-layer pattern structure with stable vertical morphology and size can be formed.

Therefore, the above-mentioned preferred embodiments are only to illustrate the technical concept and features of the present invention, and the purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly, and not to limit the scope of protection of the present invention. All equivalent changes or modifications made according to the spirit of the present invention shall fall within the protection scope of the present invention.

Claims (9)

1. A method for making a self-aligned double-layer pattern semiconductor structure, characterized in that, comprising: A semiconductor substrate is provided, and a polysilicon layer, a silicon nitride layer, and a core pattern layer are formed on the semiconductor substrate, and the material of the core pattern layer is amorphous carbon; forming a hard mask layer on the core pattern layer, the material of the hard mask layer is SiOC; forming an anti-reflection layer and a photoresist layer on the hard mask layer, the photoresist layer defines a core pattern; Using the photoresist layer as a mask, the antireflection layer, hard mask layer and core pattern layer are etched to form a positive trapezoidal core pattern layer, and the antireflection layer, photolithography subbing layer and hard mask layer; forming a silicon oxide layer, the silicon oxide layer covering the surface of the silicon nitride layer, both sides and the top of the core pattern layer; Carry out the silicon oxide main etching process, remove the silicon oxide layer on the top of the core pattern layer and the surface of the silicon nitride layer, and keep the silicon oxide layer on both sides of the core pattern layer; Performing a silicon oxide over-etching process to reduce the thickness of the silicon oxide layer on both sides of the core pattern layer; performing an etching process to remove the core pattern layer; After the silicon oxide over-etching process, a silicon nitride etching process is performed using the silicon oxide layer on both sides of the core pattern layer as a mask to remove nitrogen that is not covered by the oxide layer on both sides of the core pattern layer Silicon layer; The remaining silicon oxide layer on top of the silicon nitride is removed to form a self-aligned double-layer pattern structure. 2. the manufacture method of self-aligned double-layer pattern semiconductor structure as claimed in claim 1, is characterized in that, described core pattern layer utilizes dry etching process to remove, and described dry etching process utilizes SO ₂ , O ₂ gas mixture. 3. The method for fabricating a self-aligned double-layer pattern semiconductor structure as claimed in claim 1, wherein the silicon oxide layer is formed by an atomic layer deposition process, and the thickness range of the silicon oxide layer is 10-30 angstroms . 4. the manufacture method of self-aligned double-layer pattern semiconductor structure as claimed in claim 1, is characterized in that, described silicon oxide overetching process will be positioned at the thickness of the silicon oxide layer on both sides of core pattern layer and reduce at least 1/ 3. 5. the manufacture method of self-aligned double-layer pattern semiconductor structure as claimed in claim 4, is characterized in that, described silicon oxide overetching process will be positioned at the thickness of the silicon oxide layer on both sides of core pattern layer and reduce 1/3 to 4/5. 6 . The method for fabricating a self-aligned double-layer patterned semiconductor structure according to claim 1 , wherein the silicon oxide main etching process is performed using a mixed gas of C ₄ F ₈ and O ₂ . 7. The method for fabricating a self-aligned double-layer patterned semiconductor structure according to claim 1 or 6, wherein the silicon oxide over-etching process is performed using a mixed gas of C ₄ F ₆ and O ₂ . 8 . The method for fabricating a self-aligned double-layer patterned semiconductor structure according to claim 1 , wherein the silicon nitride etching process is performed using a mixed gas of CH ₂ F ₂ and CHF ₃ . 9. The method for fabricating a self-aligned double-layer patterned semiconductor structure according to claim 1, wherein the remaining silicon oxide layer positioned on top of the silicon nitride is removed by a plasma etching process, and the plasma etching process The gas used in the etching process includes C ₄ F ₆ , O ₂ .