CA2538959A1 - Digital fractional clock divider - Google Patents
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- 238000003786 synthesis reaction Methods 0.000 description 2
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
- H03K23/50—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits
- H03K23/502—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits with a base or a radix other than a power of two
- H03K23/507—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits with a base or a radix other than a power of two with a base which is a non-integer
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Abstract
There is provided an apparatus comprising a multiphase clock generator, a frequency divider and a frequency synthesizer. The multiphase clock generator produces a plurality of phase shifted clock signals of frequency f, and having different phases relative to each other. The frequency divider receives the phase shifted clock signals of frequency f produces phase shifted clock signals of frequency f/N, where N is an integer. The phase shifted clock signals of frequency f/N have different phases relative to each other. The frequency synthesizer receives the phase shifted clock signals of frequency f/N and produces at least one clock signal of frequency f/ (N/2P), where P is an integer. A
clocked sequential network comprising a sequential subcircuit including an initial sequential logic block and an end sequential logic block, and a multi-phase clock generator, is also provided. The multiphase clocked generator outputs a reference clock signal at a reference frequency f and a phase delayed clock signal at a delayed phase compared to the reference clock signal. The reference clock signal is received by the initial sequential logic block of the sequential subcircuit and the phase delayed clock signal is received by the end sequential logic block of the sequential subcircuit.
clocked sequential network comprising a sequential subcircuit including an initial sequential logic block and an end sequential logic block, and a multi-phase clock generator, is also provided. The multiphase clocked generator outputs a reference clock signal at a reference frequency f and a phase delayed clock signal at a delayed phase compared to the reference clock signal. The reference clock signal is received by the initial sequential logic block of the sequential subcircuit and the phase delayed clock signal is received by the end sequential logic block of the sequential subcircuit.
Description
DIGITAL FRACTIONAL CLOCK DIVIDER
Field of Invention:
The present invention is related to the field of digital frequency synthesis and digital division of electrical signals by both integer and fractional division ratios.
Digital frequency synthesis is particularly important in clock recovery circuits digital data transmission and digital Integrated Circuits (IC) in general.
Background of the Invention:
Electronic circuits can generate a sequence of pulses which can be used in many applications such as clocks and pulse generators. In various applications it may be desired to generate a sequence of pulses with a period which can be either an integer multiple or a non-integer multiple of a reference clock period, where the fractional divisions are the more difficult of the two to design. A non-integer multiple of a reference clock period T can be represented as (N/2P) x T, where N
and P are integers. This representation is equivalent to fractional division of the corresponding reference clock frequency f = 1!T by N/2P, therefore equivalent to a division of the reference frequency f by N along with a multiplication of the reference frequency f by 2P. The non-integer multiple representation as N/2P
does not limit the class of possible integers, as any non-integer ratio UM, where L and M are integers, can be rewritten as N/2P, where N and P are integers. To clarify the notion of frequency division, the following example is given: if the reference clock period is 10 ns (i.e. 100 MHz), then to produce a signal with a period of 12.5 ns (i.e. 80 MHz), the reference clock period can be multiplied by 1.25. This is equivalent to dividing the reference clock frequency by 5, then multiplying the output waveform by 4 (i.e. N = 5, 2P=4).
There are two common techniques for digital fractional clock divisions. The first is called "rational-rate" approach, which utilizes two sets of dividers, where the reference clock is divided by two different integer values to produce two sub-clocks. The system then switches between the two sub-clocks to produce a fractionai average frequency of the reference clock. The second approach is called "pulse swallowing" where fractional frequency division is essentially achieved by dropping a clock pulse every N clock cycles and stretching the period. For example if a divide by 1.5 ratio is required, the system switches between the divide by 2 and divide by 3 signals to get an average of 1.5 ratio in the case of rational rate technique. For pulse swallowing, the reference clock is divided by 2 and every third pulse is the dropped with stretching the clock period.
These techniques, however, suffer from significant lack of symmetry in the wave shape of the generated clock signals and clock jitter in the order of one clock cycle. This significant clock jitter reduces the phase margins in clock recovery applications and makes it virtually unusable in clock synthesizers for ASIC
applications.
U.S. patent No. 3,959,737 falls under the "pulse swallowing" category, where dropping a clock pulse is achieved by the inhibition of the clock divider, which also stretches the output period. Another example of the "pulse swallowing"
technique is U.S. patent No. 4,573,176 which employs a fractional divider that achieves a division factor of either 2 or 2+1/N. The division factor of 2+1/N
is achieved by dropping a clock pulse every N clock cycles.
U.S. patent No. 5,088,057 falls under the "rational rate" approach, where it divides the reference clock by two different integer values to generate two sub frequencies. The system then switches between the two sub frequencies to produce an average clock frequency.
The properties of rational rate approach can be enhanced significantly by using a single clock divider with multiple phases of the reference clock driving the divider.
U.S patent No. 6,157,694 and U.S. patent application No. 20050237090 describe a fractional frequency divider that alternately outputs signals having different respective periods to drive an average period of the output signal to within a predetermined number of phase steps of the desired period. The phase steps are provided by a plurality of phase shifted reference clock signals. These systems, however, still generates some jitter in the output signal because the switching is between several phase shifted signals whose pulse edges, in general, do not always occur at the same time. In addition, the selection of different phases of the refierence clock at specific times requires complex control logic in a feedback loop of the system.
Almost all current digital fractional clock dividers do not have inherent ways of controlling the phase of the generated clock signals. In Digital Integrated Circuits (IC) it is often necessary to adjust the phase of the generated clocks or align the edges with other clocks in the system. In general, balancing more than one clock domain due to the different loadings in Integrated Circuits (IC) could be very challenging and time consuming, and in many cases, may be excluded from timing analysis, which could affect the quality of the system. Ideally, all of the clock signals are distrybuted throughout the IC such that their) edges occur simultaneously. However, the generated clock signals are typically skewed with respect to the reference and other generated clocks in the IC due to the different loading and path delays they have. This skew between clocks can affect the functionality of the logic circuit and may cause improper operation of the device if not compensated for. A common technique to synchronize (or balance) multiple clock signals is to insert buffers in the propagation paths of each clock signal.
The use of buffers suffers from a significant increase in power consumption and silicon area. As well, the task of balancing multiple clocks in this manner becomes exceedingly complex.
Furthermore, in integrated circuit designs having timing critical paths, such as in the prior art FIG. 11 a, clocking techniques might require using lower clock frequency, in order to make such circuit operable.
Field of Invention:
The present invention is related to the field of digital frequency synthesis and digital division of electrical signals by both integer and fractional division ratios.
Digital frequency synthesis is particularly important in clock recovery circuits digital data transmission and digital Integrated Circuits (IC) in general.
Background of the Invention:
Electronic circuits can generate a sequence of pulses which can be used in many applications such as clocks and pulse generators. In various applications it may be desired to generate a sequence of pulses with a period which can be either an integer multiple or a non-integer multiple of a reference clock period, where the fractional divisions are the more difficult of the two to design. A non-integer multiple of a reference clock period T can be represented as (N/2P) x T, where N
and P are integers. This representation is equivalent to fractional division of the corresponding reference clock frequency f = 1!T by N/2P, therefore equivalent to a division of the reference frequency f by N along with a multiplication of the reference frequency f by 2P. The non-integer multiple representation as N/2P
does not limit the class of possible integers, as any non-integer ratio UM, where L and M are integers, can be rewritten as N/2P, where N and P are integers. To clarify the notion of frequency division, the following example is given: if the reference clock period is 10 ns (i.e. 100 MHz), then to produce a signal with a period of 12.5 ns (i.e. 80 MHz), the reference clock period can be multiplied by 1.25. This is equivalent to dividing the reference clock frequency by 5, then multiplying the output waveform by 4 (i.e. N = 5, 2P=4).
There are two common techniques for digital fractional clock divisions. The first is called "rational-rate" approach, which utilizes two sets of dividers, where the reference clock is divided by two different integer values to produce two sub-clocks. The system then switches between the two sub-clocks to produce a fractionai average frequency of the reference clock. The second approach is called "pulse swallowing" where fractional frequency division is essentially achieved by dropping a clock pulse every N clock cycles and stretching the period. For example if a divide by 1.5 ratio is required, the system switches between the divide by 2 and divide by 3 signals to get an average of 1.5 ratio in the case of rational rate technique. For pulse swallowing, the reference clock is divided by 2 and every third pulse is the dropped with stretching the clock period.
These techniques, however, suffer from significant lack of symmetry in the wave shape of the generated clock signals and clock jitter in the order of one clock cycle. This significant clock jitter reduces the phase margins in clock recovery applications and makes it virtually unusable in clock synthesizers for ASIC
applications.
U.S. patent No. 3,959,737 falls under the "pulse swallowing" category, where dropping a clock pulse is achieved by the inhibition of the clock divider, which also stretches the output period. Another example of the "pulse swallowing"
technique is U.S. patent No. 4,573,176 which employs a fractional divider that achieves a division factor of either 2 or 2+1/N. The division factor of 2+1/N
is achieved by dropping a clock pulse every N clock cycles.
U.S. patent No. 5,088,057 falls under the "rational rate" approach, where it divides the reference clock by two different integer values to generate two sub frequencies. The system then switches between the two sub frequencies to produce an average clock frequency.
The properties of rational rate approach can be enhanced significantly by using a single clock divider with multiple phases of the reference clock driving the divider.
U.S patent No. 6,157,694 and U.S. patent application No. 20050237090 describe a fractional frequency divider that alternately outputs signals having different respective periods to drive an average period of the output signal to within a predetermined number of phase steps of the desired period. The phase steps are provided by a plurality of phase shifted reference clock signals. These systems, however, still generates some jitter in the output signal because the switching is between several phase shifted signals whose pulse edges, in general, do not always occur at the same time. In addition, the selection of different phases of the refierence clock at specific times requires complex control logic in a feedback loop of the system.
Almost all current digital fractional clock dividers do not have inherent ways of controlling the phase of the generated clock signals. In Digital Integrated Circuits (IC) it is often necessary to adjust the phase of the generated clocks or align the edges with other clocks in the system. In general, balancing more than one clock domain due to the different loadings in Integrated Circuits (IC) could be very challenging and time consuming, and in many cases, may be excluded from timing analysis, which could affect the quality of the system. Ideally, all of the clock signals are distrybuted throughout the IC such that their) edges occur simultaneously. However, the generated clock signals are typically skewed with respect to the reference and other generated clocks in the IC due to the different loading and path delays they have. This skew between clocks can affect the functionality of the logic circuit and may cause improper operation of the device if not compensated for. A common technique to synchronize (or balance) multiple clock signals is to insert buffers in the propagation paths of each clock signal.
The use of buffers suffers from a significant increase in power consumption and silicon area. As well, the task of balancing multiple clocks in this manner becomes exceedingly complex.
Furthermore, in integrated circuit designs having timing critical paths, such as in the prior art FIG. 11 a, clocking techniques might require using lower clock frequency, in order to make such circuit operable.
There is a need for an improved digital fractional clock divider producing balanced clock signals,-with minimized jitter, with improved alignment of pulse edges or phase shifted output signals, and reduced requirements for control logic in feedback loops.
Summary of the Invention:
An object of the invention is to provide a digital fractional clock divider that alleviates totally or in part the drawbacks of the prior art digital fractional clock dividers.
Accordingly, an apparatus comprising a multiphase clock generator, a frequency divider and a frequency synthesizer is provided. The multiphase clock generator produces a plurality of phase shifted clock signals of frequency f, and having different phases relative to each other. The frequency divider receives the phase shifted clock signals of frequency f, and produces phase shifted clock signals of frequency f/N, where N is an integer. The phase shifted clock signals of frequency f/N have different phases relative to each other. The frequency synthesizer receives the phase shifted clock signals of frequency f/N and produces at least one clock signal of frequency f/ (N/2P), where P is an integer.
Advantageously, the frequency synthesizer further comprises a waveshaper, for enhancing the symmetry of the clock signals produced by the frequency divider.
According to a further embodiment of the invention, a clocked sequential network comprising a sequential subcircuit including an initial sequential logic block and an end sequential logic block, and a multi-phase clock generator, is also provided. The multiphase clocked generator outputs a reference clock signal at a reference frequency f and a phase delayed clock signal at a delayed phase compared to the reference clock signal. The reference clock signal is received by the initial sequential logic block of the sequential subcircuit and the phase delayed clock signal is received by the end sequential logic block of the sequential subcircuit.
Summary of the Invention:
An object of the invention is to provide a digital fractional clock divider that alleviates totally or in part the drawbacks of the prior art digital fractional clock dividers.
Accordingly, an apparatus comprising a multiphase clock generator, a frequency divider and a frequency synthesizer is provided. The multiphase clock generator produces a plurality of phase shifted clock signals of frequency f, and having different phases relative to each other. The frequency divider receives the phase shifted clock signals of frequency f, and produces phase shifted clock signals of frequency f/N, where N is an integer. The phase shifted clock signals of frequency f/N have different phases relative to each other. The frequency synthesizer receives the phase shifted clock signals of frequency f/N and produces at least one clock signal of frequency f/ (N/2P), where P is an integer.
Advantageously, the frequency synthesizer further comprises a waveshaper, for enhancing the symmetry of the clock signals produced by the frequency divider.
According to a further embodiment of the invention, a clocked sequential network comprising a sequential subcircuit including an initial sequential logic block and an end sequential logic block, and a multi-phase clock generator, is also provided. The multiphase clocked generator outputs a reference clock signal at a reference frequency f and a phase delayed clock signal at a delayed phase compared to the reference clock signal. The reference clock signal is received by the initial sequential logic block of the sequential subcircuit and the phase delayed clock signal is received by the end sequential logic block of the sequential subcircuit.
An advantage of controlling the phase of the generated clock signals is having the capabilities of relaxing the constraints on timing critical paths in Integrated Circuits (IC) by using dual phase clocks of the same frequency instead of a single clock.
Other advantages, objects and features of the present invention will be readily apparent to those skilled in the art from a review of the following detailed description of preferred embodiments in conjunction with the accompanying drawings.
Brief Description of Drawinas The following detailed description, given by way of example and not intended to limit the present invention solely thereto, will best be appreciated in conjunction with the accompanying drawings, wherein like reference numerals denote like elements and parts, where:
FIG. I is a block diagram of a digital fractional clock divider in accordance with one embodiment of the invention;
FIG. 2a is a block diagram of a 1-stage frequency multiplier x2, in accordance with an embodiment of the invention;
FIG. 2b is a waveform diagram of clock signals received and produced by the 1-stage clock frequency multiplier x2 in FIG. 2a;
FIG. 3a is a block diagram of a 2-stage frequency multiplier x2, in accordance with an embodiment of the invention;
FIG. 3b is a waveform diagram of clock signals received and produced by the 2-stage clock frequency multiplier x2 in FIG. 3b;
FIG. 4a is a block diagram of a frequency divider 22, in accordance with an embodiment of the invention;
FIG. 4b is a block diagram of frequency dividers 23, 24 and a waveshaper 35a, in accordance with an embodiment of the invention;
FIG. 5 is a block diagram of a fractional clock divider 20' of a ratio of 1.5, in accordance with an embodiment of the invention;
FIG. 6 is a block diagram of a frequency synthesizer 30', in accordance with the an embodiment of the invention;
FIG. 7 is a waveform diagram of clock signals within the circuit in FIG. 5;
FIG. 8 is a waveform diagram of clock signals within the circuit in FIG. 5, showing skewed output clocks due to loading;
FIG. 9 is a waveform diagram of clock signals within the circuit in FIG. 5, showing a mechanism of correcting the skewed clock signal in accordance with a further embodiment of the invention;
FIG. 10 is a block diagram of an integrated circuit design using a clocking technique according to a further embodiment of the present invention; and FIGS. 11 a and 11 b are example of Integrated Circuits using a prior-art clocking technique and a clocking technique according to the embodiment of the invention in FIG. 10 .
Detailed Description of the Invention In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.
Some portions of the detailed description that follows are presented in terms of waveform diagrams of clock signals (or timing diagrams), digital logic elements such as flip-flops, Ring Shift Registers, OR and XOR gates. These descriptions and representations are consistent with the techniques used by those skilled in the digital processing art to convey the substance of their work to others skilled in the art, and they are not intended to limit the scope of the invention, when equivalent techniques are available in the art for achieving similar results.
In circuits embodying the invention, fractional division is generally accomplished by applying different clock signals having the same frequency as a reference clock signal, but different phases, to integer dividers of ratio N. The resultant waveforms are then passed through P-stage x2 multipliers, where P is the number of stages of a multiply x2 block. A final waveform of ratio N/2P
relative to the reference clock frequency is produced.
Reference is now made to FIG. 1, which illustrates a block diagram of a digital fractional clock divider in accordance with an embodiment of the invention.
The fractional divider in FIG. 1; comprises a multi-phase clock generator 10, a frequency divider block 20 and a frequency synthesizer 30. The multiphase clock generator 10 generates a plurality of phase shifted clock signals of the same reference clock frequency f but with different phases, phO, ph1, etc., relative to the phase of a reference clock. The frequency divider 20 receives the phase shifted clock signals at the clock reference frequency f and divides the frequency of these signals by N, producing a plurality of phase shifted clock signals of frequency f/N. The frequency synthesizer 30 receives the phase shifted signals at frequency f/N and outputs at least one clock signal of frequency f/(N/2P).
In alternative embodiments, the frequency synthesizer 30 may output a plurality of waveforms of frequency f/(N/2P), at different phases relative to each other.
The frequency synthesizer might also output waveforms of frequency f/N. In general, if N is an even number and 2P=1, then you only need 1 phase, if N is an odd number and 2P=1, then you need 2 phases, if N is an odd number and P is 1 or more (i.e. you are dividing by a fraction), then you need more than 2 phases.
The number of phases required to get full symmetrical waveforms is 4P. For example if P= 1 you need 4 phases each phase is 3600/4 apart, and if P = 2 you need 8 phases, each is 360 /8 apart and so on.
In order to achieve the frequency multiplication by 2P of the signals received from the frequency divider 20, the frequency synthesizer 30 comprises a frequency multiplier 40, performing frequency multiplication x2P on the incoming signals. Clock signals received by the frequency synthesizer 30,-may present a substantially high degree of symmetry This may be achieved by various logic implementations of the frequency divider 20 in conjunction with particular values for integer N and may be facilitated by selecting the phases of the phase shifted clock signals generated by the multiphase clock generator 10. These technical aspects would be obvious to a person skilled in the digital processing art.
Without limitation, an implementation example will be provided, showing substantially symmetrical clock signals being outputted by the frequency divider 20 in the case of an even N.
Advantageously, the degree of symmetry of clock signals of frequency f/N may be increased using a waveshaper 35, for balancing any non-symmetrical waveforms of frequency f/N outputted by the frequency divider 20, before performing frequency multiplication within the frequency multiplier 40. The phases of the signals generated by the multiphase clock generator 10; are primarily determined by the degree of symmetry required in the final waveforms and by the logical implementation of the digital fractional clock divider. It will be understood by those skilled in the art, that a compromise between symmetry of final waveforms of frequency f/(N/2P) and the number of phases, which relates to the complexity of digital logic circuitry, might be necessary for more complex ratios N/2P. However, it will also be appreciated that in embodiments of the present invention, fractional frequency division is accomplished mainly with digital logic blocks, without use of complex feedback loops, as in prior-art cases, yet a high degree of symmetry of divided signals can be achieved. An example of how phases can be selected for a given N/2P will be given below. In particular, according to a preferred embodiment, for a divide by 3, two phases are required and for a divide by 1.5, four phases are required. The values of these phases are 0 and 90 in the case of divide by 3 and 00, 90 , 180 and 270 in the case of a divide by 1.5. According to one embodiment of the invention, the number of phases to be selected for achieving substantially symmetrical waveforms at the output is as follows: if N is an even number and 2P=1, then only 1 phase suffices;
if N is an odd number and 2P=1, then 2 phases are sufficient; if N is an odd number and P is greater than or equal to 1, then at least 4P phases would be required. Furthermore, according to this particular embodiment, phases can be equidistant, as follows: if P= 1, four phases approximately 360 /4 apart could be used, whereas for P = 2, eight phases approximately 360 /8 apart could be used required, etc. However it will be recognized by those skilled in the art that alternative logic implementations may require different phase selections.
According to a preferred embodiment, the frequency multiplier 40 comprises P-stages of x2 multipliers. Referring to FIG. 2a, a 1-stage x2 according to an embodiment of the invention comprises a XOR gate 42 for combining two substantially symmetrical clock signals of frequency f, in a quadrature-phase relationship, i.e. presenting approximately a 90 phase difference between the two clocks, to produce substantially symmetrical clock signal of double the frequency f, i.e. 2f. Because of the quadrature-phase relationship, only one transition occurs at a time, hence eliminating any glitches on the output waveform. FIG. 2b shows the waveforms associated with the 1-stage x2 multiplier.
FIG. 3a shows a 2-stage x2 multiplier, comprising 2 XOR gates 44 in the first stage and an XOR gate 42 in the second stage. Each XOR gate in either stage, operates similarly to the XOR gate in FIG. 2a, by receiving a pair of clock signals of frequency f' in a quadrature phase relationship and outputting clock signals of double the frequency f', such that, after two x2 multiplication stage, the output clock signal has frequency 4f". According to the embodiment in FIG. 3a, in order for the second stage to receive signals in quadrature phase relationship, one pair of signals in the first stage should have a 90 /2 (=45 ) phase relationship with the other pair in the first stage. FIG. 3b shows the waveform diagram of clock signals received and produced by the 2-stage clock frequency multiplier x2 in FIG. 3a.
Following a similar approach, a 3-stage x 2 multiplier implemented similarly to those in FIGS. 2a and 3a, would require 4 XOR gates in its first stage, in addition to a 2-stage x 2 multiplier built as in FIG. 3a. In order to propagate the quadrature phase relationship between signal pair entering each XOR gate, the pairs of signals in the first stage may have the following phases, respectively:
(0 ,90 ), (90 /2,90 /2+90 ), (90 /2/2,90 /2/2+90 ) ((900/2+900)/2, (90 /2+90 )/2+90 ). A P-stage x2 multiplier may be built using this approach, inductively.
Referring back to FIG. 1, the frequency divider 20 may comprise a plurality of subdivider circuits, each subdivider circuit performing integer frequency division by N on a clock signal at the reference frequency and at a given phase, received from the multiphase clock generator 10. According to a preferred embodiment, the frequency subdividers are identical and each frequency subdivider may comprise a Ring Shift Register of N flops or Taps, where the N flops may be connected sequentially and the output of the Nth flop may be fed back to the input of the first flop. For example if the frequency of the output waveform is required to be 3 times slower that the reference clock (divide by 3), N is equal to 3, and if output waveform is required to be 4 times slower than the reference clock (divide by 4), N is equal to 4, and so on.
Referring now to FIGS. 4a and 4b, examples of use of Ring Shift Registers 22, 23, 24 to achieve division by N, for N even and N odd, respectively, are illustrated. In the case of N even (N=2k), shown in FIG. 4a, division by N of a clock signal CIk_Ref alpha can be achieved using a shift register 22 of N=2k flops 25, by initializing k consecutive flops 25 with 1 and the remaining flops 25 with 0. It can be noted that in this case, the output clock signal CIk div sym_alpha will be substantially symmetrical.
FIG. 4b illustrates a possible way of achieving a symmetrical clock signal of frequency f/N, for the case when N is odd (N=2k+1). In this case, frequency division by N can be achieved in the same way as in the case of an even N, by initializing k consecutive flops 25 by 1 and the remaining by 0. However, the output from a single ring shift register 23, 24 would not be symmetric. In this embodiment, symmetry is achieved with an OR gate 35a which receives two signals of frequency f/N produced by two identical Ring Shift Registers 23, 24 clocked by two signals of frequency f, with a phase shift of 1800 degrees relative to each other. The signals input to the frequency divider of FIG 4b are denoted with Clk_Ref alpha and respectively CIk_Ref alpha+180. Each ring shift register 23 and 24 shifts the respective input signal to provide a divided clock CIk divN alpha and respectively Clk_divN alpha+180/N. The OR gate 35a in FIG. 4b acts as a waveshaper element, and the output of the waveshaper is a symmetric clock signal denoted with Clk divN_sym_alpha. All waveshaper elements used in a given implementation; could be considered as part of a main waveshaper block (see 35 back in FIG. 1).
According to an alternate embodiment, any one of the taps of a Ring Shift Register can be used as the output of the Ring Shift Register, allowing for various phase selection for the output waveform. According to one embodiment, the initialization of the Ring Shift Register taps is made so that at least one tap is set to logical "1" and at least at least one tap is set to logical "0".
The invention can be better understood from the following example.
FIG. 5 illustrates an example of an embodiment of the invention where it is desired to make the frequency of the reference clock 1.5 the frequency of the output waveform. To generate the intermediate clocks at half the desired output frequency with a quadrature-phase relationship, four Ring Shift Registers 25', 26', 27' and 28' may be used. Each of these Ring Shift Registers has three taps (N=3) and are driven by 4 four reference clocks, Clk Ref_ph0, Clk_Refph90, CIk Ref_ph180 and Clk Ref ph270 with 90 phase difference from each other respectively. The initial values of the flops are indicated by the number inside their corresponding box (e.g. Tap1 in RSR_ph0 has an initial value of logical 1, Tap2 has an initial value logical 0 and Tap3 has an initial value of logical 0).
Each Ring Shift Register will produce a clock with a frequency of 0, where f is the frequency of the reference clock, and with 90 phase difference between each other.
FIG. 6 shows the processing of the frequency divided signals from FIG. 5, by the frequency synthesizer 30', into a final output waveform. A logical OR 35a, is performed on Tap1 of RSR_ph0 and Tap1 of RSR_ph180 to obtain a clock "div3ph0" with a frequency of f/3, 50% duty cycle and 0 degree phase shift relative to Clk Ref_ph0. Similarly, by performing a logical OR on the Tap2 of RSR_ph90 and Tap1 of RSR_ph270 a clock "div3ph90" with a frequency of f/3, 50% duty cycle is obtained. The relative phase between clocks "div3ph0" and "div3ph90" is 90 . The final output is then produced by exclusive ORing (XOR) 42 div3phO and div3ph90 to obtain an output waveform with frequency equal to f/1.5. Signals div3phO, div3ph9O and divlp5phO can be used as outputs.
FIG. 7 shows the timing diagram for the divide by 1.5. Similar circuits can be constructed for other ratios such as, 5/2, 5/4, 7/2, 7/4, etc.
FIGS. 8 and 9 illustrate the phase adjustment capabilities of preferred embodiments of the invention. Clock "div1p5_ph0" is skewed by more than 180 degrees, i.e. (180 + a ), where a is any angle, compared to the ideal clock.
According to embodiments of this invention, the skew can be reduced by advancing intermediate clocks by approximately 180 degree, which will, in turn, cause the output to be advanced by the same angle, hence compensating for most of the skew created due to clock loading. The equations to generate the intermediate signals in this case could be:
div3ph0 = Tap3_ph180 OR Tap1_ph0 div3ph90 = Tap1_ph90 OR Tapl_ph270 where Tap3_ph180 is the output of Flop 3 of Ring Shift Register 28' (RSR_ph270), Tap1_ph0 is the output of Flop 1 of Ring Shift Register 25' (RSR_ph0), Tapl_ph9O is the output of Flop 1 of Ring Shift Register 27' (RSR_ph90) and Tapl_ph270 is the output of Flop 1 of Ring Shift Register 26' (RSR_ph270).
Referring to FIG. 10, additional phase adjustment capabilities may be achieved using a method according to a further embodiment of the invention, referred herein as a time borrowing technique. In a clocked sequential logic network 80, path A 100, between an initial sequential logic block 110 and end sequential logic block 150, is a timing critical path. The timing critical path 100 may run through any logic design, including any combinational and/or sequential logic subblocks.
Prior art clocking techniques might require using lower clock frequency, in order to make the sequential logic network operable. According to further embodiments of the present invention, the prior-art requirement for using lower clock frequency within IC design 80 is alleviated, by borrowing time from a less timing critical path B 100, between the end sequential logic blocks 150 of path A 100 and a third sequential logic block 190, and adding the time towards timing critical path A
200. The time borrowing can be achieved by using dual phase clock outputted by multiphase clock generator 10, where a sequential element such as a flop or set of flops at the end of the timing critical path 100 is triggered with a delayed version of the clock f 0, clock f cp where cp is any non-zero phase delay. In addition to blocks 110 and 150, the integrated circuit 80 may comprise any number of other logic blocks, combinational or sequential, that may receive clocking signals, such as 85, 86. FIG. 11 illustrates an example of an Integrated Circuit Design 80' in an embodiment, according to the invention, using a dual phase clock and applying the time borrowing technique. Delay blocks are illustrated in the accompanying timing diagrams. The phase delay between the two clocks is chosen as 900. In general, the optimal phase delay is design dependent.
Although the present invention has been described in considerable detail with reference to certain preferred embodiments thereof, other versions are possible.
Therefore, the spirit and scope of the appended claims should not be limited to the description of the preferred embodiments contained herein.
Other advantages, objects and features of the present invention will be readily apparent to those skilled in the art from a review of the following detailed description of preferred embodiments in conjunction with the accompanying drawings.
Brief Description of Drawinas The following detailed description, given by way of example and not intended to limit the present invention solely thereto, will best be appreciated in conjunction with the accompanying drawings, wherein like reference numerals denote like elements and parts, where:
FIG. I is a block diagram of a digital fractional clock divider in accordance with one embodiment of the invention;
FIG. 2a is a block diagram of a 1-stage frequency multiplier x2, in accordance with an embodiment of the invention;
FIG. 2b is a waveform diagram of clock signals received and produced by the 1-stage clock frequency multiplier x2 in FIG. 2a;
FIG. 3a is a block diagram of a 2-stage frequency multiplier x2, in accordance with an embodiment of the invention;
FIG. 3b is a waveform diagram of clock signals received and produced by the 2-stage clock frequency multiplier x2 in FIG. 3b;
FIG. 4a is a block diagram of a frequency divider 22, in accordance with an embodiment of the invention;
FIG. 4b is a block diagram of frequency dividers 23, 24 and a waveshaper 35a, in accordance with an embodiment of the invention;
FIG. 5 is a block diagram of a fractional clock divider 20' of a ratio of 1.5, in accordance with an embodiment of the invention;
FIG. 6 is a block diagram of a frequency synthesizer 30', in accordance with the an embodiment of the invention;
FIG. 7 is a waveform diagram of clock signals within the circuit in FIG. 5;
FIG. 8 is a waveform diagram of clock signals within the circuit in FIG. 5, showing skewed output clocks due to loading;
FIG. 9 is a waveform diagram of clock signals within the circuit in FIG. 5, showing a mechanism of correcting the skewed clock signal in accordance with a further embodiment of the invention;
FIG. 10 is a block diagram of an integrated circuit design using a clocking technique according to a further embodiment of the present invention; and FIGS. 11 a and 11 b are example of Integrated Circuits using a prior-art clocking technique and a clocking technique according to the embodiment of the invention in FIG. 10 .
Detailed Description of the Invention In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.
Some portions of the detailed description that follows are presented in terms of waveform diagrams of clock signals (or timing diagrams), digital logic elements such as flip-flops, Ring Shift Registers, OR and XOR gates. These descriptions and representations are consistent with the techniques used by those skilled in the digital processing art to convey the substance of their work to others skilled in the art, and they are not intended to limit the scope of the invention, when equivalent techniques are available in the art for achieving similar results.
In circuits embodying the invention, fractional division is generally accomplished by applying different clock signals having the same frequency as a reference clock signal, but different phases, to integer dividers of ratio N. The resultant waveforms are then passed through P-stage x2 multipliers, where P is the number of stages of a multiply x2 block. A final waveform of ratio N/2P
relative to the reference clock frequency is produced.
Reference is now made to FIG. 1, which illustrates a block diagram of a digital fractional clock divider in accordance with an embodiment of the invention.
The fractional divider in FIG. 1; comprises a multi-phase clock generator 10, a frequency divider block 20 and a frequency synthesizer 30. The multiphase clock generator 10 generates a plurality of phase shifted clock signals of the same reference clock frequency f but with different phases, phO, ph1, etc., relative to the phase of a reference clock. The frequency divider 20 receives the phase shifted clock signals at the clock reference frequency f and divides the frequency of these signals by N, producing a plurality of phase shifted clock signals of frequency f/N. The frequency synthesizer 30 receives the phase shifted signals at frequency f/N and outputs at least one clock signal of frequency f/(N/2P).
In alternative embodiments, the frequency synthesizer 30 may output a plurality of waveforms of frequency f/(N/2P), at different phases relative to each other.
The frequency synthesizer might also output waveforms of frequency f/N. In general, if N is an even number and 2P=1, then you only need 1 phase, if N is an odd number and 2P=1, then you need 2 phases, if N is an odd number and P is 1 or more (i.e. you are dividing by a fraction), then you need more than 2 phases.
The number of phases required to get full symmetrical waveforms is 4P. For example if P= 1 you need 4 phases each phase is 3600/4 apart, and if P = 2 you need 8 phases, each is 360 /8 apart and so on.
In order to achieve the frequency multiplication by 2P of the signals received from the frequency divider 20, the frequency synthesizer 30 comprises a frequency multiplier 40, performing frequency multiplication x2P on the incoming signals. Clock signals received by the frequency synthesizer 30,-may present a substantially high degree of symmetry This may be achieved by various logic implementations of the frequency divider 20 in conjunction with particular values for integer N and may be facilitated by selecting the phases of the phase shifted clock signals generated by the multiphase clock generator 10. These technical aspects would be obvious to a person skilled in the digital processing art.
Without limitation, an implementation example will be provided, showing substantially symmetrical clock signals being outputted by the frequency divider 20 in the case of an even N.
Advantageously, the degree of symmetry of clock signals of frequency f/N may be increased using a waveshaper 35, for balancing any non-symmetrical waveforms of frequency f/N outputted by the frequency divider 20, before performing frequency multiplication within the frequency multiplier 40. The phases of the signals generated by the multiphase clock generator 10; are primarily determined by the degree of symmetry required in the final waveforms and by the logical implementation of the digital fractional clock divider. It will be understood by those skilled in the art, that a compromise between symmetry of final waveforms of frequency f/(N/2P) and the number of phases, which relates to the complexity of digital logic circuitry, might be necessary for more complex ratios N/2P. However, it will also be appreciated that in embodiments of the present invention, fractional frequency division is accomplished mainly with digital logic blocks, without use of complex feedback loops, as in prior-art cases, yet a high degree of symmetry of divided signals can be achieved. An example of how phases can be selected for a given N/2P will be given below. In particular, according to a preferred embodiment, for a divide by 3, two phases are required and for a divide by 1.5, four phases are required. The values of these phases are 0 and 90 in the case of divide by 3 and 00, 90 , 180 and 270 in the case of a divide by 1.5. According to one embodiment of the invention, the number of phases to be selected for achieving substantially symmetrical waveforms at the output is as follows: if N is an even number and 2P=1, then only 1 phase suffices;
if N is an odd number and 2P=1, then 2 phases are sufficient; if N is an odd number and P is greater than or equal to 1, then at least 4P phases would be required. Furthermore, according to this particular embodiment, phases can be equidistant, as follows: if P= 1, four phases approximately 360 /4 apart could be used, whereas for P = 2, eight phases approximately 360 /8 apart could be used required, etc. However it will be recognized by those skilled in the art that alternative logic implementations may require different phase selections.
According to a preferred embodiment, the frequency multiplier 40 comprises P-stages of x2 multipliers. Referring to FIG. 2a, a 1-stage x2 according to an embodiment of the invention comprises a XOR gate 42 for combining two substantially symmetrical clock signals of frequency f, in a quadrature-phase relationship, i.e. presenting approximately a 90 phase difference between the two clocks, to produce substantially symmetrical clock signal of double the frequency f, i.e. 2f. Because of the quadrature-phase relationship, only one transition occurs at a time, hence eliminating any glitches on the output waveform. FIG. 2b shows the waveforms associated with the 1-stage x2 multiplier.
FIG. 3a shows a 2-stage x2 multiplier, comprising 2 XOR gates 44 in the first stage and an XOR gate 42 in the second stage. Each XOR gate in either stage, operates similarly to the XOR gate in FIG. 2a, by receiving a pair of clock signals of frequency f' in a quadrature phase relationship and outputting clock signals of double the frequency f', such that, after two x2 multiplication stage, the output clock signal has frequency 4f". According to the embodiment in FIG. 3a, in order for the second stage to receive signals in quadrature phase relationship, one pair of signals in the first stage should have a 90 /2 (=45 ) phase relationship with the other pair in the first stage. FIG. 3b shows the waveform diagram of clock signals received and produced by the 2-stage clock frequency multiplier x2 in FIG. 3a.
Following a similar approach, a 3-stage x 2 multiplier implemented similarly to those in FIGS. 2a and 3a, would require 4 XOR gates in its first stage, in addition to a 2-stage x 2 multiplier built as in FIG. 3a. In order to propagate the quadrature phase relationship between signal pair entering each XOR gate, the pairs of signals in the first stage may have the following phases, respectively:
(0 ,90 ), (90 /2,90 /2+90 ), (90 /2/2,90 /2/2+90 ) ((900/2+900)/2, (90 /2+90 )/2+90 ). A P-stage x2 multiplier may be built using this approach, inductively.
Referring back to FIG. 1, the frequency divider 20 may comprise a plurality of subdivider circuits, each subdivider circuit performing integer frequency division by N on a clock signal at the reference frequency and at a given phase, received from the multiphase clock generator 10. According to a preferred embodiment, the frequency subdividers are identical and each frequency subdivider may comprise a Ring Shift Register of N flops or Taps, where the N flops may be connected sequentially and the output of the Nth flop may be fed back to the input of the first flop. For example if the frequency of the output waveform is required to be 3 times slower that the reference clock (divide by 3), N is equal to 3, and if output waveform is required to be 4 times slower than the reference clock (divide by 4), N is equal to 4, and so on.
Referring now to FIGS. 4a and 4b, examples of use of Ring Shift Registers 22, 23, 24 to achieve division by N, for N even and N odd, respectively, are illustrated. In the case of N even (N=2k), shown in FIG. 4a, division by N of a clock signal CIk_Ref alpha can be achieved using a shift register 22 of N=2k flops 25, by initializing k consecutive flops 25 with 1 and the remaining flops 25 with 0. It can be noted that in this case, the output clock signal CIk div sym_alpha will be substantially symmetrical.
FIG. 4b illustrates a possible way of achieving a symmetrical clock signal of frequency f/N, for the case when N is odd (N=2k+1). In this case, frequency division by N can be achieved in the same way as in the case of an even N, by initializing k consecutive flops 25 by 1 and the remaining by 0. However, the output from a single ring shift register 23, 24 would not be symmetric. In this embodiment, symmetry is achieved with an OR gate 35a which receives two signals of frequency f/N produced by two identical Ring Shift Registers 23, 24 clocked by two signals of frequency f, with a phase shift of 1800 degrees relative to each other. The signals input to the frequency divider of FIG 4b are denoted with Clk_Ref alpha and respectively CIk_Ref alpha+180. Each ring shift register 23 and 24 shifts the respective input signal to provide a divided clock CIk divN alpha and respectively Clk_divN alpha+180/N. The OR gate 35a in FIG. 4b acts as a waveshaper element, and the output of the waveshaper is a symmetric clock signal denoted with Clk divN_sym_alpha. All waveshaper elements used in a given implementation; could be considered as part of a main waveshaper block (see 35 back in FIG. 1).
According to an alternate embodiment, any one of the taps of a Ring Shift Register can be used as the output of the Ring Shift Register, allowing for various phase selection for the output waveform. According to one embodiment, the initialization of the Ring Shift Register taps is made so that at least one tap is set to logical "1" and at least at least one tap is set to logical "0".
The invention can be better understood from the following example.
FIG. 5 illustrates an example of an embodiment of the invention where it is desired to make the frequency of the reference clock 1.5 the frequency of the output waveform. To generate the intermediate clocks at half the desired output frequency with a quadrature-phase relationship, four Ring Shift Registers 25', 26', 27' and 28' may be used. Each of these Ring Shift Registers has three taps (N=3) and are driven by 4 four reference clocks, Clk Ref_ph0, Clk_Refph90, CIk Ref_ph180 and Clk Ref ph270 with 90 phase difference from each other respectively. The initial values of the flops are indicated by the number inside their corresponding box (e.g. Tap1 in RSR_ph0 has an initial value of logical 1, Tap2 has an initial value logical 0 and Tap3 has an initial value of logical 0).
Each Ring Shift Register will produce a clock with a frequency of 0, where f is the frequency of the reference clock, and with 90 phase difference between each other.
FIG. 6 shows the processing of the frequency divided signals from FIG. 5, by the frequency synthesizer 30', into a final output waveform. A logical OR 35a, is performed on Tap1 of RSR_ph0 and Tap1 of RSR_ph180 to obtain a clock "div3ph0" with a frequency of f/3, 50% duty cycle and 0 degree phase shift relative to Clk Ref_ph0. Similarly, by performing a logical OR on the Tap2 of RSR_ph90 and Tap1 of RSR_ph270 a clock "div3ph90" with a frequency of f/3, 50% duty cycle is obtained. The relative phase between clocks "div3ph0" and "div3ph90" is 90 . The final output is then produced by exclusive ORing (XOR) 42 div3phO and div3ph90 to obtain an output waveform with frequency equal to f/1.5. Signals div3phO, div3ph9O and divlp5phO can be used as outputs.
FIG. 7 shows the timing diagram for the divide by 1.5. Similar circuits can be constructed for other ratios such as, 5/2, 5/4, 7/2, 7/4, etc.
FIGS. 8 and 9 illustrate the phase adjustment capabilities of preferred embodiments of the invention. Clock "div1p5_ph0" is skewed by more than 180 degrees, i.e. (180 + a ), where a is any angle, compared to the ideal clock.
According to embodiments of this invention, the skew can be reduced by advancing intermediate clocks by approximately 180 degree, which will, in turn, cause the output to be advanced by the same angle, hence compensating for most of the skew created due to clock loading. The equations to generate the intermediate signals in this case could be:
div3ph0 = Tap3_ph180 OR Tap1_ph0 div3ph90 = Tap1_ph90 OR Tapl_ph270 where Tap3_ph180 is the output of Flop 3 of Ring Shift Register 28' (RSR_ph270), Tap1_ph0 is the output of Flop 1 of Ring Shift Register 25' (RSR_ph0), Tapl_ph9O is the output of Flop 1 of Ring Shift Register 27' (RSR_ph90) and Tapl_ph270 is the output of Flop 1 of Ring Shift Register 26' (RSR_ph270).
Referring to FIG. 10, additional phase adjustment capabilities may be achieved using a method according to a further embodiment of the invention, referred herein as a time borrowing technique. In a clocked sequential logic network 80, path A 100, between an initial sequential logic block 110 and end sequential logic block 150, is a timing critical path. The timing critical path 100 may run through any logic design, including any combinational and/or sequential logic subblocks.
Prior art clocking techniques might require using lower clock frequency, in order to make the sequential logic network operable. According to further embodiments of the present invention, the prior-art requirement for using lower clock frequency within IC design 80 is alleviated, by borrowing time from a less timing critical path B 100, between the end sequential logic blocks 150 of path A 100 and a third sequential logic block 190, and adding the time towards timing critical path A
200. The time borrowing can be achieved by using dual phase clock outputted by multiphase clock generator 10, where a sequential element such as a flop or set of flops at the end of the timing critical path 100 is triggered with a delayed version of the clock f 0, clock f cp where cp is any non-zero phase delay. In addition to blocks 110 and 150, the integrated circuit 80 may comprise any number of other logic blocks, combinational or sequential, that may receive clocking signals, such as 85, 86. FIG. 11 illustrates an example of an Integrated Circuit Design 80' in an embodiment, according to the invention, using a dual phase clock and applying the time borrowing technique. Delay blocks are illustrated in the accompanying timing diagrams. The phase delay between the two clocks is chosen as 900. In general, the optimal phase delay is design dependent.
Although the present invention has been described in considerable detail with reference to certain preferred embodiments thereof, other versions are possible.
Therefore, the spirit and scope of the appended claims should not be limited to the description of the preferred embodiments contained herein.
Claims (17)
1. A digital fractional clock divider comprising:
a multiphase clock generator for producing a plurality of phase shifted clock signals of reference frequency f , said signals of frequency f having different phases relative to each other ;
a frequency divider for receiving said phase shifted clock signals of frequency f and for producing phase shifted clock signals of frequency f/N, where N is an integer; and a frequency synthesizer for receiving said phase shifted clock signals of frequency f/N and for producing at least a clock signal of frequency f/
(N/2P), wherein P is an integer.
a multiphase clock generator for producing a plurality of phase shifted clock signals of reference frequency f , said signals of frequency f having different phases relative to each other ;
a frequency divider for receiving said phase shifted clock signals of frequency f and for producing phase shifted clock signals of frequency f/N, where N is an integer; and a frequency synthesizer for receiving said phase shifted clock signals of frequency f/N and for producing at least a clock signal of frequency f/
(N/2P), wherein P is an integer.
2. The digital fractional clock divider in claim 1, wherein the frequency synthesizer produces a plurality of signals of frequency f/(N/2P), at different phases relative to each other.
3. The digital fractional clock divider in claim 2, wherein the frequency synthesizer further produces signals of frequency f/N, at different phases relative to each other.
4. The digital fractional clock divider in claim 1, wherein the clock signal of frequency f/(N/2P) produced by the frequency synthesizer is a substantially symmetrical waveform.
5. The digital fractional clock divider in claim 1, wherein the frequency synthesizer further comprises a frequency multiplier, for receiving input signals and comprising digital logic means for multiplying the frequency of said input signals by 2P, where P is an integer.
6. The digital fractional clock divider in claim 5, wherein the frequency synthesizer further comprises a waveshaper, for receiving input signals at a clock frequency and comprising digital logic means for producing substantially symmetrical output signals at said clock frequency.
7. The digital fractional clock divider in claim 5, wherein said frequency multiplier comprises P-stage x2 frequency multiplier blocks.
8. The digital fractional clock divider in claim 7, wherein each x2 frequency multiplier block comprises digital logic means for doubling the frequency of two input signals having same frequency but in quadrature-phase relationship with one another.
9. The digital fractional clock divider in claim 7, wherein each x2 frequency multiplier block comprises XOR gates.
10. The digital fractional dock divider in claim 1, wherein the frequency divider comprises a plurality of frequency subdividers, each frequency subdivider receiving a phase shifted signal of frequency f and producing at least one phase shifted signal of frequency f/N.
11. The digital fractional clock divider in claim 10, wherein each frequency subdivider comprises a ring shift register including N flip flops stages, and wherein the input of each flip flop stage is connected to the output of the following flip flop and the output of the last flip flop is connected to the first flip flop.
12. The digital fractional clock divider in claim 11 wherein each said flip flop stage has only one flip flop.
13. The digital fractional clock divider in claim 12 wherein N/2 consecutive flip flops are initialized to 0.
14. The digital fractional clock divider in claim 12 wherein N/2 consecutive flip flops are initialized to 1.
15. The digital fractional clock divider in claim 12 wherein any said flip-flop stage can be an output of said sub-divider.
16. A clocked sequential network comprising:
a sequential subcircuit including an initial sequential logic block and an end sequential logic block;
a multi-phase clock generator outputting a reference clock signal at a reference frequency f and a phase delayed clock signal at a delayed phase compared to the reference clock signal, the phase delayed clock signal having the same reference frequency, wherein said reference clock signal is received by the initial sequential logic block of the sequential subcircuit and said phase delayed clock signal is received by the end sequential logic block of the sequential subcircuit.
a sequential subcircuit including an initial sequential logic block and an end sequential logic block;
a multi-phase clock generator outputting a reference clock signal at a reference frequency f and a phase delayed clock signal at a delayed phase compared to the reference clock signal, the phase delayed clock signal having the same reference frequency, wherein said reference clock signal is received by the initial sequential logic block of the sequential subcircuit and said phase delayed clock signal is received by the end sequential logic block of the sequential subcircuit.
17
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| CA 2538959 CA2538959A1 (en) | 2006-03-10 | 2006-03-10 | Digital fractional clock divider |
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| CA 2538959 CA2538959A1 (en) | 2006-03-10 | 2006-03-10 | Digital fractional clock divider |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2025080357A1 (en) * | 2023-10-11 | 2025-04-17 | Qualcomm Incorporated | Fractional clock divider |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2025080357A1 (en) * | 2023-10-11 | 2025-04-17 | Qualcomm Incorporated | Fractional clock divider |
| US12524035B2 (en) | 2023-10-11 | 2026-01-13 | Qualcomm Incorporated | NP5 fractional clock divider |
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