CA2017639C - Switching power source means - Google Patents
Switching power source meansInfo
- Publication number
- CA2017639C CA2017639C CA 2017639 CA2017639A CA2017639C CA 2017639 C CA2017639 C CA 2017639C CA 2017639 CA2017639 CA 2017639 CA 2017639 A CA2017639 A CA 2017639A CA 2017639 C CA2017639 C CA 2017639C
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- Canada
- Prior art keywords
- inductor
- switch element
- power source
- switching power
- switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- 230000003071 parasitic effect Effects 0.000 claims abstract description 53
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- 238000007599 discharging Methods 0.000 claims description 11
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- 230000033228 biological regulation Effects 0.000 claims description 4
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- 230000020169 heat generation Effects 0.000 description 3
- 230000002265 prevention Effects 0.000 description 3
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
- H03K17/0814—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit
- H03K17/08142—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit in field-effect transistor switches
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
- H02M7/42—Conversion of DC power input into AC power output without possibility of reversal
- H02M7/44—Conversion of DC power input into AC power output without possibility of reversal by static converters
- H02M7/48—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/505—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means
- H02M7/515—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only
- H02M7/523—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only with LC-resonance circuit in the main circuit
- H02M7/5233—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only with LC-resonance circuit in the main circuit the commutation elements being in a push-pull arrangement
- H02M7/5236—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only with LC-resonance circuit in the main circuit the commutation elements being in a push-pull arrangement in a series push-pull arrangement
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/04—Modifications for accelerating switching
- H03K17/041—Modifications for accelerating switching without feedback from the output circuit to the control circuit
- H03K17/0416—Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the output circuit
- H03K17/04163—Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the output circuit in field-effect transistor switches
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
- Inverter Devices (AREA)
- Power Conversion In General (AREA)
Abstract
A switching power source means comprises a DC
voltage source, a first switch element, a low-pass filter connected to the DC voltage source through the first switch element, and a second switch element connected to the input end of the low-pass filter, the switch elements being coupled to the DC voltage source either directly or through a transformer and being operable in such a manner that an output of DC or AC at a desired frequency can be derived across the output end of the low-pass filter. With the invention, an inductor is connected in parallel across the input end of the low-pass filter, to charge and discharge parasitic capacitances of the switch elements, preferably by being provided with a saturable core accompanied by an addi-tional winding supplied with a load current, thus preventing surge currents in the switch elements.
voltage source, a first switch element, a low-pass filter connected to the DC voltage source through the first switch element, and a second switch element connected to the input end of the low-pass filter, the switch elements being coupled to the DC voltage source either directly or through a transformer and being operable in such a manner that an output of DC or AC at a desired frequency can be derived across the output end of the low-pass filter. With the invention, an inductor is connected in parallel across the input end of the low-pass filter, to charge and discharge parasitic capacitances of the switch elements, preferably by being provided with a saturable core accompanied by an addi-tional winding supplied with a load current, thus preventing surge currents in the switch elements.
Description
~o~ 9 SWITCHING POWER SOURCE MEANS
This invention relates to a switching power source means having a DC voltage source with at least two switch elements connected thereto, so as to produce a DC output, or an AC output at a desired frequency, by 05 turning on and off the switch elements in an alternate manner. In particular, the invention relates to preven-tion of surge currents and switching losses due to parasitic capacitors in the switching power source means.
A switching power source means of the above-mentioned type is generally small and highly efficient, and has been widely used, for instance, as a power source for a computer data processing system. In the case of a power source means with a large output capacity, or an AC power source means producing sinusoidal AC output from a DC power source, the power source means is often made controllable by connecting paired switch elements thereto so as to regulate the power or frequency of its output simply by alternately changing over the operating state of the switching elements.
Fig. 6 shows a circuit diagram of a typical 201~6~39 example of a conventional controllable power source means. The waveforms at different points in the circuit thereof are shown in Figs. 7A and 7B. Paired switch elements, i.e., a first switch element l and a second 06 switch element 2, are joined in series at a point 7 and serially connected across a DC voltage source 5. A low-pass filter, which is formed of a choke coil 3 and a capacitor 4, is connected to the DC voltage source 5 through the first switch element l. The input end of the low-pass filter i-s connected in parallel with the second switch element 2. A load 6 is connected in parallel with the output end of the low-pass filter.
If switch elements l and 2 are alternately turned on and alternately turned off, while changing the ratio between ON-time and OFF-time of the switch element 2 in a sinu-soidal manner, a series of pulse width modulated (PWM) voltage pulses are generated at the point 7 as shown by the curve in Fig. 7A. After elimination of switching frequency component and harmonics from the series of the ao voltage pulses by the low-pass filter made of the choke coil 3 and the capacitor 4, a sinusoidal AC output voltage can be obtained as shown by the curve in Fig. 7B.
The above functional description of the switching power source means of Fig. 6 is based on the assumptions that the switch elements l and 2 perform 2017~3q an exactly rectangular ON-OFF switching operation as ideal switch elements can do, and the control signals for driving the ON-OFF operation are also exactly rectangular. Performance of actual switch elements to 05 be used, however, deviates from the above-mentioned exact rectangular switching operation due to intrinsic characteristics of individual switch elements, which causes certain difficulties during switching operation.
The difficulties during the switching operation will be explained by referring to a typical switch element of a metal oxide semiconductor field effect transistor (MOS-FET) of Fig. 8. MOS-FET's are quite frequently used as the switch elements l and 2 of Fig. 6. The circuit of Fig. 8 is essentially the same as that of Fig. 6 except that MOS-FETl and MOS-FET2 are used as the switch elements l and 2 respectively.
The MOS-FET is different from a conventional bipolar transistor in that the MOS-FET is free from delay in turn-off operation due to storage time caused by residual carriers. Thus, if control signals applied to the gates of MOS-FETl and MOS-FET2 of Fig. 8 are exactly rectangular, simultaneous ON states of the MOS-FETl and MOS-FET2 will never occur. However, the actual MOS-FET has a comparatively large parasitic capacitor between its drain and source on the order of about several hundred pF to several ten pF. At the time of turn-ON and turn-OFF of the paired MOS-FETl and MOS-FET2, there is a serious problem of how to handle the electric charge stored in the parasitic capacitors so as to eliminate adverse effects of the stored charge on the 05 turning ON and turning OFF function.
Fig. 9 shows an equivalent circuit of a MOS-FET.
Due to its configuration, parasitic capacitors are inevitable; namely, Cdg between the gate and the drain, CdS between the drain and the source, and Cgs between the gate and the source. The value of resistance RdS between the drain and the source varies greatly from almost zero to infinity depending on the gate-source voltage, and the zero value corresponds to the ON state and the infinity value corresponds to the OFF state.
A parasitic diode Do must be considered between the drain and the source.
Phenomena relating to the turn-ON and turn-OFF
of the equivalent circuit of Fig. 9 will now be explained. Electric charge stored in the drain-source parasitic capacitor CdS of each MOS-FET is discharged through the drain-source resistance Rds when it is turned ON. Hence, when the paired MOS-FET's are switched over from one to the other, a large surge current is produced. For example, a large surge current flows through the ON-state drain-source resistance RdS Of the MOS-FET2 when the MOS-FET2 is turned ON from its OFF
state. The surge current is due to two reasons, namely, the drain-source parasitic capacitor Cds of the MOS-FET2 is discharged through the ON-state drain-source resist-ance Rds, and the drain-source parasitic capacitor CdS of 05 MOS-FETl is directly charged by the DC voltage source 5 through the ON-state drain-source resistance RdS of the MOS-FET2. Similarly, a large surge current flows through the ON-state drain-source resistance RdS of the MOS-FETl when the MOS-FET2 is turned OFF and the MOS-FETl is turned ON due to the same two reasons as described above.
As a result, the charge stored in the drain-source parasitic capacitor CdS of each MOS-FET of the paired switch elements of Fig. 8 causes a large surge current through the ON-state drain-source resistance RdS
when the two-MOS-FET's are switched over from one to another. The energy of such surge current is converted into and consumed as heat, which means not only power loss and temperature rise of the switch element but also generation of noise. Further, intensity of such phenomenon increases with the increase of the switching frequency of the paired switch elements. Thus, the occurrence of such surge current makes it very difficult to use high frequency switchover of the paired switch 26 elements of the switching power source means. Further, if the peak value of such surge current is too high, ~7~
it may cause break-down of the switch elements.
Several protective methods against the surge current accompanying the switchover of the switch elements have been proposed. Fig. 10A through Fig. 10C
05 illustrate some of them. Gate resistors 8al and 8a2 of several hundred ohms are serially connected to the gates of the MOS-FETl and MOS-FET2 as shown in Fig. 10A.
Functions of such gate resistors include the reduction of the rise-rate of the gate-source voltage of each MOS-FET, the gradual change of the value of the drain-source resistance Rds of each MOS-FET at the time of switchover, and the suppression of the peak value of the surge current even if not eliminated. Fig. 10B shows the case in which two saturable magnetic cores 8bl and 8b2 are connected in series to the MOS-FETl and MOS-FET2, respectively. Snubber circuits 8Cl and 8C2~ each comprising for instance a resistor and a capacitor, are connected in parallel to the MOS-FETl and MOS-FET2, respectively, as shown in Fig. 10C.
The inventors found that the conventional protective methods could not ensure complete prevention of the occurrence of the above-mentioned surge current.
Even if the protective methods are used, electric charge stored in the parasitic capacitors of the MOS-FET's is eventually consumed as heat in the drain-source resist-ance RdS. Thus, with increase of the frequency of switchover of switch elements in the switching power source means, its power consumption or heat generation increases. In short, prevention of occurrence of the surge current and reduction of switching loss at 05 switchover of the switch elements is a very important problem to be solved in the conventional switching power source means.
Therefore, an object of the present invention is to solve the above-mentioned problems of the prior art by providing an improved switching power source means which prevents occurrence of the surge current due to parasitic capacitors of switch elements and of a transformer, if used, so as to enable high efficiency and size reduction of such means.
16 A switching power source means according to the invention has a DC voltage source, a first switch element, a low-pass filter connected to the DC voltage source through the first switch element, and a second switch element connected to the input end of the low-pass filter, in which switch elements are operable in such a manner that a DC output or an AC output at a desired frequency can be produced across the output end of the low-pass filter. Further, an inductor is connected in parallel to one of the switch elements, e.g., the 2~ second switch element, to charge and discharge parasitic capacitors of the switch elements, so as to prevent the B~
20~ 7639 ~ surge currents in the switch elements.
With the inductor connecte~ across the second switch element, no surge current is caused at switchover of the switch elements, and it is made possible to 05 provide a small yet highly efficient switching power source means which is particularly suitable for use in a DC constant-voltage power source, an inverter, an AC
uninterruptible power supply, a battery charger, controllers of motors of various types, and the like.
For a better understanding of the invention, reference is made to the accompanying drawings, in which:
Fig. 1 is a circuit diagram of the first fundamental configuration of a switching power source 1~ means according to the invention;
Fig. 2A shows waveforms of current and voltage at point 7 in the power source means of Fig. l;
Fig. 2B shows current versus efficiency charac-teristics of the power source means of Fig. 1 in the case of producing an AC output;
Fig. 2C shows current versus efficiency charac-teristics of the power source means with a circuit configuration of Fig. 4 in the case of producing a DC
output;
Fig. 3 is a circuit diagram of a forward type power source to which the switching power source means 6~9 of the invention is applied;
Fig. 4 is a circuit diagram of a half-bridge type DC power source to which the switching power source means of the invention is applied;
05 Fig. 5 is a circuit diagram of a full-bridge type power source to which the switching power source means of the invention is applied;
Fig. 6 is a circuit diagram of the essential configuration of a conventional switching power source means;
Figs. 7A and 7B show waveforms of voltages at different points of the essential configuration of Fig. 6;
Fig. 8 is a circuit diagram of the formation of a conventional switching power source means which uses MOS-FET's as switch elements;
Fig. 9 is an equivalent circuit of a MOS-FET;
Fig. 10A through Fig. 10C are circuit diagrams of conventional methods for preventing surge currents in switch elements, respectively;
Fig. ll is a circuit diagram showing the second fundamental configuration of a switching power source according to the present invention;
Fig. 12A is a diagram showing waveforms of voltage at point 7 in the power source of Fig. ll;
Fig. 12B is a diagram showing waveforms of 20 i 7639 inductor current without bias applied in the power source of Fig. 11;
Fig. 12C is a diagram showing waveforms of inductor current with bias applied in the power source of 06 Fig. 11;
Fig. 12D is a diagram showing waveforms o-f current from point 7 in the power source of Fig. 11;
Fig. 13 is a circuit diagram showing the third fundamental configuration of a switching power source according to the present invention;
Fig. 14 is a circuit diagram showing an embodi-ment of a backboost type switching power source according to the present invention;
Fig. 15 is a circuit diagram showing another 16 embodiment of a forward type switching power source according to the present invention;
Fig. 16 is a circuit diagram showing another embodiment of a half-bridge switching power source according to the present invention; and Fig. 17 is a circuit diagram showing another embodiment of a full-bridge switching power source according to the present invention.
- Throughout different views of the drawing, 1, 2, 11, 13, 14 are switch elements (MOS-FET's), 3 is a choke 26 coil, 4, 10, 12, 16 are capacitors, 5 is a DC voltage source, 6 is a load, 7 is a point, 8al, 8a2 are gate .
resistors, 8bl, 8b2 are saturable magnetic cores, 8Cl~ 8C2 are snubber circuits, 9, 15 are inductors, and 9S is a saturable inductor.
The invention will be described in further 05 detail by referring to embodiments.
Fig. 1 shows the basic circuit of a switching power source means according to the invention. In the figure, MOS-FETl and MOS-FET2 are examples of switch elements 1 and 2 of the ensuing embodiments. The output voltage from the switching power source means is controlled by turning ON and turning OFF the switch elements 1 and 2 alternately so as to regulate the duration ratio of ON state and OFF state, as in the case of conventional switching power source means. At each 1~ switchover from one switch element to another, "dead time" is provided during which the two switch elements are both in OFF state.
The embodiment of Fig. 1 is different from the prior art in such a way that a series circuit of an inductor 9 and a capacitor 10 is connected across the second switch element 2 or MOS-FET2 in Fig. 1.
The inductor 9 stores energy in the form of current therein during a half cycle prior to the dead time, and the stored energy is used for charging and discharging 2~ of parasitic capacitors of the switch elements during the dead time. Thus, the internal resistance of the switch elements is freed from adverse effects of charg-ing currents to and discharging currents from parasitic capacitors of the switch elements. A capacitor 10 is used to cut off a DC component in the voltage at point 05 7. The capacitance of the capacitor 10 is selected in such a manner that the resonant frequency of the circuit formed of the inductor 9 and the capacitor 10 is much lower than the switching frequency of the switch elements l and 2. The voltage appearing across the capacitor 10, which is almost constant, depends on both the voltage of the voltage source 5 and time ratio of switching.
In operation, when the MOS-FETl is turned ON, a current is fed from the DC voltage source 5 to the inductor 9 through the ~OS-FETl and energy is stored in the inductor 9. At the moment of turn-o~F of the MOS-FETl, the voltage at point 7 is held by the parasitic capacitors across the switches, hence FETl is turned off with zero voltage switching. The current in the inductor 9 cannot change rapidly and it varies in a continuous manner while charging the drain-source parasitic capacitors Cds of MOS-FETl and discharging the drain source parasitic capacitor Cds of MOS-FET2. Thus, the voltage at point 7 decreases substantially linearly.
2~ After the voltage at point 7 reaches zero, the current in the Lnductor 9 continues to flow through the parasitic diode Do of MOS-FET2 ( see .Fig. 9). In the interval of diode Do conduction , FET2 is turned ON. Thus the zero voltage switching is realized in FET2 at turn-on and there is no current surge. When FET2 is ON, the current 05 from the inductor 9 varies at a certain slope in response to the change of the voltage of the capacitor 10 and changes its polarity.
When the switchover is from FET2 to FETl, the - same kind of zero voltage switching arises. In this case, however, the direction of the current from point 7 has been reversed. When MOS-FET2 is turned OFF, parasitic capacitor CdS of MOS-FET2 is charged and parasitic capacitor Cds of MOS-FETl.is discharged by the energy stored in the inductor 9. AS a result, the voltage at point 7 increases gradually until it reaches to the voltage of the voltage source 5. Zero voltage switching is therefore realized at turn-off of FET2.
After the voltage at point 7 reaches to the voltage of voltage source 5, the energy in the inductor 9 is recovered to the voltage of the source 5 through the parasitic diode Do of the MOS-FETl. During the conduction of diode Do of MOS-FETl, FETl is turned ON.
Hence zero voltage switching in FETl is realized, too.
When FETl is ON, the current in the inductor 9 increases with a certain slope, and changes its polarity. Next, the same operation is repeated. The charging and B
discharging of the parasitic capacitors of the MOS-FET's through the drain-source resistors Rds Gf the MOS-FET's is prevented by the energy stored-in the inductor 9.
The voltage at and the current from point 7 will 05 be discussed now in detail. The upper graph of Fig. 2A
shows the theoretical waveform of voltage at point 7 r while the lower graph of Fig. 2A shows the theoretical waveform of current from point 7. In the two graphs, solid lines are for no-load conditions and dash lines are for loaded conditions. Fig. 2B and Fig. 2C show measured values of efficiency versus load current Io characteristics for the configura~ion of Fig. l and for the configuration of Fig. 4, respectively. High efficiency of the means of the invention was proved;
namely, about 95% for the case of Fig. 2B and about 85%
for the case of Fig. 2C.
In Fig. l, if the voltage of the voltage source 5 is represented by Ei and the time ratio of the ON
period of the switch element 1 is represented by Dr a voltage DEi appears across the capacitor 10. If the inductance of the inductor 9 is designated by L,-!the switching frequency is designated by f and the output current is designated by Ior the peak current ILmaX of the inductor 9, i.e., the current through inductor 9 when both of MOS-FETl and MOS-FET2 are OFF, can be given by the following equation.
~, .~ -....
ILmaX=Ei(l-D)D/2fL ........... (1) In deriving the equation (1), one assumption was used;
namely, the switchover time between the switch elements 1 and 2 is sufficiently short as compared with the ON
06 time of the switch element 1 or 2.
The current i through point 7 can be given by the following equation (2) for the ON time of the MOS-FETl and by the following equation (3) for the ON time of the MOS-FET2.
i=[Ei(l-D)t/L]-[D(l-D)Ei/2 f L]+Io ....... ..... (2) i=[Ei D t/L]~[D(l-D)Ei/2 f L]+Io ......... (3) When the MOS-FETl or the MOS-FET2 is switched from the ON state to OFF state, the parasitic capacitors of the MOS-FETl and MOS-FET2 are charged by the energy - 16 stored in the inductor 9, and the voltage at polnt 7 varies. If the total capacitance of the entire drain-source parasitic capacitors of the MOS-FETl and MOS-FET2 as seen from point 7 is represented by C, the internal resistance of the inductor g is rep~esented by r, and the current of the inductor 9 at turn-off time of the MOS-FET's is represented by IL~ then the voltage u at point 7 and the current i through point 7 can be given by the following equations (4) and (5) for switchover of ON
state from MOS-FETl to MOS-FET2 and by the following 26 equations (6) and (7) for switchover of ON state from MOS-FET2 to MOS-FETl.
~ 20 1 7639 u=e~at[(Ei-Ec+rIL)cos~t+{a(Ei-Ec+rIL) -(IO+IL)/C} (l/~)sin~t]+(Ec-rIL) ......... (4) i=e~at[(IO+IL)cos~t +{(Ei-Ec)/L-a(IO+IL)} (1/~)sin~t] ............. (5) 05 u=e~at[(-Ec+r IL ) cos~t+{a(-Ec+r IL ) -(-IO+IL)/C}-(l/~)sin~t]+(Ec-rIL) ............. (6) i=e~at[(-IO+IL)cos~t +{(-Ec)/L+a( Io+IL ) } ( 1~ ) sinwt] .. ..(7) where, a=r/2L and ~=~J1/LC-1.
If the internal resistance r of the inductor 9 is sufficiently small and the time necessary for the voltage at point 7 to change into its next state is sufficiently short as compared with the intrinsic period of LC, the above equations (4) through (7) can be 16 simplified as the following expressions (8) through (ll) with a sufficient degree of approximation, respectively.
For the switchover of ON state from MOS-FET1 to MOS-FET2 u=Ei-( Io+ILmax ) t/c ---- (8) i=Io+ILmax+ ( Ei-Ec)-t/c ......... (9) For the switchover of ON state from MOS-FET2 to MOS-FETl U=(ILmax--Io)-t/c ......................... (10) i= ( ~Io+ILmax ) -Ec t/c ................ (ll) The equations (8) through (ll) show that the variation of the voltage at point 7 is substantially 2~ linear. With the condition for positive slope of the voltage of the equation (10), the peak value ILmaX of the ~'; .
~ 201 7639 -inductor current and the load current Io must-~satisfy the following conditions.
io<ILmax=Ei(l-D)D/2-f-L .......... (12) During the switchover of the voltage at point 7, 05 the two MOS-FET's must be simultaneously OFF, and the dead time Td during which both of the two MOS-FET's are OFF can be derived as follows from the equation (ll).
Td2Ei C/(Io~ILmax) ............... (13) As can be seen from the foregoing description, with the circuit configuration of the invention, it is possible to completely eliminate surge currents due to the charging and discharging of parasitic capacitors of the switch elements through the internal resistances of such switch elements at switchover of-switch elements.
Further, values of constants necessary in the invention such as the inductance of the inductor 9 and the duration of the dead time can be determined by use of the simple equations.
With the prior art, several methods have been used to protect switch elements against the surge current at the time of switchover of the switch elements and to prevent noise in the voltage and current due to such surge currents; namely, connection of gate resistors of several hundred ohms to the gates of MOS-FET's for reducing the rate of rise of the gate voltage,suppression of the current peak value by gradually ~9 reducing the drain-source resistance of the MOS-FET to its complete ON state at the time of its turn-ON, and use of means for preventing sudden changes of voltage and current such as the snubber circuits formed of 05 resistors and capacitors. However, such conventional methods could not ensure complete elimination of the surge current, and the electric charge stored in the parasitic capacitors of the MOS-FET's are eventually consumed in the ON-state drain-source resistance of each MOS-FET. Thus, with the increase of frequency of the switchover of the switch elements, problems of increased power consumption and increased heat generation are inevitable, and such problems have not been solved.
In the above description of the principles of the invention, MOS-FETl and MOS-FET2 are used as examples of the switch elements 1 and 2. When bipolar transistors, gate turn off transistors (GTO), or regular thyristors are used as the switch elements of the switching power source means, parasitic capacitors of such transistors and thyristors also cause problems similar to those related to the MOS-FET'S. The inven-tion can solve the problems accompanying with the use of the above transistors and thyristors.
Thus, the invention can reduce the number of 26 surge absorbing elements in the switching power source means compared with the conventional power source means 201 763~
of similar type. Since the power consumption at the time of switchover can be kept low, the frequency of the switchover can be increased, and various components such as the smoothing choke coils and capacitors can be made 05 small. When applied to the output voltage control, the invention can permit a faster response and facilitate more sophisticated fine control of the output voltage.
Other embodiments will be described now. Fig. 3 shows a forward type switching power source to which the present invention is applied. Switch elements 1 and 2 are paired, and when one of them is ON the other is controlled to be OFF. A switch element 11 is so controlled as to turn-ON and turn-OFF substantlally simultaneously with the switch element 1. During switchover of the switch elements 1, ll and 2, the energy stored in the inductor 9 is used to charge and discharge parasitic capacitors of such switch elements 1, ll, 2 and a transformer Tl.
Fig. 4 shows a half-bridge type power source, in which output end of a switching power source means of the invention is connected to the primary winding of a transformer T2 and the output is rectified by diodes D2 and D3 that are connected to the secondary winding of the transformer T2, so as to provide a DC output.
as Switch elements l and 2 are paired, and when one of them is ON the other is controlled to be OFF. The power B
- ~ 201 763q source of Fig. 4 uses a capacitor 12 for cutting off the DC component of the output from the switching power source means of the invention. During switchover of the switch elements 1 and 2, the energy stored in the 05 inductor 9 is used to charge and discharge parasitic capacitors of such switch elements 1, 2 and the transformer T2. Parasitic capacitors across terminals of the diodes D2 and D3 are also charged and discharged by the energy stored in the inductor 9, and surge currents due to recovery currents (reverse direction currents caused during the switchover) never occur.
Fig. 5 shows a full bridge inverter circuit.
The AC voltage produced by the switching power source means of the invention is applied to the primary winding lB of a transformer T3, and rectified by diodes D2 and D3 connected to the secondary winding of the transformer T3. Switch elements 1 and 2 are paired, and switch elements 13 and 14 are similarly paired. When one of the paired switch elements is ON the other one of the paired switch elements is controlled to be OFF. A DC
output of any desired magnitude can be produced by controlling phase difference between the switching element 1-2 pair and the switching element 13-14 pair.
In this embodiment, the energy stored in inductors 9 and 15 is used to charge and discharge parasitic capacitors of the switch elements, the transformer, and the diodes during switchover of the switch elements.
The switch elements 1, 2, 13 and 14 in the embodiments of Fig. 3 through Fig. 5 can be MOS-FET's, bipoIar transistors, GTO's, thyristors, or diodes.
06 In the embodiments as described hereinbefore in detail, the wattless current IL as indicated by solid lines in the lower graph of Fig. 2A, which flows through - the inductor 9 employed in the funda~lental configuration as shown In Fig. 1, flows through within the switch elements FETl and FET2. So that, the losses in the equivalent resistances within the switch circuits and the losses in ON-state drain-source resistance of switch elements are increased. Furthermore, in order to effectively charge and discharge the parasitic 16 capacitors across the switch elements, it is required that the amplitude value ILmaX of the inductor current should be larger than that of the load current Io~ as described before.
On the other hand, a current corresponding to the sum of the load current Io and the inductor current IL~ that is, the current indicated by dash lines in the lower graph of Fig. 2A flows from point 7 in the fundamental configuration as shown in Fig. 1, and, as a result, a peak current equal to twice of the load 26 current Io flows through the switch elements FETl and FET2 on the maximum load. Therefore, it is required to ;~:`St '-select semiconductor devices having a large current capacity for the switch elements FETl, FET2. Moreover, a wattless current with a peak value larger than the load current Io always flows through the inductor 9.
05 Hence it is required to increase the diameter of the windings of the inductor 9 for reducing the power loss caused on the inductor 9.
In order to remove the above-mentioned defects of the switching power source of inductor-current diversion type based on the fundamental configuration as shown in Fig. 1 according to the present invention, in which an inductor is connected in parallel with switch elements to divert the charging and discharging currents of parasitic capacitors of those switch elements into 1~ an inductor current, a saturable core is used for the inductor concerned, so as to give a non-linear property thereto and hence to make the most of the merit of the inductor-current diversion. Moreover, if the induct~or made of the saturated core is further provided with an additional winding through which the load current flows, so as to be applied with a bias in response to the load current, the most profitable charging and discharging current required for the inductor-current diversion can be always obtained.
The second fundamental configuration of the improved switching power source of the present invention . . ; .
is shown in Fig. ll. In the original fundamental configuration, when switch element FETl is in ON-state, the voltage stored in the parasitic capacitor across the drain and the source of the switch element FETl is zero, 05 while the source voltage Ei is applied to the parasitic capacitor across the drain and the source of switch element FET2. In this condition, when the switch element FETl is turned OFF at a fairly high switching speed, the switching is completed in a condition such as the electric.charge stored in the parasitic capacitor across the drain and the source of the switch element FETl is substantially zero. However, when switch element.FET2 is turned ON immediately after the switch element FETl is turned OFF, both of the discharge current of the parasitic capacitor of FET2 and the charge current of the parasitic capacitor of FETl flow through the conduction resistance of switch element FET2. As a result, an abrupt large surge current is generated within the switch element FET2 r and hence the heat and the noise are further generated.
In contrast therewith, in the improved fundamental configuration, a saturable inductor 9S is connected across the switch element FET2, so that the core of the inductor 9S is saturated a little while a5 before one of switch elements, for instance, FETl is turned OFF. As a result, an inductor current in such B?
~ an operational waveform as-shown in Fig. 12B flows through the saturable ind-~ctor 9S. Figs 12A through 12D
show several operational waveforms in the improved fundamental configuration. In other words, during the 06 saturation of the saturable inductor 9S, a current supplied from the DC voltage source 5 through the switch element FETl is stored in this saturated inductor 9S
When a dead time duration having a suitable time length is provided after the switch element FETl is turned OFF, the current flowing through the saturable inductor 9S
tends to maintain the present state of current flow.
Hence, the electric charge stored in the parasitic capacitor across the drain and the source of the switch element FET2 is discharged, while the parasitic 16 capacitor across the drain and the source of the switch element FETl is charged by the peak of this maintained current. As a result, the terminal voltage across the switch element FET2 decreases with a certain inclina-tion. If switch element FET2 is turned ON after this terminal voltage reaches to zero, the zero voltage switching can be realized.
Moreover, even when the ON state is switched over from the switch element FET2 to the switch element FETl on contrary to the above, the zero voltage 2~ switching similar to the above can be realized by providing the dead time duration having the suitable B
L
time length similar to the above, and furthermore, since the current flowing through the inductor 9S is the wattless current, those currents flowing to charge and to discharge the parasitic capacitors do not cause any 06 power loss at all. Furthermore, since the inclination of the variation of terminal voltages across the switch elements FETl and FET2 is determined by the capacitance of the parasitic capacitors across those elements, the peak value ILmaX of the inductor current, and the load current Io,-the power loss and the noise which are caused by the abrupt change of the current or the voltage, that is, the surge current or the surge voltage, can be prevented by selecting suitable values of those causing factors.
16 In this connection, the current, which charges or discharges the parasitic capacitors across the switch elements FETl and FET2, corresponds to the sum of the inductor current IL and the load current Io in case the ON
state is switched over from the switch element FETl to the switch element FET2, while the current concerned corresponds to the difference between the inductor current IL and the load current Io in case the ON state is switched over from the switch element FET2 to the switch element FETl. Consequently, if the peak values 26 of the inductor currents IL flow through the current-diversion inductor 9S are equal to each other, the ~. .
`~ ` 201 7639 inclination of the terminal voltage across the switch element becomes steep in case the ON state is switched over from the switch element FETl to the switch element FET2, while the inclination concerned becomes gentle.
05 As a result, when the load current Io exceeds the peak value ILmaX Of the inductor current, the current diversion through the inductor 9S cannot be realized.
However, the aforesaid difficulty can be removed by providing the core of the saturable inductor 9S with an additional winging through which the load current Io flows, so as to apply a bias responding to the load current Io to the saturable core concerned. An example of the configuration of the switching power source of the present invention in which the core of the saturable 16 inductor 9S is applied with;the bias responding to the load current Io is shown in Fig. 13, while the waveforms of the induct~r current IL and the current flowing from point 7 in the example as shown in Fig. 13, are shown in Figs. 12C and 12D respectively. In the configuration as shown in Fig. 13, which is arranged so that the bias responding to the load current is applied to the core of the saturable inductor 9S, the positive peak value of the inductor current IL is decreased, while the negative peak value thereof is increased, as shown in Figs. 12C and a5 12D. As a result, the saturable core is appropriately biased, such that an excessive peak current flowing ~ . .
20 1 763~
.
through the switch elements on the bias of the increased load current Io can be prevented, as well as the charging current or the discharging current of the parasitic capacitor, which is required for thei-inductor 05 current diversion, can be provided. Furthermore, at the instant at which the terminal voltages across the switch elements are switched over between each other, the current flowing from point 7 is maintained at constant, so that the inclination of the voltage variation at this instant is maintained at constant, too, and hence the noise caused by the abrupt change of the voltage can be prevented, too.
As described above, in the inductor current diversion type switching power source of the present invention, a saturable core is used for the current diversion ~Inductor~ so that the condition required for realizing the charge and the discharge of parasitic capacitors across the switch elements is always satisfied, and hence it is possible to prevent the power - 20 loss caused by the larger wattless current which tends to be generated when the current diversion inductor is formed of an air-cored linear inductor without satur-ation of core.
The principle of the improvement of the switch-2~ ing power source according to the present invention,which is referred to the improved fundamental configura-tion shown in Fig. 11, provided by modifying the original fundamental configuration shown in Fig. 1, can be generally applied to any kind of switching power source in which paired switch elements are controlled to 05 be alternately switched over. Therefore, the embodi-ments of the present invention which are referred to Figs. 3 to S provided by modifying the original fundamental configuration as shown in Fig. 1 can be applied with the same principle of improvement together with the same effect. For example, an embodiment of the switching power source according to the present inven-tion, in which the aforesaid principle of improvement is applied to a power source of backboost type, is shown in Fig. 14, another embodiment thereof, in which the 16 aforesaid principle of improvement is applied to a forward type power source as shown in Fig. 3, being shown in Fig. 15, another embodiment thereof, in which the aforesaid principle of improvement is applied to an inverter rectifying DC power source as shown in ao Fig. 4, being shown in Fig. 16, and another embodiment thereof, in which the aforesaid principle of improvement is applied on a full-bridge type power source as shown in Fig. 5, being shown in Fig. 17. In other words, the principle of improvement according to the present 26 invention can be generally applied to the switching power sources of this kind including various bridge type 2~1~9 power sources and hence similar effects of improvement can be obtained.
As can be seen from the foregoing detailed description, the outstanding effects of the invention 05 can be summarized as follows.
(l) A high efficiency of electric power in the switching power source means is achieved.
(2) Due to the reduction of heat generation at constituent elements, heat dissipating fins and other fringe parts can be made small.
This invention relates to a switching power source means having a DC voltage source with at least two switch elements connected thereto, so as to produce a DC output, or an AC output at a desired frequency, by 05 turning on and off the switch elements in an alternate manner. In particular, the invention relates to preven-tion of surge currents and switching losses due to parasitic capacitors in the switching power source means.
A switching power source means of the above-mentioned type is generally small and highly efficient, and has been widely used, for instance, as a power source for a computer data processing system. In the case of a power source means with a large output capacity, or an AC power source means producing sinusoidal AC output from a DC power source, the power source means is often made controllable by connecting paired switch elements thereto so as to regulate the power or frequency of its output simply by alternately changing over the operating state of the switching elements.
Fig. 6 shows a circuit diagram of a typical 201~6~39 example of a conventional controllable power source means. The waveforms at different points in the circuit thereof are shown in Figs. 7A and 7B. Paired switch elements, i.e., a first switch element l and a second 06 switch element 2, are joined in series at a point 7 and serially connected across a DC voltage source 5. A low-pass filter, which is formed of a choke coil 3 and a capacitor 4, is connected to the DC voltage source 5 through the first switch element l. The input end of the low-pass filter i-s connected in parallel with the second switch element 2. A load 6 is connected in parallel with the output end of the low-pass filter.
If switch elements l and 2 are alternately turned on and alternately turned off, while changing the ratio between ON-time and OFF-time of the switch element 2 in a sinu-soidal manner, a series of pulse width modulated (PWM) voltage pulses are generated at the point 7 as shown by the curve in Fig. 7A. After elimination of switching frequency component and harmonics from the series of the ao voltage pulses by the low-pass filter made of the choke coil 3 and the capacitor 4, a sinusoidal AC output voltage can be obtained as shown by the curve in Fig. 7B.
The above functional description of the switching power source means of Fig. 6 is based on the assumptions that the switch elements l and 2 perform 2017~3q an exactly rectangular ON-OFF switching operation as ideal switch elements can do, and the control signals for driving the ON-OFF operation are also exactly rectangular. Performance of actual switch elements to 05 be used, however, deviates from the above-mentioned exact rectangular switching operation due to intrinsic characteristics of individual switch elements, which causes certain difficulties during switching operation.
The difficulties during the switching operation will be explained by referring to a typical switch element of a metal oxide semiconductor field effect transistor (MOS-FET) of Fig. 8. MOS-FET's are quite frequently used as the switch elements l and 2 of Fig. 6. The circuit of Fig. 8 is essentially the same as that of Fig. 6 except that MOS-FETl and MOS-FET2 are used as the switch elements l and 2 respectively.
The MOS-FET is different from a conventional bipolar transistor in that the MOS-FET is free from delay in turn-off operation due to storage time caused by residual carriers. Thus, if control signals applied to the gates of MOS-FETl and MOS-FET2 of Fig. 8 are exactly rectangular, simultaneous ON states of the MOS-FETl and MOS-FET2 will never occur. However, the actual MOS-FET has a comparatively large parasitic capacitor between its drain and source on the order of about several hundred pF to several ten pF. At the time of turn-ON and turn-OFF of the paired MOS-FETl and MOS-FET2, there is a serious problem of how to handle the electric charge stored in the parasitic capacitors so as to eliminate adverse effects of the stored charge on the 05 turning ON and turning OFF function.
Fig. 9 shows an equivalent circuit of a MOS-FET.
Due to its configuration, parasitic capacitors are inevitable; namely, Cdg between the gate and the drain, CdS between the drain and the source, and Cgs between the gate and the source. The value of resistance RdS between the drain and the source varies greatly from almost zero to infinity depending on the gate-source voltage, and the zero value corresponds to the ON state and the infinity value corresponds to the OFF state.
A parasitic diode Do must be considered between the drain and the source.
Phenomena relating to the turn-ON and turn-OFF
of the equivalent circuit of Fig. 9 will now be explained. Electric charge stored in the drain-source parasitic capacitor CdS of each MOS-FET is discharged through the drain-source resistance Rds when it is turned ON. Hence, when the paired MOS-FET's are switched over from one to the other, a large surge current is produced. For example, a large surge current flows through the ON-state drain-source resistance RdS Of the MOS-FET2 when the MOS-FET2 is turned ON from its OFF
state. The surge current is due to two reasons, namely, the drain-source parasitic capacitor Cds of the MOS-FET2 is discharged through the ON-state drain-source resist-ance Rds, and the drain-source parasitic capacitor CdS of 05 MOS-FETl is directly charged by the DC voltage source 5 through the ON-state drain-source resistance RdS of the MOS-FET2. Similarly, a large surge current flows through the ON-state drain-source resistance RdS of the MOS-FETl when the MOS-FET2 is turned OFF and the MOS-FETl is turned ON due to the same two reasons as described above.
As a result, the charge stored in the drain-source parasitic capacitor CdS of each MOS-FET of the paired switch elements of Fig. 8 causes a large surge current through the ON-state drain-source resistance RdS
when the two-MOS-FET's are switched over from one to another. The energy of such surge current is converted into and consumed as heat, which means not only power loss and temperature rise of the switch element but also generation of noise. Further, intensity of such phenomenon increases with the increase of the switching frequency of the paired switch elements. Thus, the occurrence of such surge current makes it very difficult to use high frequency switchover of the paired switch 26 elements of the switching power source means. Further, if the peak value of such surge current is too high, ~7~
it may cause break-down of the switch elements.
Several protective methods against the surge current accompanying the switchover of the switch elements have been proposed. Fig. 10A through Fig. 10C
05 illustrate some of them. Gate resistors 8al and 8a2 of several hundred ohms are serially connected to the gates of the MOS-FETl and MOS-FET2 as shown in Fig. 10A.
Functions of such gate resistors include the reduction of the rise-rate of the gate-source voltage of each MOS-FET, the gradual change of the value of the drain-source resistance Rds of each MOS-FET at the time of switchover, and the suppression of the peak value of the surge current even if not eliminated. Fig. 10B shows the case in which two saturable magnetic cores 8bl and 8b2 are connected in series to the MOS-FETl and MOS-FET2, respectively. Snubber circuits 8Cl and 8C2~ each comprising for instance a resistor and a capacitor, are connected in parallel to the MOS-FETl and MOS-FET2, respectively, as shown in Fig. 10C.
The inventors found that the conventional protective methods could not ensure complete prevention of the occurrence of the above-mentioned surge current.
Even if the protective methods are used, electric charge stored in the parasitic capacitors of the MOS-FET's is eventually consumed as heat in the drain-source resist-ance RdS. Thus, with increase of the frequency of switchover of switch elements in the switching power source means, its power consumption or heat generation increases. In short, prevention of occurrence of the surge current and reduction of switching loss at 05 switchover of the switch elements is a very important problem to be solved in the conventional switching power source means.
Therefore, an object of the present invention is to solve the above-mentioned problems of the prior art by providing an improved switching power source means which prevents occurrence of the surge current due to parasitic capacitors of switch elements and of a transformer, if used, so as to enable high efficiency and size reduction of such means.
16 A switching power source means according to the invention has a DC voltage source, a first switch element, a low-pass filter connected to the DC voltage source through the first switch element, and a second switch element connected to the input end of the low-pass filter, in which switch elements are operable in such a manner that a DC output or an AC output at a desired frequency can be produced across the output end of the low-pass filter. Further, an inductor is connected in parallel to one of the switch elements, e.g., the 2~ second switch element, to charge and discharge parasitic capacitors of the switch elements, so as to prevent the B~
20~ 7639 ~ surge currents in the switch elements.
With the inductor connecte~ across the second switch element, no surge current is caused at switchover of the switch elements, and it is made possible to 05 provide a small yet highly efficient switching power source means which is particularly suitable for use in a DC constant-voltage power source, an inverter, an AC
uninterruptible power supply, a battery charger, controllers of motors of various types, and the like.
For a better understanding of the invention, reference is made to the accompanying drawings, in which:
Fig. 1 is a circuit diagram of the first fundamental configuration of a switching power source 1~ means according to the invention;
Fig. 2A shows waveforms of current and voltage at point 7 in the power source means of Fig. l;
Fig. 2B shows current versus efficiency charac-teristics of the power source means of Fig. 1 in the case of producing an AC output;
Fig. 2C shows current versus efficiency charac-teristics of the power source means with a circuit configuration of Fig. 4 in the case of producing a DC
output;
Fig. 3 is a circuit diagram of a forward type power source to which the switching power source means 6~9 of the invention is applied;
Fig. 4 is a circuit diagram of a half-bridge type DC power source to which the switching power source means of the invention is applied;
05 Fig. 5 is a circuit diagram of a full-bridge type power source to which the switching power source means of the invention is applied;
Fig. 6 is a circuit diagram of the essential configuration of a conventional switching power source means;
Figs. 7A and 7B show waveforms of voltages at different points of the essential configuration of Fig. 6;
Fig. 8 is a circuit diagram of the formation of a conventional switching power source means which uses MOS-FET's as switch elements;
Fig. 9 is an equivalent circuit of a MOS-FET;
Fig. 10A through Fig. 10C are circuit diagrams of conventional methods for preventing surge currents in switch elements, respectively;
Fig. ll is a circuit diagram showing the second fundamental configuration of a switching power source according to the present invention;
Fig. 12A is a diagram showing waveforms of voltage at point 7 in the power source of Fig. ll;
Fig. 12B is a diagram showing waveforms of 20 i 7639 inductor current without bias applied in the power source of Fig. 11;
Fig. 12C is a diagram showing waveforms of inductor current with bias applied in the power source of 06 Fig. 11;
Fig. 12D is a diagram showing waveforms o-f current from point 7 in the power source of Fig. 11;
Fig. 13 is a circuit diagram showing the third fundamental configuration of a switching power source according to the present invention;
Fig. 14 is a circuit diagram showing an embodi-ment of a backboost type switching power source according to the present invention;
Fig. 15 is a circuit diagram showing another 16 embodiment of a forward type switching power source according to the present invention;
Fig. 16 is a circuit diagram showing another embodiment of a half-bridge switching power source according to the present invention; and Fig. 17 is a circuit diagram showing another embodiment of a full-bridge switching power source according to the present invention.
- Throughout different views of the drawing, 1, 2, 11, 13, 14 are switch elements (MOS-FET's), 3 is a choke 26 coil, 4, 10, 12, 16 are capacitors, 5 is a DC voltage source, 6 is a load, 7 is a point, 8al, 8a2 are gate .
resistors, 8bl, 8b2 are saturable magnetic cores, 8Cl~ 8C2 are snubber circuits, 9, 15 are inductors, and 9S is a saturable inductor.
The invention will be described in further 05 detail by referring to embodiments.
Fig. 1 shows the basic circuit of a switching power source means according to the invention. In the figure, MOS-FETl and MOS-FET2 are examples of switch elements 1 and 2 of the ensuing embodiments. The output voltage from the switching power source means is controlled by turning ON and turning OFF the switch elements 1 and 2 alternately so as to regulate the duration ratio of ON state and OFF state, as in the case of conventional switching power source means. At each 1~ switchover from one switch element to another, "dead time" is provided during which the two switch elements are both in OFF state.
The embodiment of Fig. 1 is different from the prior art in such a way that a series circuit of an inductor 9 and a capacitor 10 is connected across the second switch element 2 or MOS-FET2 in Fig. 1.
The inductor 9 stores energy in the form of current therein during a half cycle prior to the dead time, and the stored energy is used for charging and discharging 2~ of parasitic capacitors of the switch elements during the dead time. Thus, the internal resistance of the switch elements is freed from adverse effects of charg-ing currents to and discharging currents from parasitic capacitors of the switch elements. A capacitor 10 is used to cut off a DC component in the voltage at point 05 7. The capacitance of the capacitor 10 is selected in such a manner that the resonant frequency of the circuit formed of the inductor 9 and the capacitor 10 is much lower than the switching frequency of the switch elements l and 2. The voltage appearing across the capacitor 10, which is almost constant, depends on both the voltage of the voltage source 5 and time ratio of switching.
In operation, when the MOS-FETl is turned ON, a current is fed from the DC voltage source 5 to the inductor 9 through the ~OS-FETl and energy is stored in the inductor 9. At the moment of turn-o~F of the MOS-FETl, the voltage at point 7 is held by the parasitic capacitors across the switches, hence FETl is turned off with zero voltage switching. The current in the inductor 9 cannot change rapidly and it varies in a continuous manner while charging the drain-source parasitic capacitors Cds of MOS-FETl and discharging the drain source parasitic capacitor Cds of MOS-FET2. Thus, the voltage at point 7 decreases substantially linearly.
2~ After the voltage at point 7 reaches zero, the current in the Lnductor 9 continues to flow through the parasitic diode Do of MOS-FET2 ( see .Fig. 9). In the interval of diode Do conduction , FET2 is turned ON. Thus the zero voltage switching is realized in FET2 at turn-on and there is no current surge. When FET2 is ON, the current 05 from the inductor 9 varies at a certain slope in response to the change of the voltage of the capacitor 10 and changes its polarity.
When the switchover is from FET2 to FETl, the - same kind of zero voltage switching arises. In this case, however, the direction of the current from point 7 has been reversed. When MOS-FET2 is turned OFF, parasitic capacitor CdS of MOS-FET2 is charged and parasitic capacitor Cds of MOS-FETl.is discharged by the energy stored in the inductor 9. AS a result, the voltage at point 7 increases gradually until it reaches to the voltage of the voltage source 5. Zero voltage switching is therefore realized at turn-off of FET2.
After the voltage at point 7 reaches to the voltage of voltage source 5, the energy in the inductor 9 is recovered to the voltage of the source 5 through the parasitic diode Do of the MOS-FETl. During the conduction of diode Do of MOS-FETl, FETl is turned ON.
Hence zero voltage switching in FETl is realized, too.
When FETl is ON, the current in the inductor 9 increases with a certain slope, and changes its polarity. Next, the same operation is repeated. The charging and B
discharging of the parasitic capacitors of the MOS-FET's through the drain-source resistors Rds Gf the MOS-FET's is prevented by the energy stored-in the inductor 9.
The voltage at and the current from point 7 will 05 be discussed now in detail. The upper graph of Fig. 2A
shows the theoretical waveform of voltage at point 7 r while the lower graph of Fig. 2A shows the theoretical waveform of current from point 7. In the two graphs, solid lines are for no-load conditions and dash lines are for loaded conditions. Fig. 2B and Fig. 2C show measured values of efficiency versus load current Io characteristics for the configura~ion of Fig. l and for the configuration of Fig. 4, respectively. High efficiency of the means of the invention was proved;
namely, about 95% for the case of Fig. 2B and about 85%
for the case of Fig. 2C.
In Fig. l, if the voltage of the voltage source 5 is represented by Ei and the time ratio of the ON
period of the switch element 1 is represented by Dr a voltage DEi appears across the capacitor 10. If the inductance of the inductor 9 is designated by L,-!the switching frequency is designated by f and the output current is designated by Ior the peak current ILmaX of the inductor 9, i.e., the current through inductor 9 when both of MOS-FETl and MOS-FET2 are OFF, can be given by the following equation.
~, .~ -....
ILmaX=Ei(l-D)D/2fL ........... (1) In deriving the equation (1), one assumption was used;
namely, the switchover time between the switch elements 1 and 2 is sufficiently short as compared with the ON
06 time of the switch element 1 or 2.
The current i through point 7 can be given by the following equation (2) for the ON time of the MOS-FETl and by the following equation (3) for the ON time of the MOS-FET2.
i=[Ei(l-D)t/L]-[D(l-D)Ei/2 f L]+Io ....... ..... (2) i=[Ei D t/L]~[D(l-D)Ei/2 f L]+Io ......... (3) When the MOS-FETl or the MOS-FET2 is switched from the ON state to OFF state, the parasitic capacitors of the MOS-FETl and MOS-FET2 are charged by the energy - 16 stored in the inductor 9, and the voltage at polnt 7 varies. If the total capacitance of the entire drain-source parasitic capacitors of the MOS-FETl and MOS-FET2 as seen from point 7 is represented by C, the internal resistance of the inductor g is rep~esented by r, and the current of the inductor 9 at turn-off time of the MOS-FET's is represented by IL~ then the voltage u at point 7 and the current i through point 7 can be given by the following equations (4) and (5) for switchover of ON
state from MOS-FETl to MOS-FET2 and by the following 26 equations (6) and (7) for switchover of ON state from MOS-FET2 to MOS-FETl.
~ 20 1 7639 u=e~at[(Ei-Ec+rIL)cos~t+{a(Ei-Ec+rIL) -(IO+IL)/C} (l/~)sin~t]+(Ec-rIL) ......... (4) i=e~at[(IO+IL)cos~t +{(Ei-Ec)/L-a(IO+IL)} (1/~)sin~t] ............. (5) 05 u=e~at[(-Ec+r IL ) cos~t+{a(-Ec+r IL ) -(-IO+IL)/C}-(l/~)sin~t]+(Ec-rIL) ............. (6) i=e~at[(-IO+IL)cos~t +{(-Ec)/L+a( Io+IL ) } ( 1~ ) sinwt] .. ..(7) where, a=r/2L and ~=~J1/LC-1.
If the internal resistance r of the inductor 9 is sufficiently small and the time necessary for the voltage at point 7 to change into its next state is sufficiently short as compared with the intrinsic period of LC, the above equations (4) through (7) can be 16 simplified as the following expressions (8) through (ll) with a sufficient degree of approximation, respectively.
For the switchover of ON state from MOS-FET1 to MOS-FET2 u=Ei-( Io+ILmax ) t/c ---- (8) i=Io+ILmax+ ( Ei-Ec)-t/c ......... (9) For the switchover of ON state from MOS-FET2 to MOS-FETl U=(ILmax--Io)-t/c ......................... (10) i= ( ~Io+ILmax ) -Ec t/c ................ (ll) The equations (8) through (ll) show that the variation of the voltage at point 7 is substantially 2~ linear. With the condition for positive slope of the voltage of the equation (10), the peak value ILmaX of the ~'; .
~ 201 7639 -inductor current and the load current Io must-~satisfy the following conditions.
io<ILmax=Ei(l-D)D/2-f-L .......... (12) During the switchover of the voltage at point 7, 05 the two MOS-FET's must be simultaneously OFF, and the dead time Td during which both of the two MOS-FET's are OFF can be derived as follows from the equation (ll).
Td2Ei C/(Io~ILmax) ............... (13) As can be seen from the foregoing description, with the circuit configuration of the invention, it is possible to completely eliminate surge currents due to the charging and discharging of parasitic capacitors of the switch elements through the internal resistances of such switch elements at switchover of-switch elements.
Further, values of constants necessary in the invention such as the inductance of the inductor 9 and the duration of the dead time can be determined by use of the simple equations.
With the prior art, several methods have been used to protect switch elements against the surge current at the time of switchover of the switch elements and to prevent noise in the voltage and current due to such surge currents; namely, connection of gate resistors of several hundred ohms to the gates of MOS-FET's for reducing the rate of rise of the gate voltage,suppression of the current peak value by gradually ~9 reducing the drain-source resistance of the MOS-FET to its complete ON state at the time of its turn-ON, and use of means for preventing sudden changes of voltage and current such as the snubber circuits formed of 05 resistors and capacitors. However, such conventional methods could not ensure complete elimination of the surge current, and the electric charge stored in the parasitic capacitors of the MOS-FET's are eventually consumed in the ON-state drain-source resistance of each MOS-FET. Thus, with the increase of frequency of the switchover of the switch elements, problems of increased power consumption and increased heat generation are inevitable, and such problems have not been solved.
In the above description of the principles of the invention, MOS-FETl and MOS-FET2 are used as examples of the switch elements 1 and 2. When bipolar transistors, gate turn off transistors (GTO), or regular thyristors are used as the switch elements of the switching power source means, parasitic capacitors of such transistors and thyristors also cause problems similar to those related to the MOS-FET'S. The inven-tion can solve the problems accompanying with the use of the above transistors and thyristors.
Thus, the invention can reduce the number of 26 surge absorbing elements in the switching power source means compared with the conventional power source means 201 763~
of similar type. Since the power consumption at the time of switchover can be kept low, the frequency of the switchover can be increased, and various components such as the smoothing choke coils and capacitors can be made 05 small. When applied to the output voltage control, the invention can permit a faster response and facilitate more sophisticated fine control of the output voltage.
Other embodiments will be described now. Fig. 3 shows a forward type switching power source to which the present invention is applied. Switch elements 1 and 2 are paired, and when one of them is ON the other is controlled to be OFF. A switch element 11 is so controlled as to turn-ON and turn-OFF substantlally simultaneously with the switch element 1. During switchover of the switch elements 1, ll and 2, the energy stored in the inductor 9 is used to charge and discharge parasitic capacitors of such switch elements 1, ll, 2 and a transformer Tl.
Fig. 4 shows a half-bridge type power source, in which output end of a switching power source means of the invention is connected to the primary winding of a transformer T2 and the output is rectified by diodes D2 and D3 that are connected to the secondary winding of the transformer T2, so as to provide a DC output.
as Switch elements l and 2 are paired, and when one of them is ON the other is controlled to be OFF. The power B
- ~ 201 763q source of Fig. 4 uses a capacitor 12 for cutting off the DC component of the output from the switching power source means of the invention. During switchover of the switch elements 1 and 2, the energy stored in the 05 inductor 9 is used to charge and discharge parasitic capacitors of such switch elements 1, 2 and the transformer T2. Parasitic capacitors across terminals of the diodes D2 and D3 are also charged and discharged by the energy stored in the inductor 9, and surge currents due to recovery currents (reverse direction currents caused during the switchover) never occur.
Fig. 5 shows a full bridge inverter circuit.
The AC voltage produced by the switching power source means of the invention is applied to the primary winding lB of a transformer T3, and rectified by diodes D2 and D3 connected to the secondary winding of the transformer T3. Switch elements 1 and 2 are paired, and switch elements 13 and 14 are similarly paired. When one of the paired switch elements is ON the other one of the paired switch elements is controlled to be OFF. A DC
output of any desired magnitude can be produced by controlling phase difference between the switching element 1-2 pair and the switching element 13-14 pair.
In this embodiment, the energy stored in inductors 9 and 15 is used to charge and discharge parasitic capacitors of the switch elements, the transformer, and the diodes during switchover of the switch elements.
The switch elements 1, 2, 13 and 14 in the embodiments of Fig. 3 through Fig. 5 can be MOS-FET's, bipoIar transistors, GTO's, thyristors, or diodes.
06 In the embodiments as described hereinbefore in detail, the wattless current IL as indicated by solid lines in the lower graph of Fig. 2A, which flows through - the inductor 9 employed in the funda~lental configuration as shown In Fig. 1, flows through within the switch elements FETl and FET2. So that, the losses in the equivalent resistances within the switch circuits and the losses in ON-state drain-source resistance of switch elements are increased. Furthermore, in order to effectively charge and discharge the parasitic 16 capacitors across the switch elements, it is required that the amplitude value ILmaX of the inductor current should be larger than that of the load current Io~ as described before.
On the other hand, a current corresponding to the sum of the load current Io and the inductor current IL~ that is, the current indicated by dash lines in the lower graph of Fig. 2A flows from point 7 in the fundamental configuration as shown in Fig. 1, and, as a result, a peak current equal to twice of the load 26 current Io flows through the switch elements FETl and FET2 on the maximum load. Therefore, it is required to ;~:`St '-select semiconductor devices having a large current capacity for the switch elements FETl, FET2. Moreover, a wattless current with a peak value larger than the load current Io always flows through the inductor 9.
05 Hence it is required to increase the diameter of the windings of the inductor 9 for reducing the power loss caused on the inductor 9.
In order to remove the above-mentioned defects of the switching power source of inductor-current diversion type based on the fundamental configuration as shown in Fig. 1 according to the present invention, in which an inductor is connected in parallel with switch elements to divert the charging and discharging currents of parasitic capacitors of those switch elements into 1~ an inductor current, a saturable core is used for the inductor concerned, so as to give a non-linear property thereto and hence to make the most of the merit of the inductor-current diversion. Moreover, if the induct~or made of the saturated core is further provided with an additional winding through which the load current flows, so as to be applied with a bias in response to the load current, the most profitable charging and discharging current required for the inductor-current diversion can be always obtained.
The second fundamental configuration of the improved switching power source of the present invention . . ; .
is shown in Fig. ll. In the original fundamental configuration, when switch element FETl is in ON-state, the voltage stored in the parasitic capacitor across the drain and the source of the switch element FETl is zero, 05 while the source voltage Ei is applied to the parasitic capacitor across the drain and the source of switch element FET2. In this condition, when the switch element FETl is turned OFF at a fairly high switching speed, the switching is completed in a condition such as the electric.charge stored in the parasitic capacitor across the drain and the source of the switch element FETl is substantially zero. However, when switch element.FET2 is turned ON immediately after the switch element FETl is turned OFF, both of the discharge current of the parasitic capacitor of FET2 and the charge current of the parasitic capacitor of FETl flow through the conduction resistance of switch element FET2. As a result, an abrupt large surge current is generated within the switch element FET2 r and hence the heat and the noise are further generated.
In contrast therewith, in the improved fundamental configuration, a saturable inductor 9S is connected across the switch element FET2, so that the core of the inductor 9S is saturated a little while a5 before one of switch elements, for instance, FETl is turned OFF. As a result, an inductor current in such B?
~ an operational waveform as-shown in Fig. 12B flows through the saturable ind-~ctor 9S. Figs 12A through 12D
show several operational waveforms in the improved fundamental configuration. In other words, during the 06 saturation of the saturable inductor 9S, a current supplied from the DC voltage source 5 through the switch element FETl is stored in this saturated inductor 9S
When a dead time duration having a suitable time length is provided after the switch element FETl is turned OFF, the current flowing through the saturable inductor 9S
tends to maintain the present state of current flow.
Hence, the electric charge stored in the parasitic capacitor across the drain and the source of the switch element FET2 is discharged, while the parasitic 16 capacitor across the drain and the source of the switch element FETl is charged by the peak of this maintained current. As a result, the terminal voltage across the switch element FET2 decreases with a certain inclina-tion. If switch element FET2 is turned ON after this terminal voltage reaches to zero, the zero voltage switching can be realized.
Moreover, even when the ON state is switched over from the switch element FET2 to the switch element FETl on contrary to the above, the zero voltage 2~ switching similar to the above can be realized by providing the dead time duration having the suitable B
L
time length similar to the above, and furthermore, since the current flowing through the inductor 9S is the wattless current, those currents flowing to charge and to discharge the parasitic capacitors do not cause any 06 power loss at all. Furthermore, since the inclination of the variation of terminal voltages across the switch elements FETl and FET2 is determined by the capacitance of the parasitic capacitors across those elements, the peak value ILmaX of the inductor current, and the load current Io,-the power loss and the noise which are caused by the abrupt change of the current or the voltage, that is, the surge current or the surge voltage, can be prevented by selecting suitable values of those causing factors.
16 In this connection, the current, which charges or discharges the parasitic capacitors across the switch elements FETl and FET2, corresponds to the sum of the inductor current IL and the load current Io in case the ON
state is switched over from the switch element FETl to the switch element FET2, while the current concerned corresponds to the difference between the inductor current IL and the load current Io in case the ON state is switched over from the switch element FET2 to the switch element FETl. Consequently, if the peak values 26 of the inductor currents IL flow through the current-diversion inductor 9S are equal to each other, the ~. .
`~ ` 201 7639 inclination of the terminal voltage across the switch element becomes steep in case the ON state is switched over from the switch element FETl to the switch element FET2, while the inclination concerned becomes gentle.
05 As a result, when the load current Io exceeds the peak value ILmaX Of the inductor current, the current diversion through the inductor 9S cannot be realized.
However, the aforesaid difficulty can be removed by providing the core of the saturable inductor 9S with an additional winging through which the load current Io flows, so as to apply a bias responding to the load current Io to the saturable core concerned. An example of the configuration of the switching power source of the present invention in which the core of the saturable 16 inductor 9S is applied with;the bias responding to the load current Io is shown in Fig. 13, while the waveforms of the induct~r current IL and the current flowing from point 7 in the example as shown in Fig. 13, are shown in Figs. 12C and 12D respectively. In the configuration as shown in Fig. 13, which is arranged so that the bias responding to the load current is applied to the core of the saturable inductor 9S, the positive peak value of the inductor current IL is decreased, while the negative peak value thereof is increased, as shown in Figs. 12C and a5 12D. As a result, the saturable core is appropriately biased, such that an excessive peak current flowing ~ . .
20 1 763~
.
through the switch elements on the bias of the increased load current Io can be prevented, as well as the charging current or the discharging current of the parasitic capacitor, which is required for thei-inductor 05 current diversion, can be provided. Furthermore, at the instant at which the terminal voltages across the switch elements are switched over between each other, the current flowing from point 7 is maintained at constant, so that the inclination of the voltage variation at this instant is maintained at constant, too, and hence the noise caused by the abrupt change of the voltage can be prevented, too.
As described above, in the inductor current diversion type switching power source of the present invention, a saturable core is used for the current diversion ~Inductor~ so that the condition required for realizing the charge and the discharge of parasitic capacitors across the switch elements is always satisfied, and hence it is possible to prevent the power - 20 loss caused by the larger wattless current which tends to be generated when the current diversion inductor is formed of an air-cored linear inductor without satur-ation of core.
The principle of the improvement of the switch-2~ ing power source according to the present invention,which is referred to the improved fundamental configura-tion shown in Fig. 11, provided by modifying the original fundamental configuration shown in Fig. 1, can be generally applied to any kind of switching power source in which paired switch elements are controlled to 05 be alternately switched over. Therefore, the embodi-ments of the present invention which are referred to Figs. 3 to S provided by modifying the original fundamental configuration as shown in Fig. 1 can be applied with the same principle of improvement together with the same effect. For example, an embodiment of the switching power source according to the present inven-tion, in which the aforesaid principle of improvement is applied to a power source of backboost type, is shown in Fig. 14, another embodiment thereof, in which the 16 aforesaid principle of improvement is applied to a forward type power source as shown in Fig. 3, being shown in Fig. 15, another embodiment thereof, in which the aforesaid principle of improvement is applied to an inverter rectifying DC power source as shown in ao Fig. 4, being shown in Fig. 16, and another embodiment thereof, in which the aforesaid principle of improvement is applied on a full-bridge type power source as shown in Fig. 5, being shown in Fig. 17. In other words, the principle of improvement according to the present 26 invention can be generally applied to the switching power sources of this kind including various bridge type 2~1~9 power sources and hence similar effects of improvement can be obtained.
As can be seen from the foregoing detailed description, the outstanding effects of the invention 05 can be summarized as follows.
(l) A high efficiency of electric power in the switching power source means is achieved.
(2) Due to the reduction of heat generation at constituent elements, heat dissipating fins and other fringe parts can be made small.
(3) Reliability of the constituent elements is improved because surge currents are substantially eliminated.
(4) Need of conventional fringe elements such as snubber circuits and noise filters can be removed.
(5) Higher switching frequencies than before can be used, and size of circuit elements such as transformers and filters can be reduced.
(6) Any excessive voltage is not applied to constituent elements, so that semiconductor devices having low voltage-endurance can be employed for those constituent elements.
(7) The regulation of the output of the switching power source means is accomplished by 20~76~9 controlling the ON-OFF duty ratio of the switch elements.
Although the invention has been described with a certain degree of particularity, it is understood that 05 the present disclosure has been made only by way of example and that numerous changes in details of construction and parts may be resorted to without departing from the scope of the invention as hereinafter claimed.
ao
Although the invention has been described with a certain degree of particularity, it is understood that 05 the present disclosure has been made only by way of example and that numerous changes in details of construction and parts may be resorted to without departing from the scope of the invention as hereinafter claimed.
ao
Claims (9)
1. A switching power source, comprising:
a DC voltage source;
a first switch element connected to said DC voltage source;
low-pass filter means having an output end for connection to a load and an input end selectively connectable to said DC voltage source through said first switch element;
a second switch element connected in parallel relative to the input end of said low-pass filter means, said first and second switch elements having parasitic capacitors and being turned on and off so that an output signal of desired frequency is produced at the output end of said low-pass filter means;
an inductor connected in parallel with said second switch element for charging and discharging said parasitic capacitors during a switching operation when said first switch element is switched off and said second switch element is switched on, and vice versa; and a capacitor connected in series with said inductor so that the series connection of said inductor and said capacitor is in parallel with said second switch element, wherein said first and second switch elements have a common connection point, and the series connection of said inductor and said capacitor is connected to said common connection point, wherein said inductor is provided with a saturable core for giving a nonlinear property to said inductor, said saturable core provided in said inductor is provided with an additional winding through which a load current flows for applying a bias responding to the load current on said saturable core.
a DC voltage source;
a first switch element connected to said DC voltage source;
low-pass filter means having an output end for connection to a load and an input end selectively connectable to said DC voltage source through said first switch element;
a second switch element connected in parallel relative to the input end of said low-pass filter means, said first and second switch elements having parasitic capacitors and being turned on and off so that an output signal of desired frequency is produced at the output end of said low-pass filter means;
an inductor connected in parallel with said second switch element for charging and discharging said parasitic capacitors during a switching operation when said first switch element is switched off and said second switch element is switched on, and vice versa; and a capacitor connected in series with said inductor so that the series connection of said inductor and said capacitor is in parallel with said second switch element, wherein said first and second switch elements have a common connection point, and the series connection of said inductor and said capacitor is connected to said common connection point, wherein said inductor is provided with a saturable core for giving a nonlinear property to said inductor, said saturable core provided in said inductor is provided with an additional winding through which a load current flows for applying a bias responding to the load current on said saturable core.
2. A switching power source as defined in claim 1, wherein said first switch element has an electrode connected to a positive pole of said DC voltage source and said second switch element has an electrode connected to a negative pole of said DC voltage source.
3. A switching power source, comprising:
a DC voltage source;
a first switch element connected to said DC voltage source;
low-pass filter means having an output end for connection to a load and an input end selectively connectable to said DC voltage source through said first switch element;
a second switch element connected in parallel relative to the input end of said low-pass filter means, said first and second switch elements having parasitic capacitors and being turned on and off so that an output signal of desired value is produced at the output end of said low-pass filter means;
an inductor connected in parallel with said second switch element for charging and discharging said parasitic capacitors during a switching operation when said first switch element is switched off and said second switch element is switched on, and vice versa;
a transformer connected between said first switch element and said low-pass filter means, wherein said inductor is provided with a saturable core for giving a nonlinear property to said inductor, and said saturable core provided in said inductor is provided with an additional winding through which a load current flows for applying a bias responding to the load current on said saturable core.
a DC voltage source;
a first switch element connected to said DC voltage source;
low-pass filter means having an output end for connection to a load and an input end selectively connectable to said DC voltage source through said first switch element;
a second switch element connected in parallel relative to the input end of said low-pass filter means, said first and second switch elements having parasitic capacitors and being turned on and off so that an output signal of desired value is produced at the output end of said low-pass filter means;
an inductor connected in parallel with said second switch element for charging and discharging said parasitic capacitors during a switching operation when said first switch element is switched off and said second switch element is switched on, and vice versa;
a transformer connected between said first switch element and said low-pass filter means, wherein said inductor is provided with a saturable core for giving a nonlinear property to said inductor, and said saturable core provided in said inductor is provided with an additional winding through which a load current flows for applying a bias responding to the load current on said saturable core.
4. A switching power source as defined in claim 3, wherein said transformer has a primary circuit and a secondary circuit, said DC voltage source and said first switch element being connected in said primary circuit, and said second switch element and said inductor being connected in said secondary circuit.
5. A switching power source, comprising:
a DC voltage source;
a first switch element connected to said DC voltage source;
low-pass filter means having an output end for connection to a load and an input end selectively connectable to said DC voltage source through said first switch element;
a second switch element connected in parallel relative to the input end of said low-pass filter means, said first and second switch elements having parasitic capacitors and being turned on and off so that an output signal of desired value is produced at the output end of said low-pass filter means;
an inductor connected in parallel with said second switch element for charging and discharging said parasitic capacitors during a switching operation when said first switch element is switched off and said second switch element is switched on, and vice versa;
a transformer connected between said first switch element and said low-pass filter means, a third switch element connected in series with both said second switch element and said inductor, said third switch element being controlled to turn on and off substantially simultaneously with said first switch element, and said third switch element and said transformer having parasitic capacitors which are charged and discharged by said inductor;
wherein said inductor is provided with a saturable core for giving a nonlinear property to said inductor, and said saturable core provided in said inductor is provided with an additional winding through which a load current flows for applying a bias responding to the load current on said saturable core.
a DC voltage source;
a first switch element connected to said DC voltage source;
low-pass filter means having an output end for connection to a load and an input end selectively connectable to said DC voltage source through said first switch element;
a second switch element connected in parallel relative to the input end of said low-pass filter means, said first and second switch elements having parasitic capacitors and being turned on and off so that an output signal of desired value is produced at the output end of said low-pass filter means;
an inductor connected in parallel with said second switch element for charging and discharging said parasitic capacitors during a switching operation when said first switch element is switched off and said second switch element is switched on, and vice versa;
a transformer connected between said first switch element and said low-pass filter means, a third switch element connected in series with both said second switch element and said inductor, said third switch element being controlled to turn on and off substantially simultaneously with said first switch element, and said third switch element and said transformer having parasitic capacitors which are charged and discharged by said inductor;
wherein said inductor is provided with a saturable core for giving a nonlinear property to said inductor, and said saturable core provided in said inductor is provided with an additional winding through which a load current flows for applying a bias responding to the load current on said saturable core.
6. A switching power source as defined in claim 5, and further comprising:
a capacitor connected in series with said inductor so that the series connection of said inductor and said capacitor is in parallel with said second switch element;
wherein said transformer has a primary circuit and a secondary circuit, and said DC voltage source, first and second switch elements and series connection of said capacitor and inductor are all connected in said primary circuit, and said secondary circuit includes diode means for rectifying the output signal to produce a DC output, wherein said inductor is provided with a saturable core for giving a nonlinear property to said inductor.
a capacitor connected in series with said inductor so that the series connection of said inductor and said capacitor is in parallel with said second switch element;
wherein said transformer has a primary circuit and a secondary circuit, and said DC voltage source, first and second switch elements and series connection of said capacitor and inductor are all connected in said primary circuit, and said secondary circuit includes diode means for rectifying the output signal to produce a DC output, wherein said inductor is provided with a saturable core for giving a nonlinear property to said inductor.
7. A switching power source as defined in claim 5, and further comprising:
a first capacitor connected in series with said inductor so that the series connection of said inductor and said first capacitor is in parallel with said second switch element; and wherein said first and second switch elements have a common connection point and further comprising a second capacitor connected between said common connection point and said transformer, wherein the output regulation of said switching power source is accomplished by pulse-width modulation.
a first capacitor connected in series with said inductor so that the series connection of said inductor and said first capacitor is in parallel with said second switch element; and wherein said first and second switch elements have a common connection point and further comprising a second capacitor connected between said common connection point and said transformer, wherein the output regulation of said switching power source is accomplished by pulse-width modulation.
8. A switching power source as defined in claim 5, wherein said transformer has a primary circuit including a primary winding and said first and second switch elements have a common connection point connected at one end of said primary winding, and further comprising third and fourth switch elements having a common connection point connected at the other end of said primary winding and a second inductor connected to said common connection point so as to be in parallel with said fourth switch element, said third switch element being connected to said DC voltage source, wherein said third and fourth switch elements and said second inductor operate similarly to said first and second switch elements and said inductor, respectively, to produce a full bridge inverter circuit, wherein the output regulation of said switching power source is accomplished by pulse-width modulation.
9. A switching power source as defined in claim 8, and further comprising a first capacitor connected in series with said inductor so that the series connection of said first capacitor and said inductor is in parallel with said second switch; and a second capacitor connected in series with said second inductor, the series connection of said second capacitor and said second inductor being in parallel with said fourth switch element, wherein said inductor is provided with a saturable core for giving a nonlinear property to said inductor, and said saturable core provided in said inductor is provided with an additional winding through which a load current flows for applying a bias responding to the load current on said saturable core, wherein the output regulation of said switching power source is accomplished by pulse-width modulation.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1234577A JPH06101930B2 (en) | 1988-09-16 | 1989-09-12 | Switching power supply |
| JP1-234,577 | 1989-09-12 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2017639A1 CA2017639A1 (en) | 1991-03-12 |
| CA2017639C true CA2017639C (en) | 1995-07-11 |
Family
ID=16973196
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA 2017639 Expired - Fee Related CA2017639C (en) | 1989-09-12 | 1990-05-28 | Switching power source means |
Country Status (2)
| Country | Link |
|---|---|
| CA (1) | CA2017639C (en) |
| DE (1) | DE4019158C2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107340416B (en) * | 2017-08-28 | 2020-04-14 | 国网江西省电力公司电力科学研究院 | A distribution network fault indicator LC tuning external signal source |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| AT386096B (en) * | 1985-11-28 | 1988-06-27 | Schrack Elektronik Ag | FLOW CONVERTER WITH A DC INPUT CIRCUIT |
| US4672303A (en) * | 1986-08-28 | 1987-06-09 | International Business Machines Corporation | Inductor current control circuit |
-
1990
- 1990-05-28 CA CA 2017639 patent/CA2017639C/en not_active Expired - Fee Related
- 1990-06-15 DE DE19904019158 patent/DE4019158C2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CA2017639A1 (en) | 1991-03-12 |
| DE4019158A1 (en) | 1991-03-21 |
| DE4019158C2 (en) | 1994-04-21 |
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